JPS61161839A - Frame aligner circuit - Google Patents

Abstract

PURPOSE:To minimize the destruction of data by shifting a location of a shift register section from which an output is extracted depending on the kind of a slip signal transmitted from a bit buffer section to use a word end part as a normal location. CONSTITUTION:A bit buffer section 4 counts T line data from a terminal device by using a T line clock and sends it to a shift register 5 and a head word signal T-MF is inputted to a counter decoder 7. When a signal has a slip, the bit buffer section 4 sends a write/read slip signal W or R to a control section 9. A counter decoder section 7 counts the 1st T-MF signal for the next MF signal by using a subscriber line clock. The control section 9 obtains a slip amount by using a signal from the decoder section 7 and the subscriber line MF signal, sends it to the selector section 6 together with the R or W signal, the ends of words are arranged and fed to the multiplex section. Thus, the destruction of data is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a frame aligner circuit included in a subscriber line termination device that connects a data terminal to a data network.

FIG. 4 shows a block diagram of a subscriber system transmission device, and FIG. 5 shows a frame configuration diagram of FIG. 4.

In Fig. 4, for example, data (hereinafter referred to as T-line data) from a data terminal (hereinafter abbreviated as DTE) 2 is input to a subscriber line termination unit (hereinafter abbreviated as DSU) 2. The frame structure is 1 as shown in Figure 5(a).
A burst consists of, for example, 20 words, and the first word is indicated by the T line MF signal.

On the other hand, since the equipment in the station operates on a second clock (hereinafter abbreviated as subscriber line clock) that has a different phase relationship with the first clock used in DTE 1 (hereinafter abbreviated as T-line lock), the DSU DTf in 2! The T-line data input from 1 is synchronized with the subscriber line clock sent from within the station, and the subscriber line liver signal indicating the position of the first word (a signal indicating the beginning of data using the second clock) is synchronized. After matching the first word of the T-line data to the position and converting it into subscriber line data (see FIG. 5 (bl)), the data is added to the multiplexing unit via an in-office terminal unit (hereinafter abbreviated as OCU) 3.

The frame aligner circuit is the part that performs the above conversion, but for the subscriber line side clock. When the jitter of the terminal clock exceeds its tolerance, a slip occurs in which part of the data is missing or duplicated, and the data is erroneous from that point until the end of the burst.

Therefore, there is a need for a frame aligner circuit that can minimize data errors even if a slip occurs.

[Conventional technology]

FIG. 6 shows a block diagram of a conventional example of a frame aligner circuit, and FIG. 7 shows a time chart of FIG. 6.

In FIG. 6, the T-line data synchronized with the T-line clock is read out at the falling point of the subscriber line clock in the bit buffer unit 4, so that the T-line data synchronized with the subscriber line clock is converted into T-line data synchronized with the subscriber line clock. It is converted and input to the shift register section 5 (see FIGS. 7(a) and 7(b)).

Note that the data format is that l word consists of n bits, and (1) in Figure 7 (bl) is, for example, #1 word from 1 to n shown in Figure 5, followed by #2 and #3. The words ``...'' continue.

The counter section 7 receives T iM from the bit buffer section 4.
After resetting the counter section with the F signal detection signal (first detection signal), counting of the subscriber line clock is started again (see FIG. 7 (C1, (d)).

The decoder unit 8 outputs a count value (for example, 4
) (see FIG. 7(e)).

With this, the difference between the T line MF signal and the subscriber line MP double signal is 4.
Now that we know that there are enough clocks, we can control the selector unit 6 to take out the output (4) from the shift register unit 5.
T-line data in which the first word is located at the position specified by the subscriber line liver signal is obtained (see FIG. 7(f)).

[Problem that the invention seeks to solve]

As mentioned above, in order to synchronize the T-line data synchronized with the T-line lock to the subscriber line clock, the T-line data is read by the subscriber line clock, but the T-line lock is the subscriber line clock. If the clock oscillates due to jitter that cannot be absorbed by the bit buffer, the converted data will be incorrect, with some parts missing or increased.

The former is called a write slip, and the latter is called a read slip, but in either case, the problem is that when an error occurs, an error will occur in the multiplexed data from that point until the end of the burst. There is.

[Means for solving problems]

The problem mentioned above is that the function converts data synchronized with the first clock into data synchronized with the second clock, and also generates a slip signal indicating the occurrence of an error when an error occurs during data conversion. and a bit buffer section having a function of detecting a valley in the signal when a signal indicating the beginning of data synchronized with the first clock is input and sending out a first detection signal; and the bit buffer section. a shift register unit that shifts and stores data synchronized with the second clock output from the second clock; and a shift register unit that is reset by the input first detection signal until it is reset again by the first detection signal. , a counter decoder unit that counts the second clock, and a shift register unit that corresponds to the count value when a signal indicating the beginning of data using the second clock is detected when no slip signal is input. a control unit that controls a selector unit so that when an output is selected and input to the slip signal, the output of the shift register unit corresponding to the slip signal is selected; This problem is solved by the frame aligner circuit of the present invention, which comprises a selector section that selects the parallel outputs of.

[Effect]

In the present invention, by shifting the position at which the output is taken from the shift register section in accordance with the type of slip signal sent from the bit buffer section, the end portion of the word that is shifted from the normal position due to the occurrence of a slip is corrected. I made it so that it came to the position of . This eliminates errors in subsequent output data.

Conventionally, the position from which the output is taken from the shift register section was fixed regardless of the presence or absence of a slip, so when a slip occurs, the bit position will deviate from the normal position from then on until the burst ends2.For example, in the worst case. The data for 20 words becomes an error.

However, in the present invention, the position at which the output is taken from the shift register section is changed in response to the slip that occurs, so that the end position of the word is at the normal position.
~ Only 2 words of data are wrong, other words are not wrong,
Data corruption can be minimized.

〔Example〕

The present invention will be specifically explained below with reference to illustrated examples. still,
The same reference numerals indicate the same objects throughout the figures.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of the control section.

In this figure, for simplicity, 1 word = 4 bits, and (4) on the left side is the count value between the T-line MF signal and the joining i-line MF signal, same as (4) in Fig. 7(b). shows.

Since the operation of the frame aligner circuit when the bit buffer unit l is converting data without slip has already been explained, the case where a slip occurs during data conversion will be explained.

(2) When data is lost For example, assume that the first bit of the subscriber line clock is lost and the third bit of the #1 word is lost, but the conversion from the #2 word onwards is performed normally. At this time, as shown in (3) of FIG. 2(a), the word is shifted one bit to the left of the ↓ mark that indicates the end of each word when normal conversion is performed.

Therefore, in order to return this to its normal position, the slip signal (W
-5lip) is added to the control unit 9, if the control unit 9 controls the selector unit 6 so that the output of the shift register unit 5 that was taken from (3) is taken from (4), the #2 word is Although there is an error, normal data can be changed after word #3.

■ When the amount of data increases, for example due to noise, read the same T-line data twice and read the second
As shown in (4) of Figure (b), the end position of the data is shifted to the right. Note that ↓ indicates the end position of normal data as above.

In this case, if the output of the shift register unit 5 that was taken from (4) is taken from (3), the data from #3 onwards will become normal data.

FIG. 3 shows a professional hook diagram of an example of the control section shown in FIG.

In the figure, 10 is a flip-flop (hereinafter referred to as D-FP).
(abbreviated as ), 11 indicates a switch, and since, for example, 10 identical circuits are connected in parallel, the operation of 1 will be explained.

First, each switch 11-1... LS representing a hard slip, R5 representing a write slip, PL representing a subscriber line MP signal, and ST representing a memory retention.
One type of control signal among the types of control signals is applied, and the decoded output from the counter decoder section 7 is only the switch 11-1 when the count value is 1, and the switch 11-1 when the count value is 2.
-2 only...becomes 1.

Here, when the subscriber line liver signal is input, the control signal PL
is applied to each switch, and the decoded output is selected by each switch. For example, if the count value is 4, D -FF
10-4 reads 1.

Therefore, the terminal LS of the switch 10-3, the terminal R3 of the switch 10-5, and the output terminal (4) become 1. Next, the control signal S
When T is added, a signal flows as shown by the arrow and FFl0-
4 is self-maintained.

Note that the remaining output terminals are O.

For this reason, the output of the switch 11-4 is set to the selector section 6 in FIG.
As shown in FIG. 7(b), the shift register section 5
Only the output (4) of is selected.

Next, when a control signal LS is applied because a slip occurs and the focus increases, the signal applied to the terminal LS of the switch 11-3 is transferred to the D-FF via the switch 11-3.
Since it is added to 10-3, output terminal (3) and switch 11
The terminal LS of -2 and the terminal R3 of 11-4 become 1, and the output terminals of the other switching devices become 0.

As a result, the output of the shift register section 5 changes from (4) to (
3) and the data one bit before is selected.

Also, when a bit is missing, the control signal R5 is applied, so the output terminal (5) of only the switch 11-5 becomes 1 in the same procedure as above, so the output of the shift register section 5 becomes (4). ) to (5) and the data one bit after is selected.

As a result, 1-2. Since the data becomes normal in words, it is no longer possible for one burst to be entirely erroneous.

〔Effect of the invention〕

As described above in detail, according to the present invention, data corruption at the time of bit slip can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the control section, FIG. 3 is a program diagram of the control section, and FIG. 4 is a program diagram of the subscriber system transmission equipment. 5 is a frame configuration diagram, 4 is a bit buffer section, 5 is a shift register section, 6 is a selector section, 7 is a counter/decoder section, and 9 is a control section. Early 2 response (η) (b) 1 粁 しん wo 4 bar 5 (s) 0 /?
2J4 /2J4 /234 /2J47%4 Closed peak S drawing number 6 Kau

Claims (1)

[Claims] A function of converting data synchronized with a first clock into data synchronized with a second clock, and generating a slip signal indicating the occurrence of an error when an error occurs during data conversion; a bit buffer unit having a function of detecting a signal indicating the beginning of data synchronized with a clock when the signal is input and transmitting a first detection signal;
a shift register section that shifts and stores data synchronized with the second clock output from the bit buffer section; and a shift register section that shifts and stores data synchronized with the second clock outputted from the bit buffer section; A counter/decoder unit that counts the second clock until it is reset, and corresponds to the count value when a signal indicating the beginning of data using the second clock is detected when the slip signal is not input. a control unit that controls a selector unit to select an output of the shift register unit and select an output of the shift register unit corresponding to the slip signal when the slip signal is input; and a control unit under the control of the control unit. and a selector section for selecting parallel outputs from the shift register section.