JPS6247741A - Rom type multiplying device - Google Patents

Abstract

PURPOSE:To omit such a case where two different types of multipliers are used to obtain positive and negative multipliers respectively, by using a single multiplier properly by a multiplication mode switching signal between the multiplication of two positive numbers and the multiplication of two negative numbers respectively. CONSTITUTION:When both a multiplier X and a multiplier Y are positive, the logic of a switching signal 10 is equal to 0 and both the multiplicand X and multiplier Y emerge as they are at the outputs of exclusive OR gates 1 and 2. These X and Y are supplied to ROMs 3-6 in the form of multiplicand and multiplier for arithmetic. Then the product P of X and Y is delivered from an adder 9. When both the multiplicand X and multiplier Y are negative, the signal 10 is set at logic 1 and the most significant bits of both X and Y undergo the logical inversion through both gates 1 and 2 together with other bits kept as they are. Thus the multiplicand and the multiplier for arithmetic are produced and the product of X and Y is delivered from an adder 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an ROIVIW multiplication device using a ROM.

[Conventional technology]

FIG. 4 is a block diagram showing an example of a conventional circuit. In the figure, (3) is a first ROM (abbreviated as ROMI), (
4) is the second ROM (abbreviated as ROM2), (5) is the third ROM (abbreviated as ROM3), (6) is the fourth ROM (abbreviated as ROM4), (11') is the addition I'll use a vessel. Further, the number appended to each signal line represents the number of parallel bits (binary number) transmitted by that signal line.

X is a multiplicand and should consist of 8 bits (generally n bits), 27+54 X=X7・X6・2+x・2+x・2+X3・2+
It is expressed as・2+XL...(1). Here, XU-X7・2+X6・2+X5・2+X4・2° and XL=X3・2+X2・2+X1・2 +X□”
It is 2.

Similarly, the multiplier Y has an 8-bit configuration and can be expressed as Y=Y.2/Y (2) U L . Here, YU=y7・23÷y6・22 + y,,・21 +
y4・2° and y, -13”2 +y2・2+y,
・2+yo・2.

ROM +31, (4+, (51, (61 are all the same structure 5y in the example shown in FIG. 5), and the multiplicand is 4 bits (generally dm bits, in this case m1=n
/2) and the multiplier 4 bits (generally m2 bits, in this case m2 = 2) are entered as the address, and the loss 8 bits (generally ml +
m2 bits) is output as a binary number.

P = X-Y = (Xtr・2'+XL) (YU・
24+ YL)=XU-YU・2+For・YL・2+XL
-YU・2+XL-YL...(3), R
OMI (31 is XU-size calculation, ROM2 (41 is XU" YL calculation, ROM 3 +51 is XL-Yt
Calculation of r, ROM4 (61 outputs the calculation result of XL-YL.

Carry up the output of ROMI +31 by 8 bits, and
+41.

By carrying the output of ROM 4 (5) by 4 bits and adding the output of ROM 4 (6) as is (that is, after performing the necessary digit alignment for the output of each ROM) in adder (1), the desired product can be obtained. P'i can be output as a 16-bit (generally 2n-bit) binary number.

By the way, a multiplication device may perform multiplication of negative numbers by negative numbers. In this case, a negative number is represented in complement representation, and if its most significant bit is logical rlJ, it is determined that it represents a negative number in complement representation.

Both the multiplicand X and the multiplier Y are negative numbers, and are 8-bit binary numbers.
□ xo (However, x, = x, = r I J ) Y=y8. y6Ty5. y4. y3. y2. ylpyo
(However, if it is displayed as y8=y7-r 1 j ), this is the value of X.

If, P=X-Y; (Xl-2) (Y knee 2) n-12H
-2 =4・Y□−(X1+Y1) 2 + 2 ・
...(4) Thealkara P=X, -Y1+(□+Ma,)
2n-1+(f-2+1)-2n (5).

FIG. 5 is a block diagram showing another example of the conventional circuit. When the multiplicand X1 and the multiplier Y are both negative numbers in complement representation, the equation (5
) is a circuit that performs calculations. In Fig. 5, the same reference numerals as in Fig. 4 indicate the same or equivalent parts.1-1(9) Addition device 9
．． ．． (12), (1:'l') are each 1-bit inverter, (14) 8-bit ijZ set (total 1
6-bit) inverter, (15) is a fixed number (2”2+
IX, when n = 8 (41) H (express H in hexadecimal)
) It is a constant circuit with full output.

Next, the operation will be explained. If both X and Y are negative numbers in complement representation, their most significant bit (+.

- bit representing the sign) XB r'! s is the logical ``tech''. x3 by inverter (12), (13)
Convert p 3'3 to a logical "0" bit, and
The other bits are left as they are to create a wave multiplier for calculation and a multiplier for calculation Y1. ROMI +31, 2 f4)
, 3 f5+ , 4 +61, input X1 and Yli by decomposing them into the upper 4 bits and lower 4 bits, respectively, and
Calculating Yl is the same as in the case of FIG. The inverter (14) is Xo.

Input Yl and output X engineering and Yl. Constant circuit (I5)
is a constant 2+1 ((41)H when n=8) k. Adder 2 (9) adds x and Yl to (n
-1) Carry up by one digit, (2n-2+1) f n
Pt- is calculated by adding it to the upper X□ and Y□ which have been carried up by one digit.

[Problem that the invention seeks to solve]

Since the conventional multiplication device is configured as described above, 2
The problem is that it is necessary to prepare separate multipliers for the multiplication of two positive numbers and the multiplication of two negative numbers (negative numbers are expressed as complements), as shown in Figures 4 and 5. There was a point.

This EiA was developed in order to solve the above problems, and provides a multiplication circuit that can perform multiplication of two positive numbers and multiplication of two negative numbers using the same multiplier. The purpose is to

[Means for solving problems]

In this invention, the same multiplier is conveniently switched between multiplication of two positive numbers and multiplication of two negative numbers by means of a multiplication mode switching signal.

[Effect]

In the multiplication circuit of the present invention, the multiplication algorithm is switched between multiplication according to equation (3) and multiplication according to equation (5) by the multiplication mode switching signal.

〔Example〕 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, the same reference numerals as in FIG.
11, (21U each Nis exclusive or gate, (
7x) and (7y) are NOR gates, (8) is the constant circuit of Hato's invention, and (10) is the switching signal S for multiplication of two positive numbers (temporarily referred to as the first multiplication mode).
The logic of signal S (10) is rOJ, and in the case of multiplication of two negative numbers (all expressed in complements) (temporarily referred to as 20th multiplication mode), the logic of signal S (10) is "1".

FIG. 2 is a connection diagram showing the internal connections of the NOR gate (7x) in FIG. 1, and the IC1NOR gate (7y) has a similar internal connection. - Also, FIG. 3 is a connection diagram showing the internal connections of the constant circuit of FIG. 1.

When the multiplicand X and the multiplier Y are both positive numbers, the signal S (1
Since the logic of 0) is "0", the logic of
ROvl 1 +31, 2 f4) as a calculation multiplier
, 3f51, 4 +61, and these R
From GvI are XU-YU, XU-YL, XL- respectively.
YU, XL-YL are output.

When the logic of the signal S (10) is "O", as is clear from FIGS. 2 and 3, the output X2. NOR game) (7y) output Y2. The outputs A of the constant circuit (8) are both connected to O, and the adder 2 (9) performs addition according to equation (3) and outputs the ratio P=X-Yk.

When the multiplicand equivalent)
The logic is inverted by the exclusive or gate (il), +2) (from cooking "1" to "0"),
X6. By leaving the logic of the bits below y6 as is, the multiplicand for operation X and the multiplier for operation Y1 are generated. Rran 1
The input/output of t31, 2+41, 3+51, and 4t61 can be performed in the same manner as when the logic of signal S (10) is "0". Also, NOR game) (7x) and (7y) are inputted to X and Y1e respectively, and the logic of signal (10) is rl
Since it is J, it outputs X2;
1) H) is output, and adder 2 (9) performs addition according to equation (5) and outputs @P. That is, by using the same multiplier and switching the multiplication mode according to the logic of the switching signal S (10), it is possible to perform multiplication when both the multiplicand and the multiplier are positive, and when both the multiplicand and the multiplier are negative (complement representation). .

In the above embodiment, an example of an 8-bit temporary multiplier and an 8-bit multiplier was explained, but in general, a multiplicand α bit and a multiplier β bit are used.
The invention can also be applied to bit multiplication.

Also, the exclusive or gate (11) in FIG.

(2), and the NOR gate shown in FIG.
The AND gates and the like shown in the figure only represent one embodiment of the present invention; they may be replaced with any other circuit that realizes all the equivalent functions, and the logic of the switching signal 5 (10) is
1", all multiplications of two positive numbers are performed, and the switching signal S (
It can also be designed to perform multiplication of two negative numbers when the value of 10) is "0".

〔Effect of the invention〕

As described above, according to the present invention, the multiplication of two positive numbers and the multiplication of two negative numbers (in complement representation) can be performed using the same multiplier.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a connection diagram showing the internal connections of the NOR gate in FIG. 1, and FIG.
1. FIG. 4 is a block diagram showing an example of a conventional circuit. FIG. 5 is a block diagram showing another example of the conventional circuit. fi+, (2H:t exclusive or gate, t3), +41, +51, +61
are the first. Second. Third. fourth ROlv1,
(7x) and (7y) are NOR gates, (8) is a constant circuit, (9) is an adder, and (10) is a multiplication mode switching signal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) At the address position indicated by the signal generated by concatenating the bit pattern representing the multiplicand in binary code and the bit pattern representing the multiplier in binary code, insert a binary code representing the product of the multiplicand and the multiplier. R to perform multiplication using stored ROM
In an OM type multiplication device, means for switching the multiplication mode between a first multiplication mode in which two positive numbers are multiplied and a second multiplication mode in which two negative numbers (complement representation) are multiplied. , in the first multiplication mode, the input multiplicand X and the input multiplier Y are directly used as the calculation multiplicand
In the second multiplication mode, the logic of the most significant bit (sign bit) of the input multiplicand ) is set to 0 and the multiplicand Y
Means for generating and outputting _1, inputting X_1 and Y_1 and using ROM to generate and output X_1・Y_1
A ROM type multiplier that outputs the values of
A NOR gate that outputs a value of 0 in the first multiplication mode and a constant circuit that outputs a constant in the second multiplication mode, the output of the ROM type multiplier, the output of the NOR gate, and the constant circuit 1. A ROM type multiplier comprising an adder that performs necessary digit alignment on the output of the ROM and then adds the result. (2) The ROM type multiplier converts the upper bits of the operation multiplicand to
_U, the lower bit is X_L, the upper bit of the operation multiplier is Y
_U, when the lower bit is Y_L, X_U, Y_U
The first ROM outputs X_U and Y_U with the address as
, X_U, Y_L are addresses and the second ROM outputs X_U・Y_L, X_L, Y_U are addresses and X_
A third ROM that outputs L and Y_U, a fourth ROM that uses X_L and Y_L as addresses and outputs X_L and Y_L,
ROM type according to claim 1, further comprising an adder that adds the outputs of the first, second, third, and fourth ROMs after performing necessary digit alignment. multiplication device.