| 
            
              JPS58147879A
              (ja)
            
            *
            
           | 
          1982-02-26 | 
          1983-09-02 | 
          Toshiba Corp | 
          キヤツシユメモリ制御方式 
        | 
        
        
          | 
            
              JPS5948879A
              (ja)
            
            *
            
           | 
          1982-09-10 | 
          1984-03-21 | 
          Hitachi Ltd | 
          記憶制御方式 
        | 
        
        
          | 
            
              US4897783A
              (en)
            
            *
            
           | 
          1983-03-14 | 
          1990-01-30 | 
          Nay Daniel L | 
          Computer memory system 
        | 
        
        
          | 
            
              JPS59213084A
              (ja)
            
            *
            
           | 
          1983-05-16 | 
          1984-12-01 | 
          Fujitsu Ltd | 
          バッファ記憶装置のアクセス制御方式 
        | 
        
        
          | 
            
              US4858111A
              (en)
            
            *
            
           | 
          1983-07-29 | 
          1989-08-15 | 
          Hewlett-Packard Company | 
          Write-back cache system using concurrent address transfers to setup requested address in main memory before dirty miss signal from cache 
        | 
        
        
          | 
            
              JPS60124754A
              (ja)
            
            *
            
           | 
          1983-12-09 | 
          1985-07-03 | 
          Fujitsu Ltd | 
          バッファ記憶制御装置 
        | 
        
        
          | 
            
              US4736293A
              (en)
            
            *
            
           | 
          1984-04-11 | 
          1988-04-05 | 
          American Telephone And Telegraph Company, At&T Bell Laboratories | 
          Interleaved set-associative memory 
        | 
        
        
          | 
            
              US4985829A
              (en)
            
            *
            
           | 
          1984-07-31 | 
          1991-01-15 | 
          Texas Instruments Incorporated | 
          Cache hierarchy design for use in a memory management unit 
        | 
        
        
          | 
            
              JPS6184753A
              (ja)
            
            *
            
           | 
          1984-10-01 | 
          1986-04-30 | 
          Hitachi Ltd | 
          バツフアメモリ 
        | 
        
        
          | 
            
              US4775955A
              (en)
            
            *
            
           | 
          1985-10-30 | 
          1988-10-04 | 
          International Business Machines Corporation | 
          Cache coherence mechanism based on locking 
        | 
        
        
          | 
            
              US4785398A
              (en)
            
            *
            
           | 
          1985-12-19 | 
          1988-11-15 | 
          Honeywell Bull Inc. | 
          Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page 
        | 
        
        
          | 
            
              US4953073A
              (en)
            
            *
            
           | 
          1986-02-06 | 
          1990-08-28 | 
          Mips Computer Systems, Inc. | 
          Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories 
        | 
        
        
          | 
            
              JPS62194563A
              (ja)
            
            *
            
           | 
          1986-02-21 | 
          1987-08-27 | 
          Hitachi Ltd | 
          バツフア記憶装置 
        | 
        
        
          | 
            
              US5237671A
              (en)
            
            *
            
           | 
          1986-05-02 | 
          1993-08-17 | 
          Silicon Graphics, Inc. | 
          Translation lookaside buffer shutdown scheme 
        | 
        
        
          | 
            
              EP0259967B1
              (en)
            
            *
            
           | 
          1986-08-01 | 
          1994-03-23 | 
          Fujitsu Limited | 
          Directory memory 
        | 
        
        
          | 
            
              JPS6340925A
              (ja)
            
            *
            
           | 
          1986-08-06 | 
          1988-02-22 | 
          Nec Corp | 
          メモリ初期化方式 
        | 
        
        
          | 
            
              JPS63118816A
              (ja)
            
            *
            
           | 
          1986-11-06 | 
          1988-05-23 | 
          Toshiba Corp | 
          キヤツシユメモリ付マイクロプロセツサシステム 
        | 
        
        
          | 
            
              US5055999A
              (en)
            
            *
            
           | 
          1987-12-22 | 
          1991-10-08 | 
          Kendall Square Research Corporation | 
          Multiprocessor digital data processing system 
        | 
        
        
          | 
            
              US5341483A
              (en)
            
            *
            
           | 
          1987-12-22 | 
          1994-08-23 | 
          Kendall Square Research Corporation | 
          Dynamic hierarchial associative memory 
        | 
        
        
          | 
            
              EP0325421B1
              (en)
            
            *
            
           | 
          1988-01-20 | 
          1994-08-10 | 
          Advanced Micro Devices, Inc. | 
          Organization of an integrated cache unit for flexible usage in supporting multiprocessor operations 
        | 
        
        
          | 
            
              US5184320A
              (en)
            
            *
            
           | 
          1988-02-12 | 
          1993-02-02 | 
          Texas Instruments Incorporated | 
          Cached random access memory device and system 
        | 
        
        
          | 
            
              JPH01217530A
              (ja)
            
            *
            
           | 
          1988-02-26 | 
          1989-08-31 | 
          Hitachi Ltd | 
          キヤツシユメモリ 
        | 
        
        
          | 
            
              US5034885A
              (en)
            
            *
            
           | 
          1988-03-15 | 
          1991-07-23 | 
          Kabushiki Kaisha Toshiba | 
          Cache memory device with fast data-write capacity 
        | 
        
        
          | 
            
              CA1301367C
              (en)
            
            *
            
           | 
          1988-03-24 | 
          1992-05-19 | 
          David James Ayers | 
          Pseudo set-associative memory cacheing arrangement 
        | 
        
        
          | 
            
              US5210843A
              (en)
            
            *
            
           | 
          1988-03-25 | 
          1993-05-11 | 
          Northern Telecom Limited | 
          Pseudo set-associative memory caching arrangement 
        | 
        
        
          | 
            
              US5214770A
              (en)
            
            *
            
           | 
          1988-04-01 | 
          1993-05-25 | 
          Digital Equipment Corporation | 
          System for flushing instruction-cache only when instruction-cache address and data-cache address are matched and the execution of a return-from-exception-or-interrupt command 
        | 
        
        
          | 
            
              US4996641A
              (en)
            
            *
            
           | 
          1988-04-15 | 
          1991-02-26 | 
          Motorola, Inc. | 
          Diagnostic mode for a cache 
        | 
        
        
          | 
            
              US5058006A
              (en)
            
            *
            
           | 
          1988-06-27 | 
          1991-10-15 | 
          Digital Equipment Corporation | 
          Method and apparatus for filtering invalidate requests 
        | 
        
        
          | 
            
              US4912630A
              (en)
            
            *
            
           | 
          1988-07-29 | 
          1990-03-27 | 
          Ncr Corporation | 
          Cache address comparator with sram having burst addressing control 
        | 
        
        
          | 
            
              US4907189A
              (en)
            
            *
            
           | 
          1988-08-08 | 
          1990-03-06 | 
          Motorola, Inc. | 
          Cache tag comparator with read mode and compare mode 
        | 
        
        
          | 
            
              US4905141A
              (en)
            
            *
            
           | 
          1988-10-25 | 
          1990-02-27 | 
          International Business Machines Corporation | 
          Partitioned cache memory with partition look-aside table (PLAT) for early partition assignment identification 
        | 
        
        
          | 
            
              KR900008516A
              (ko)
            
            *
            
           | 
          1988-11-01 | 
          1990-06-04 | 
          미다 가쓰시게 | 
          버퍼 기억장치 
        | 
        
        
          | 
            
              US5202969A
              (en)
            
            *
            
           | 
          1988-11-01 | 
          1993-04-13 | 
          Hitachi, Ltd. | 
          Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively 
        | 
        
        
          | 
            
              JPH0680499B2
              (ja)
            
            *
            
           | 
          1989-01-13 | 
          1994-10-12 | 
          インターナショナル・ビジネス・マシーンズ・コーポレーション | 
          マルチプロセッサ・システムのキャッシュ制御システムおよび方法 
        | 
        
        
          | 
            
              GB9008145D0
              (en)
            
            *
            
           | 
          1989-05-31 | 
          1990-06-06 | 
          Ibm | 
          Microcomputer system employing address offset mechanism to increase the supported cache memory capacity 
      | 
        
        
          | 
            
              US5226133A
              (en)
            
            *
            
           | 
          1989-12-01 | 
          1993-07-06 | 
          Silicon Graphics, Inc. | 
          Two-level translation look-aside buffer using partial addresses for enhanced speed 
        | 
        
        
          | 
            
              US5014195A
              (en)
            
            *
            
           | 
          1990-05-10 | 
          1991-05-07 | 
          Digital Equipment Corporation, Inc. | 
          Configurable set associative cache with decoded data element enable lines 
        | 
        
        
          | 
            
              EP0458552B1
              (en)
            
            *
            
           | 
          1990-05-18 | 
          2003-01-15 | 
          Sun Microsystems, Inc. | 
          Dynamic hierarchical routing directory organization associative memory 
        | 
        
        
          | 
            
              US5282274A
              (en)
            
            *
            
           | 
          1990-05-24 | 
          1994-01-25 | 
          International Business Machines Corporation | 
          Translation of multiple virtual pages upon a TLB miss 
        | 
        
        
          | 
            
              JPH05108484A
              (ja)
            
            *
            
           | 
          1990-06-07 | 
          1993-04-30 | 
          Intel Corp | 
          キヤツシユメモリ 
        | 
        
        
          | 
            
              EP0461926B1
              (en)
            
            *
            
           | 
          1990-06-15 | 
          1998-09-02 | 
          Compaq Computer Corporation | 
          Multilevel inclusion in multilevel cache hierarchies 
        | 
        
        
          | 
            
              US5434990A
              (en)
            
            *
            
           | 
          1990-08-06 | 
          1995-07-18 | 
          Ncr Corporation | 
          Method for serially or concurrently addressing n individually addressable memories each having an address latch and data latch 
        | 
        
        
          | 
            
              US5291442A
              (en)
            
            *
            
           | 
          1990-10-31 | 
          1994-03-01 | 
          International Business Machines Corporation | 
          Method and apparatus for dynamic cache line sectoring in multiprocessor systems 
        | 
        
        
          | 
            
              US5325504A
              (en)
            
            *
            
           | 
          1991-08-30 | 
          1994-06-28 | 
          Compaq Computer Corporation | 
          Method and apparatus for incorporating cache line replacement and cache write policy information into tag directories in a cache system 
        | 
        
        
          | 
            
              GB2260628A
              (en)
            
            *
            
           | 
          1991-10-11 | 
          1993-04-21 | 
          Intel Corp | 
          Line buffer for cache memory 
        | 
        
        
          | 
            
              US5414827A
              (en)
            
            *
            
           | 
          1991-12-19 | 
          1995-05-09 | 
          Opti, Inc. | 
          Automatic cache flush 
        | 
        
        
          | 
            
              US5469555A
              (en)
            
            *
            
           | 
          1991-12-19 | 
          1995-11-21 | 
          Opti, Inc. | 
          Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system 
        | 
        
        
          | 
            
              US5345582A
              (en)
            
            *
            
           | 
          1991-12-20 | 
          1994-09-06 | 
          Unisys Corporation | 
          Failure detection for instruction processor associative cache memories 
        | 
        
        
          | 
            
              US5537572A
              (en)
            
            *
            
           | 
          1992-03-31 | 
          1996-07-16 | 
          Vlsi Technology, Inc. | 
          Cache controller and method for dumping contents of a cache directory and cache data random access memory (RAM) 
        | 
        
        
          | 
            
              DE69323790T2
              (de)
            
            *
            
           | 
          1992-04-29 | 
          1999-10-07 | 
          Sun Microsystems, Inc. | 
          Verfahren und Vorrichtung für mehreren ausstehende Operationen in einem cachespeicherkohärenten Multiprozessorsystem 
        | 
        
        
          | 
            
              US5809531A
              (en)
            
            *
            
           | 
          1992-09-21 | 
          1998-09-15 | 
          Intel Corporation | 
          Computer system for executing programs using an internal cache without accessing external RAM 
        | 
        
        
          | 
            
              US5465342A
              (en)
            
            *
            
           | 
          1992-12-22 | 
          1995-11-07 | 
          International Business Machines Corporation | 
          Dynamically adaptive set associativity for cache memories 
        | 
        
        
          | 
            
              US5682515A
              (en)
            
            *
            
           | 
          1993-01-25 | 
          1997-10-28 | 
          Benchmarq Microelectronics, Inc. | 
          Low power set associative cache memory with status inhibit of cache data output 
        | 
        
        
          | 
            
              US5500950A
              (en)
            
            *
            
           | 
          1993-01-29 | 
          1996-03-19 | 
          Motorola, Inc. | 
          Data processor with speculative data transfer and address-free retry 
        | 
        
        
          | 
            
              US5539894A
              (en)
            
            *
            
           | 
          1993-04-20 | 
          1996-07-23 | 
          Sun Microsystems, Inc. | 
          Method and apparatus for optimizing a sector cache tag, block and sub-block structure base on main memory size 
        | 
        
        
          | 
            
              US5732243A
              (en)
            
            *
            
           | 
          1994-10-18 | 
          1998-03-24 | 
          Cyrix Corporation | 
          Branch processing unit with target cache using low/high banking to support split prefetching 
        | 
        
        
          | 
            
              US5860149A
              (en)
            
            *
            
           | 
          1995-06-07 | 
          1999-01-12 | 
          Emulex Corporation | 
          Memory buffer system using a single pointer to reference multiple associated data 
        | 
        
        
          | 
            
              US5845317A
              (en)
            
            *
            
           | 
          1995-11-17 | 
          1998-12-01 | 
          Micron Technology, Inc. | 
          Multi-way cache expansion circuit architecture 
        | 
        
        
          | 
            
              US5809562A
              (en)
            
            *
            
           | 
          1996-05-20 | 
          1998-09-15 | 
          Integrated Device Technology, Inc. | 
          Cache array select logic allowing cache array size to differ from physical page size 
        | 
        
        
          | 
            
              US6636944B1
              (en)
            
            *
            
           | 
          1997-04-24 | 
          2003-10-21 | 
          International Business Machines Corporation | 
          Associative cache and method for replacing data entries having an IO state 
        | 
        
        
          | 
            
              US6098152A
              (en)
            
            *
            
           | 
          1997-10-17 | 
          2000-08-01 | 
          International Business Machines Corporation | 
          Method and apparatus for miss sequence cache block replacement utilizing a most recently used state 
        | 
        
        
          | 
            
              JPH11296263A
              (ja)
            
            *
            
           | 
          1998-04-13 | 
          1999-10-29 | 
          Fujitsu Ltd | 
          プロセッサの初期設定制御装置 
        | 
        
        
          | 
            
              US6661421B1
              (en)
            
            
            
           | 
          1998-05-21 | 
          2003-12-09 | 
          Mitsubishi Electric & Electronics Usa, Inc. | 
          Methods for operation of semiconductor memory 
        | 
        
        
          | 
            
              US6559851B1
              (en)
            
            
            
           | 
          1998-05-21 | 
          2003-05-06 | 
          Mitsubishi Electric & Electronics Usa, Inc. | 
          Methods for semiconductor systems for graphics processing 
        | 
        
        
          | 
            
              US6535218B1
              (en)
            
            
            
           | 
          1998-05-21 | 
          2003-03-18 | 
          Mitsubishi Electric & Electronics Usa, Inc. | 
          Frame buffer memory for graphic processing 
        | 
        
        
          | 
            
              US6504550B1
              (en)
            
            
            
           | 
          1998-05-21 | 
          2003-01-07 | 
          Mitsubishi Electric & Electronics Usa, Inc. | 
          System for graphics processing employing semiconductor device 
        | 
        
        
          | 
            
              US6339813B1
              (en)
            
            *
            
           | 
          2000-01-07 | 
          2002-01-15 | 
          International Business Machines Corporation | 
          Memory system for permitting simultaneous processor access to a cache line and sub-cache line sectors fill and writeback to a system memory 
        | 
        
        
          | 
            
              US6823434B1
              (en)
            
            *
            
           | 
          2000-02-21 | 
          2004-11-23 | 
          Hewlett-Packard Development Company, L.P. | 
          System and method for resetting and initializing a fully associative array to a known state at power on or through machine specific state 
        | 
        
        
          | 
            
              US6629213B1
              (en)
            
            *
            
           | 
          2000-05-01 | 
          2003-09-30 | 
          Hewlett-Packard Development Company, L.P. | 
          Apparatus and method using sub-cacheline transactions to improve system performance 
        | 
        
        
          | 
            
              KR100335500B1
              (ko)
            
            *
            
           | 
          2000-05-16 | 
          2002-05-08 | 
          윤종용 | 
          직접사상 캐쉬와 완전연관 버퍼를 포함한 캐쉬 시스템의제어 방법 
        | 
        
        
          | 
            
              US6766431B1
              (en)
            
            
            
           | 
          2000-06-16 | 
          2004-07-20 | 
          Freescale Semiconductor, Inc. | 
          Data processing system and method for a sector cache 
        | 
        
        
          | 
            
              US7310706B1
              (en)
            
            *
            
           | 
          2001-06-01 | 
          2007-12-18 | 
          Mips Technologies, Inc. | 
          Random cache line refill 
        | 
        
        
          | 
            
              US7565658B2
              (en)
            
            *
            
           | 
          2001-10-08 | 
          2009-07-21 | 
          Telefonaktiebolaget L M Ericsson (Publ) | 
          Hidden job start preparation in an instruction-parallel processor system 
        | 
        
        
          | 
            
              US6912628B2
              (en)
            
            *
            
           | 
          2002-04-22 | 
          2005-06-28 | 
          Sun Microsystems Inc. | 
          N-way set-associative external cache with standard DDR memory devices 
        | 
        
        
          | 
            
              US7246202B2
              (en)
            
            *
            
           | 
          2002-11-11 | 
          2007-07-17 | 
          Matsushita Electric Industrial Co., Ltd. | 
          Cache controller, cache control method, and computer system 
        | 
        
        
          | 
            
              US20040103251A1
              (en)
            
            *
            
           | 
          2002-11-26 | 
          2004-05-27 | 
          Mitchell Alsup | 
          Microprocessor including a first level cache and a second level cache having different cache line sizes 
        | 
        
        
          | 
            
              US7240277B2
              (en)
            
            *
            
           | 
          2003-09-26 | 
          2007-07-03 | 
          Texas Instruments Incorporated | 
          Memory error detection reporting 
        | 
        
        
          | 
            
              US7526610B1
              (en)
            
            *
            
           | 
          2008-03-20 | 
          2009-04-28 | 
          International Business Machines Corporation | 
          Sectored cache memory 
        | 
        
        
          | 
            
              US8464001B1
              (en)
            
            *
            
           | 
          2008-12-09 | 
          2013-06-11 | 
          Nvidia Corporation | 
          Cache and associated method with frame buffer managed dirty data pull and high-priority clean mechanism 
        | 
        
        
          | 
            
              US8745334B2
              (en)
            
            *
            
           | 
          2009-06-17 | 
          2014-06-03 | 
          International Business Machines Corporation | 
          Sectored cache replacement algorithm for reducing memory writebacks 
        | 
        
        
          | 
            
              US9514055B2
              (en)
            
            *
            
           | 
          2009-12-31 | 
          2016-12-06 | 
          Seagate Technology Llc | 
          Distributed media cache for data storage systems 
        | 
        
        
          | 
            
              JP5597306B2
              (ja)
            
            *
            
           | 
          2010-04-21 | 
          2014-10-01 | 
          エンパイア  テクノロジー  ディベロップメント  エルエルシー | 
          記憶効率の高いセクタ化されたキャッシュ 
        | 
        
        
          | 
            
              US8589627B2
              (en)
            
            *
            
           | 
          2010-08-27 | 
          2013-11-19 | 
          Advanced Micro Devices, Inc. | 
          Partially sectored cache 
        | 
        
        
          | 
            
              US11360704B2
              (en)
            
            *
            
           | 
          2018-12-21 | 
          2022-06-14 | 
          Micron Technology, Inc. | 
          Multiplexed signal development in a memory device 
        |