JPS6244536Y2 - - Google Patents

Info

Publication number
JPS6244536Y2
JPS6244536Y2 JP17450581U JP17450581U JPS6244536Y2 JP S6244536 Y2 JPS6244536 Y2 JP S6244536Y2 JP 17450581 U JP17450581 U JP 17450581U JP 17450581 U JP17450581 U JP 17450581U JP S6244536 Y2 JPS6244536 Y2 JP S6244536Y2
Authority
JP
Japan
Prior art keywords
wiring
conductor wiring
conductor
groove
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP17450581U
Other languages
Japanese (ja)
Other versions
JPS5878652U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17450581U priority Critical patent/JPS5878652U/en
Publication of JPS5878652U publication Critical patent/JPS5878652U/en
Application granted granted Critical
Publication of JPS6244536Y2 publication Critical patent/JPS6244536Y2/ja
Granted legal-status Critical Current

Links

Description

【考案の詳細な説明】 本考案は半導体素子、特にLSIや超LSI等の多
数条の導体配線を有する素子搭載用セラミツクパ
ツケージの改良に係り、更に詳しくはセラミツク
表面に多数条の凹溝を設けたその凹溝内部に導体
配線すると共に、それに被覆する絶縁壁の対向同
一位置に導体配線して、両者を合致して構成した
もので、その導通配線の断面積を大きくして導通
抵抗値を低下し、また各配線間の短絡を防止する
構造である半導体素子搭載用セラミツクパツケー
ジに関するものである。
[Detailed description of the invention] The present invention relates to the improvement of a ceramic package for mounting semiconductor devices, particularly devices such as LSI and VLSI, which have a large number of conductor wiring lines. The conductor wiring is placed inside the groove, and the conductor wiring is placed at the same position opposite to the insulating wall covering the groove, and the two are aligned.The cross-sectional area of the conductive wiring is increased to increase the conductive resistance value. The present invention relates to a ceramic package for mounting a semiconductor element, which has a structure that prevents short circuits between wiring lines.

半導体素子は電子機器類の小型軽量化、高速
化、高密度化、高信頼性などの要求でICからLSI
を経て超LSI、超VLSIへと進展しており、これに
伴い素子搭載用セラミツクパツケージも多層高密
度配線となり製造上、性能上種々な問題が出現し
てきた。
Semiconductor elements have changed from IC to LSI due to demands for smaller size, lighter weight, higher speed, higher density, and higher reliability in electronic equipment.
This has led to the development of ultra-LSI and ultra-VLSI, and as a result, ceramic packages for mounting elements have become multi-layered and densely interconnected, creating various problems in terms of manufacturing and performance.

第1図は従来の半導体素子搭載用セラミツクパ
ツケージであり、A図は平面図、B図は線F−
F′よりの拡大半断面図である。
Figure 1 shows a conventional ceramic package for mounting semiconductor elements, where Figure A is a plan view and Figure B is a line F-
It is an enlarged half-sectional view taken from F′.

図中1のセラミツクパツケージ(以下「パツケ
ージ」に略記す)の中央に半導体素子を搭載収納
する凹部2があり、その凹部2の端縁から外端方
向に向つて多数条放射状に各導体配線3が形成さ
れていて、その上面に凹部の端縁部の導体配線部
分を僅か残して絶縁壁5が被覆されて、また導体
配線の外端側面にその取出しリード4が溶着され
る。上記の多数条放射状に設けた導体配線の形成
方法は、セラミツクの生シート表面に金属紛末を
ペースト状にしたものを印刷法にて凸状に盛りあ
げたものであり、絶縁壁5となる生シートを圧着
した時、僅かではあるが線巾が拡大する。また高
密度の配線にて形成し焼結完成したものは、各配
線間の間隔が接近して短絡発生の確率が増加し、
絶縁壁で圧接した箇所は各配線の隣線と接触する
危険性が生じた。それに加え配線の断面積が小さ
いためジユール熱発生に伴なう電気的損失となり
最終的には断線と云う致命的なものとなつた。
There is a recess 2 in the center of the ceramic package 1 (hereinafter abbreviated as "package") in which a semiconductor element is mounted and housed, and a large number of conductor wiring lines 3 extend radially from the edge of the recess 2 toward the outer end. An insulating wall 5 is formed on the upper surface of the insulating wall 5, leaving only a small portion of the conductor wiring at the edge of the recess, and the lead 4 is welded to the outer end side surface of the conductor wiring. The above-mentioned method of forming multiple radial conductor wirings involves printing a paste of metal powder on the surface of a raw ceramic sheet and mounding it up in a convex shape, which becomes the insulating wall 5. When raw sheets are crimped, the line width expands, albeit slightly. In addition, when forming and sintering high-density wiring, the distance between each wiring becomes close, increasing the probability of short circuits.
There was a risk that each wire would come into contact with the adjacent wire at the locations where the wires were pressed together with the insulating wall. In addition, because the cross-sectional area of the wiring is small, electrical loss occurs due to the generation of Joule heat, which ultimately leads to a fatal disconnection.

本考案は以上の欠点を解決するために成された
ものであり、その要旨は多数条放射状の導体配線
を、セラミツク表面に多数条放射状の少なくとも
1部に、深さaの凹溝を設けたその凹溝内部にa
より小さい厚さbに導体配線13aするととも
に、それに被覆する絶縁壁15aの対向同一位置
に厚さa−bと同等ないし僅かに大なる厚さの導
体を配線13bして両者を合致し、絶縁層を介し
たものよりなることを特徴とするもので、凹溝内
部の導体配線13aとそれらの隙間に対向の導体
配線13bが圧入され一体構成される。
The present invention has been developed to solve the above-mentioned drawbacks, and its gist is to provide multi-strip radial conductor wiring with grooves of depth a in at least a portion of the multi-strip radial conductor wiring on the ceramic surface. Inside the concave groove is a
A conductor wiring 13a with a smaller thickness b is placed, and a conductor wiring 13b with a thickness equal to or slightly larger than the thickness a-b is placed at the same position facing the insulating wall 15a covering the conductor wiring 13a, so that the two match and are insulated. It is characterized by being made of interlayered conductor wires 13a and the opposing conductor wires 13b are press-fitted into the gap between the conductor wires 13a inside the groove and are integrally constructed.

本考案では凹部内に導体配線が以上のようにし
て形成されるため、配線の厚さ寸法を厚く形成出
来て導通低抗値を低下し、各配線の隣線との接触
する危険性がなくなり、かつ短絡発生を排除出来
た。
In the present invention, since the conductor wiring is formed in the recess as described above, the thickness of the wiring can be formed thicker, lowering the conductive resistance value, and eliminating the risk of each wiring coming into contact with the adjacent wire. , and the occurrence of short circuits could be eliminated.

以下、本考案の実施例である第2図A図のパツ
ケージ平面図と、線K−K′よりの拡大半断面図
のB図と線G−G′よりの拡大一部分断面図のC
図により説明する。
Hereinafter, the package plan view shown in FIG. 2A, which is an embodiment of the present invention, FIG.
This will be explained using figures.

図中11のパツケージの中央に半導体素子を搭
載する凹部12があり、この凹部12の端縁から
外端方向に向つて多数条放射状に各導体配線が形
成されている。この各導体配線はセラミツクの生
シートを、多数条放射状に凸部を形成した金型に
て圧接して凹溝を成形した凹溝内部に金属W粉末
をペースト状にしたものを印刷法にて印刷形成
し、この時の凹溝の深さ寸法は70μmで印刷配線
は凹部底面に50μmの厚さ寸法で形成した。また
上記シートに被覆するシート下面に上記凹部と対
向する同一位置に配線を25μmの厚さで印刷形成
して、両者を合致させ圧着し、裁断后樹脂抜きし
て焼結作成した。それをC図に示し、15bが凹
部の内底面に配線を形成した層であり、15aが
層の下表面に配線を形成し被覆合致した状態であ
る。
In the center of the package 11 in the figure, there is a recess 12 in which a semiconductor element is mounted, and a large number of conductor wiring lines are formed radially from the edge of the recess 12 toward the outer end. Each of these conductor wirings is made by pressing a raw ceramic sheet with a mold with multiple radial convex parts to form a groove, and then applying a paste of metal W powder inside the groove, using a printing method. The groove was formed by printing, and the depth of the groove was 70 μm, and the printed wiring was formed on the bottom of the recess with a thickness of 50 μm. In addition, a wiring with a thickness of 25 μm was printed on the lower surface of the sheet covering the sheet at the same position facing the recess, and the two were matched and pressed together. After cutting, the resin was removed and sintered. This is shown in Figure C, where 15b is a layer in which wiring is formed on the inner bottom surface of the recess, and 15a is a layer in which wiring is formed on the lower surface of the layer and is in a state of matching coverage.

以上本実施例では凹溝断面の形状を長方形とし
たが、本考案はこれにこだわることなく底辺を円
弧状にしたりU字型にしたり、V字型等にしても
よく、導体配線の印刷もシルクスクリーン法によ
るプリント配線にこだわらず圧入法にしてもよ
い。また配線パターンも放射状にこだわらず、中
心より外方へ向うもの総て含むものとする。
As mentioned above, in this embodiment, the shape of the cross section of the groove is rectangular, but the present invention is not limited to this, and the bottom may be made into an arc, U-shape, V-shape, etc., and conductor wiring can also be printed. Instead of printing wiring using the silk screen method, a press-fitting method may be used. Furthermore, the wiring pattern is not limited to a radial pattern, and includes all wiring patterns directed outward from the center.

本考案は導体配線を厚い寸法で形成出来、また
凹溝内部より外部に食み出すことがなく、短絡や
断線が殆んどなくなり、高密度配線のパツケージ
やその他の積層型基板等に好適である。
This invention allows conductor wiring to be formed in thick dimensions, does not protrude from the inside of the groove to the outside, and almost eliminates short circuits and disconnections, making it suitable for high-density wiring packages and other laminated substrates. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のセラミツクパツケージであり、
A図は平面図、B図は線F−F′よりの拡大半断
面図、第2図は本考案の実施例であり、A図は平
面図、B図は線K−K′よりの拡大半断面図、C
図は線G−G′よりの断面一部分拡大図である。 1,11……セラミツクパツケージ、2,12
……素子搭載凹部、3,13a,13b……導体
配線、4,14……リード、5,15a……絶縁
壁。
Figure 1 shows a conventional ceramic package.
Figure A is a plan view, Figure B is an enlarged half-sectional view taken from line F-F', Figure 2 is an embodiment of the present invention, Figure A is a plan view, and Figure B is an enlarged view taken from line K-K'. Half section view, C
The figure is a partially enlarged cross-sectional view taken along line GG'. 1, 11...Ceramic package, 2, 12
...Element mounting recess, 3, 13a, 13b... Conductor wiring, 4, 14... Lead, 5, 15a... Insulating wall.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体素子搭載用パツケージの素子搭載凹部の
端縁から外端方向に向かつて多数条放射状に導体
配線されたセラミツクパツケージにおいて、上記
多数条放射状の導体配線の少なくとも1部を、セ
ラミツク表面に多数条放射状の深さaの凹溝を設
けたその凹溝内部にaより小さい厚さbに導体配
線するとともに、それに被覆する絶縁壁の対向同
一位置に厚さa−bと同等ないし僅かに大なる厚
さの導体を配線して両者を合致し、絶縁層を介し
たものよりなることを特徴とする半導体素子搭載
用セラミツクパツケージ。
In a ceramic package in which conductor wiring is arranged in multiple radial lines from the edge of an element mounting recess toward the outer end of a package for mounting a semiconductor element, at least a portion of the multiple radial conductor wiring is arranged in a multiple radial manner on the surface of the ceramic. A groove with a depth a of 1. A ceramic package for mounting a semiconductor element, characterized in that the two conductors are wired and matched with each other with an insulating layer interposed therebetween.
JP17450581U 1981-11-24 1981-11-24 Ceramic package for mounting semiconductor elements Granted JPS5878652U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17450581U JPS5878652U (en) 1981-11-24 1981-11-24 Ceramic package for mounting semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17450581U JPS5878652U (en) 1981-11-24 1981-11-24 Ceramic package for mounting semiconductor elements

Publications (2)

Publication Number Publication Date
JPS5878652U JPS5878652U (en) 1983-05-27
JPS6244536Y2 true JPS6244536Y2 (en) 1987-11-25

Family

ID=29966526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17450581U Granted JPS5878652U (en) 1981-11-24 1981-11-24 Ceramic package for mounting semiconductor elements

Country Status (1)

Country Link
JP (1) JPS5878652U (en)

Also Published As

Publication number Publication date
JPS5878652U (en) 1983-05-27

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