JP2734625B2 - Method for manufacturing multilayer wiring board - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a multilayer wiring board for mounting a semiconductor element. In particular, the present invention relates to a method for manufacturing a multilayer wiring board for mounting a semiconductor element having a through hole in which a part of an inner conductor pattern is exposed.

[Conventional technology]

2. Description of the Related Art In recent years, the number of terminals for external connection of a semiconductor device has significantly increased with the increase in the density and the number of functions of semiconductor elements.
As one of the measures, a chip carrier of a multilayer wiring board has been used. In this case, it is necessary to form a plating layer containing gold or silver on the conductor pattern of the multilayer wiring board connected to the semiconductor element by the gold wire from the viewpoint of bonding strength with the gold wire and reliability of electric characteristics. Conventionally, when forming a circuit on a conductor layer of an outer layer substrate of a multilayer substrate composed of an inner layer substrate on which an exposed conductor pattern is disposed, a temporary protection process is performed so that the exposed conductor pattern is not damaged, and then all conductor patterns are formed. At a time, but a troublesome process called a temporary protection process for preventing the exposed conductor pattern from being attacked was required. Furthermore, since the conductor pattern on the surface of the multilayer wiring board which becomes a chip carrier becomes more and more complicated due to the further development of the semiconductor element, the individual conductor patterns provided on the multilayer wiring board are insulated to form the multilayer wiring board. There is a problem that it cannot be extended to the end of the layer and used as an external connection terminal for electroplating. As a countermeasure, a conductor pattern provided on one surface of the insulating layer is connected to a conductor pattern provided on the other surface via a through-hole conductive path, thereby connecting one conductor pattern to the end of the insulating layer. They have been extended to external connection terminals for electroplating. However, in the multilayer wiring board, if such a through-hole is present as it is, the through-hole shortens the insulation distance from the conductor pattern, making it easier for leakage current to flow, or connecting the conductor pattern to an extra circuit called a conductive path of the through-hole. This causes problems such as increased circuit resistance, and when mounting the multilayer wiring board on the motherboard, the solder rises while filling the through holes and scatters on the surface of the multilayer wiring board opposite to the motherboard, damaging the conductor pattern. there were.

[Problems to be solved by the invention]

Temporarily protect the exposed conductor pattern of the inner layer substrate,
The through hole used to form the plating layer on the inner conductor pattern reduces the insulating property with the conductor pattern and increases the circuit resistance of the conductor pattern by eliminating the troublesome process of removing after use. It is still another object of the present invention to provide a method for manufacturing a multilayer wiring board in which solder does not raise through holes and damage the multilayer wiring board.

[Means for solving the problem]

In order to solve the above-mentioned problems, the present invention provides a first insulating layer, a conductive pattern layer formed on the first insulating layer, a concave portion extending from the conductive pattern layer to the first insulating layer, and a conductive pattern formed on the first insulating layer. In the inner layer substrate having a plating layer including gold plating formed on the inner layer substrate, the plating layer of the inner layer substrate is connected to conductor patterns on both sides of the insulating layer by conductive paths of through holes formed in the inner layer substrate, and a recess for mounting a semiconductor element is formed. A conductor pattern on the opposite side to the one formed is extended to the end to form an external terminal, and a second insulating layer, a conductor layer formed on the second insulating layer, and a conductor formed from the second insulating layer An outer layer substrate having an opening communicating with the layer and having an opening surface larger than the recess, wherein the recess is located in the opening, and the conductor pattern and the second insulating layer are overlapped with each other to form a pressure-receiving body. Then, this pressed body is hot-pressed and obtained. Method for manufacturing a multilayer wiring board, which comprises forming a conductor pattern on the conductive layer of the outer layer board having a multilayer wiring board. When forming a conductor pattern on the conductor layer of the outer substrate according to claim 1, a through hole larger than the diameter of the through hole is formed in the through hole formed in the inner substrate, and the first and second through holes are formed as conductive paths. It is connected to the conductor pattern of the insulating layer, and the conductor pattern on the opposite side to the side where the concave portion for mounting the semiconductor element is formed is extended to the end to form a plating layer containing gold plating as an external terminal. A method for manufacturing a multilayer wiring board according to claim 1. "

〔Example〕

The details will be described below with reference to the drawings. FIG. 1 is a perspective view of a multilayer wiring board manufactured by the present invention, and FIG. 2 (g).
Is a sectional view thereof.

The inner substrate of FIG. 2 (c) is obtained as follows.
As shown in FIG. 2 (a), the substrate of the first insulating layer 1 having the copper foil conductor layers 2 disposed on both sides thereof is placed on the first insulating layer 1 as shown in FIG. 2 (b). A concave portion 3 for mounting a semiconductor element reaching the insulating layer is formed by spot facing, and a through hole 4 communicating with the first insulating layer 1 from the conductor layer 2 to a portion other than the concave portion 3;
4,... Are provided by drilling. Then, the whole is subjected to electroless copper plating to form conductive paths 5 in the through holes 4, 4,..., And further, the conductive layer 2 shown in FIG. Form. By this circuit formation, the inner conductor pattern 6 on the surface of the first insulating layer 1 in which the recess 3 for mounting the semiconductor element is formed.
Extends to the end of the surface of the insulating layer 1 opposite to the recess 3 for mounting the semiconductor element through the conductive path 5 formed in the through hole 4 and is electrically connected to the conductor pattern 7 serving as an external connection terminal. . Using the external connection terminals, a plating layer 16 of nickel and gold plating is provided on the two inner conductor patterns 6 and 7 by electroplating to form the inner substrate 8 of FIG. 2 (c). In addition, the electroplating of various metals can be applied to the formation of the plating layer 16. That is, gold, silver, nickel, solder, and the like are preferable as the electroplating, and may be used alone or in combination. The combination of nickel and gold is optimal in terms of workability and durability.

On the other hand, the outer layer substrate is obtained as follows. As shown in FIG. 2 (d), a second insulating layer provided with a copper foil conductor layer 2 on one side and an adhesive layer 11 made of prepreg on the other side.
An outer layer substrate 9 is formed by providing a rectangular opening 12 for mounting a semiconductor element from the conductor layer 2 through the second insulating layer 10 and communicating with the adhesive layer 11 in the substrate having 10. Note that the adhesive layer 11 provided on the other surface of the second insulating layer 10 does not need to be integrated with the second insulating layer 10, and the inner substrate 8 and the outer substrate 9 are laminated and integrated. Sometimes, an adhesive film, an adhesive sheet, a prepreg or the like having an opening 12 between them is attached to the outer substrate 9.
The openings 12 may be integrated with each other. Also,
The shape of the opening 12 is not limited to a square, but may be a circle or the like, and is not particularly limited. In addition, this opening
12 must be larger than the recess 3 of the inner layer substrate 8.
The reason is that, as shown in FIG.
Is laminated and integrated with the inner layer substrate 8, the inner layer conductor pattern 6 around the concave portion 3 formed in the inner layer substrate 8 has an opening 12.
This is because if it is not exposed to the inside, a terminal for connecting the mounted semiconductor element cannot be obtained.

FIG. 2 (e) shows that the adhesive layer of the outer layer substrate 9 and the inner layer conductor pattern layer 6 of the inner layer substrate 8 on the side where the recess 3 for mounting the semiconductor element is formed are overlapped. It is a pressure-receiving body that is positioned within the opening 12 of the outer layer substrate 9 and overlapped. When the outer layer substrate 9 does not have the adhesive layer 11, the openings 12 of the outer layer substrate 9 coincide with each other by appropriately selecting from an adhesive film, an adhesive sheet, a prepreg having an opening 12 with the inner layer substrate 8, and the like. Then, these are superposed to form a pressure-receiving body.

FIG. 2 (f) shows that after the pressure-receiving body is heated and pressurized and laminated and integrated, a through hole 13 having a diameter larger than the diameter of the through hole 4 is formed at the position of the through hole 4 from the conductor pattern 7 of the inner layer substrate 8 to the outer layer. It is formed to reach the conductor layer 2 of the substrate 9.

FIG. 2 (g) shows the subsequent electroless copper plating,
The conductor layer 2 of the outer layer substrate 9 is etched to form a conductor pattern 14.
Is formed, and the conductor pattern 14 of the outer substrate 9 and the inner conductor pattern 6 protected by the plating layer of the inner substrate 8 are formed.
Are disposed on the side opposite to the recess 3 for mounting the semiconductor element of the multilayer wiring board through the conductive path 15 formed in the through hole 13 for inserting the terminal pin, and are extended to the end to serve as external terminals. The external terminal is connected to the conductor pattern 7, and a plating layer 16 of nickel and gold plating is formed on the inner layer conductor pattern 6, the conductor patterns 7 and 14 by electroplating using the external terminals to mount a semiconductor element used as a semiconductor chip carrier. This is a multilayer wiring board.

In such a structure, since the inner conductor pattern 6 exposed in the opening 12 for mounting the semiconductor element is covered with a plating layer such as nickel and further gold plating as described above, it is particularly necessary to apply a resist or a masking material. Instead, a conductor pattern can be formed on the conductor layer 2 of the outer substrate by a conventional subtractive method. The conductive path formed in the through hole 13
In the inner layer conductor pattern 6 connected to the conductor pattern 15, the conductor pattern 14 on the surface of the outer layer substrate 9, and the conductor pattern 7 formed on the opposite side of the recess 3 for mounting the semiconductor element on the inner layer substrate 8, the conductor pattern 7 or the conductor pattern 14 is formed. May be extended to the end of the multilayer wiring board to serve as an external terminal, and the conduction path is not particularly limited. Furthermore, a terminal pin (not shown) is inserted into the through hole 13 and fixed by soldering, so that the PGA which is easy to insert and mount on the motherboard is provided.
A semiconductor chip carrier of the type is obtained.

As the first insulating layer 1 and the second insulating layer 10 constituting the inner substrate 8 in FIG. 2C and the outer substrate 9 in FIG. 2D, the base material is impregnated with resin and dried. An insulating material obtained by curing the resin of the prepreg obtained as described above is used. Here the first
As the resin of the first and second insulating layers 1 and 10, it is preferable to use a resin having excellent heat resistance and moisture resistance and having a low resin purity, particularly a low ionic impurity. Specifically, epoxy resin, polyimide resin,
Fluoro resin, PPO resin and the like are suitable. As the base material of the first and second insulating layers 1 and 10, an inorganic material such as glass fiber is more preferable than paper because it is superior in heat resistance and moisture resistance and hardly causes warpage. The inner layer conductor patterns 6, conductor patterns 7, and 14 formed on the surfaces of the first and second insulating layers 1 and 10 can be appropriately selected and applied from copper, aluminum, iron, nickel, stainless steel, and the like. Copper is particularly preferred because of its excellent conductivity.

〔The invention's effect〕

As described above, according to the method for manufacturing a multilayer wiring board of the present invention, the multilayer wiring board includes an inner layer substrate on which a complicated conductor pattern that cannot be extended and disposed to the end of the insulating layer constituting the multilayer wiring substrate is provided. By forming a gold-plated plating layer on the conductor pattern of the inner substrate exposed through the through-hole conductive path in the multilayer wiring board, the conductor pattern is temporarily protected and the troublesome process of removal after use is eliminated. Can be formed, and furthermore, a through-hole for inserting a terminal pin having a diameter larger than that of the through-hole used for forming such a plating layer is overlapped and perforated to form an electroplating of the conductor pattern of the inner layer substrate. The through hole is used for inserting the terminal pin, and the terminal pin is inserted and fixed to close the through hole, so that there is a gap between the conductor pattern and the extra through hole. It is able to manufacture a multilayer wiring board having the effect of inhibiting the like to increase the circuit resistance of the conductor pattern by the connection of that or extra Sulfol conduction paths easily leak current reduces sexual flow.

[Brief description of the drawings]

FIG. 1 is a perspective view of a multilayer wiring board according to an embodiment of the present invention.
2 (a), (b), (c), (d), (e),
(F), (g) is sectional drawing of the member which showed the Example of the manufacturing method for obtaining the multilayer wiring board in a series of process order. DESCRIPTION OF SYMBOLS 1 ... 1st insulating layer 2 ... Conductor layer 3 ... Concave part for mounting a semiconductor element 4 ... Through hole 5 ... Conductor path of through hole 6 ... Inner layer conductor pattern 7 ... Conductor pattern 8 ... Inner substrate 9 ... Outer substrate 10 ... Second Insulating layer 11 ... Adhesive layer 13 ... Surhole for terminal pin insertion 16 ... Plating layer

Continuation of front page (56) References JP-A-1-93198 (JP, A) JP-A-63-114239 (JP, A) JP-A-63-255996 (JP, A)

Claims (2)

(57) [Claims] A first insulating layer, a conductive pattern layer formed on the first insulating layer, a concave portion extending from the conductive pattern layer to the first insulating layer, and a gold plating formed on the conductive pattern. In the inner layer substrate having a plating layer including the inner layer substrate, the plating layer of the inner layer substrate is connected to the conductor pattern on both sides of the insulating layer by the conductive path of the through hole formed in the inner layer substrate, and the side opposite to the side where the concave portion for mounting the semiconductor element is formed. And a second insulating layer, a conductive layer formed on the second insulating layer, and an opening communicating with the conductive layer from the second insulating layer. The opening is formed in an outer layer substrate having an opening surface larger than that of the recess, the recess is located in the opening, and the conductor pattern and the second insulating layer are overlapped to form a pressure-receiving body. Outer layer substrate of multilayer wiring board obtained by hot pressing Method for manufacturing a multilayer wiring board, which comprises forming a conductor pattern on the conductor layer. 2. The method according to claim 1, wherein when forming a conductor pattern on the conductor layer of the outer substrate, a through hole formed in the inner substrate is formed with a through hole having a diameter larger than the diameter of the through hole. A conductive layer on the side opposite to the concave portion for mounting the semiconductor element, which is connected to the conductive pattern of the insulating layer of No. 2 and extending to the end to form a plating layer containing gold plating as an external terminal. The method for manufacturing a multilayer wiring board according to claim 1, wherein