JPS6244448U - - Google Patents
Info
- Publication number
- JPS6244448U JPS6244448U JP1985135527U JP13552785U JPS6244448U JP S6244448 U JPS6244448 U JP S6244448U JP 1985135527 U JP1985135527 U JP 1985135527U JP 13552785 U JP13552785 U JP 13552785U JP S6244448 U JPS6244448 U JP S6244448U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- signal line
- electrodes
- supply electrodes
- line electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 7
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
第1図aは本考案の実施例に係る半導体装置に
おける半導体チツプの底面図、第1図bは第1図
aの半導体装置の基板の平面図、第2図aは従来
の半導体装置における半導体チツプの底面図、第
2図bは第2図aの半導体装置の基板の平面図、
第3図は第1図bの基板の一部縦断面図、第4図
は本考案の実施例に係る半導体装置の一部縦断面
図である。 11……半導体チツプ、12,14……電極、
12a,14a……信号線用電極、12b,14
b……低電源用電極、12c,14c……高電源
用電極、13……基板。
おける半導体チツプの底面図、第1図bは第1図
aの半導体装置の基板の平面図、第2図aは従来
の半導体装置における半導体チツプの底面図、第
2図bは第2図aの半導体装置の基板の平面図、
第3図は第1図bの基板の一部縦断面図、第4図
は本考案の実施例に係る半導体装置の一部縦断面
図である。 11……半導体チツプ、12,14……電極、
12a,14a……信号線用電極、12b,14
b……低電源用電極、12c,14c……高電源
用電極、13……基板。
Claims (1)
- 【実用新案登録請求の範囲】 1 第1、第2の電源用電極及び第1の信号線用
電極を有する半導体チツプと、前記第1、第2の
電源用電極及び第1の信号線用電極に対応する位
置に配設され該第1、第2の電源用電極及び第1
の信号線用電極にそれぞれ接続される第3、第4
の電源用電極及び第2の信号線用電極を有する基
板とを備えた半導体装置において、 前記第1、第2の電源用電極を前記第1の信号
線用電極の内側に配設し、それに相応して前記第
3、第4の電源用電極を前記第2の信号線用電極
の内側に配設し、さらに該第3、第4の電源用電
極のそれぞれを前記基板上にて相互に接続したこ
とを特徴とする半導体装置。 2 前記第3、第4の電源用電極は、前記基板上
にループ状に形成された実用新案登録請求の範囲
第1項記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985135527U JPS6244448U (ja) | 1985-09-04 | 1985-09-04 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985135527U JPS6244448U (ja) | 1985-09-04 | 1985-09-04 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6244448U true JPS6244448U (ja) | 1987-03-17 |
Family
ID=31037793
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1985135527U Pending JPS6244448U (ja) | 1985-09-04 | 1985-09-04 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6244448U (ja) |
-
1985
- 1985-09-04 JP JP1985135527U patent/JPS6244448U/ja active Pending