JPS6351441U - - Google Patents
Info
- Publication number
- JPS6351441U JPS6351441U JP1986144603U JP14460386U JPS6351441U JP S6351441 U JPS6351441 U JP S6351441U JP 1986144603 U JP1986144603 U JP 1986144603U JP 14460386 U JP14460386 U JP 14460386U JP S6351441 U JPS6351441 U JP S6351441U
- Authority
- JP
- Japan
- Prior art keywords
- current flows
- region
- large current
- semiconductor device
- bonding wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000008188 pellet Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
第1図は本考案に係る半導体装置の一実施例を
示すオーデイオ用パワーアンプのICの概略構成
図、第2図は第1図半導体装置の要部平面図、第
3図は従来の半導体装置の一具体例を示すオーデ
イオ用パワーアンプのICの概略構成図、第4図
は第3図半導体装置の要部平面図である。 9……ペレツト、10……小電流が流れる領域
、11……大電流が流れる領域、Vcc1,Vc
c2,M1,M2,G1,G2……電極パターン
、13……ボンデイングワイヤ。
示すオーデイオ用パワーアンプのICの概略構成
図、第2図は第1図半導体装置の要部平面図、第
3図は従来の半導体装置の一具体例を示すオーデ
イオ用パワーアンプのICの概略構成図、第4図
は第3図半導体装置の要部平面図である。 9……ペレツト、10……小電流が流れる領域
、11……大電流が流れる領域、Vcc1,Vc
c2,M1,M2,G1,G2……電極パターン
、13……ボンデイングワイヤ。
Claims (1)
- 大電流が流れる領域と小電流が流れる領域とを
有する半導体ペレツトの電極をボンデイングワイ
ヤを介して外部に引き出した半導体装置において
、上記大電流が流れる電極パターンを大電流が流
れる領域毎に区別して形成し、かつ各電極パター
ン毎に1本のボンデイングワイヤを接続したこと
を特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986144603U JPS6351441U (ja) | 1986-09-20 | 1986-09-20 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986144603U JPS6351441U (ja) | 1986-09-20 | 1986-09-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6351441U true JPS6351441U (ja) | 1988-04-07 |
Family
ID=31055358
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986144603U Pending JPS6351441U (ja) | 1986-09-20 | 1986-09-20 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6351441U (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011100828A (ja) * | 2009-11-05 | 2011-05-19 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
-
1986
- 1986-09-20 JP JP1986144603U patent/JPS6351441U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011100828A (ja) * | 2009-11-05 | 2011-05-19 | Renesas Electronics Corp | 半導体装置及びその製造方法 |