JPS6243972A - Binarization circuit for picture signal in facsimile equipment - Google Patents

Binarization circuit for picture signal in facsimile equipment

Info

Publication number
JPS6243972A
JPS6243972A JP60183520A JP18352085A JPS6243972A JP S6243972 A JPS6243972 A JP S6243972A JP 60183520 A JP60183520 A JP 60183520A JP 18352085 A JP18352085 A JP 18352085A JP S6243972 A JPS6243972 A JP S6243972A
Authority
JP
Japan
Prior art keywords
circuit
signal
average density
delay
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60183520A
Other languages
Japanese (ja)
Inventor
Fukuichi Takamatsu
高松 福一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60183520A priority Critical patent/JPS6243972A/en
Publication of JPS6243972A publication Critical patent/JPS6243972A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a sharp binarization signal by providing an original reading circuit, a line memory circuit, an average density calculating circuit, the first delay circuit, an emphasis circuit, the second delay circuit and a threshold circuit. CONSTITUTION:An original reading circuit 1 optically scans an original surface and photoelectrically converts a reflected light, converts the photoelectrically converted analog picture signal into a digital signal to output a digital picture signal 11. A line memory circuit 2 outputs an one line delay picture signal 12 and a two line delay picture signal 13. An average density (calculating) circuit 3 inputs the picture signal 11 and the delay signals 12, 13, outputs an average density signal 14 of three lines. A delay circuit 4 inputs a delay signal 12 and outputs a delay picture signal 17 delayed by several bits so as to make the signal 12 a center of an average density area. A delay circuit 5 corrects the average density signal by the delay part of an operation by an emphasis circuit 6 and an average density signal 15 and an emphasis circuit output 20 are inputted to a threshold circuit 7 and a binarization signal 16 is outputted. Thereby, a deterioration of the picture signal due to an ability or the like of a reading element can be corrected and a sharp binarization signal output can be obtained.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は1両開号2値化回路に関し、特に、ツアクシ5
り装置の原稿読み取り画信号の2値化処理に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a one-car open code binarization circuit, and in particular, to a one-car open code binary conversion circuit.
The present invention relates to binarization processing of a document reading image signal of a device.

従来の技術 従来のファクシミリ装置においては1M、稿を読み取−
)九アナログ画信号をディジタル画信号に変換し、2値
化しようとする画素に関してその画素の周辺の平均濃度
との関係によりスレツVWルドレベルを決めて2値化し
ていた。
Conventional technology Conventional facsimile machines can read 1M documents.
) Nine analog picture signals are converted into digital picture signals, and the thread VW level for a pixel to be binarized is determined based on the relationship with the average density around the pixel, and binarization is performed.

発明が解決しようとする問題点 しかしながら、上述した従来の2値化回路は。The problem that the invention aims to solve However, the conventional binarization circuit described above.

読み取9回路で読み取ったディジタル画素信号そのもの
とその周辺の平均濃度とを比較する為に。
To compare the digital pixel signal itself read by the reading 9 circuit and the average density of the surrounding area.

2値化する際に読み取り素子の解像度が影響し。The resolution of the reading element affects the binarization.

解像度の劣るものははぎれが悪く、シャープな画像が得
られない等の欠膚を有していた。
Those with poor resolution had defects such as poor peeling and inability to obtain sharp images.

本発明は従来の技術に内在する上記欠点を解消する為罠
なされたものであり、従って本発明の目的は、読み取り
素子の能力等による画信号の劣化を補正するととによっ
て、シャープな2値開号出力を得ることを可能と【、た
新規な画信号2値化回路を提供することにある。
The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the conventional technology, and therefore, an object of the present invention is to correct the deterioration of the image signal due to the ability of the reading element, etc., thereby achieving a sharp binary aperture. An object of the present invention is to provide a novel image signal binarization circuit that makes it possible to obtain a signal output.

問題点を解決するための手段 上記目的を達成する為に1本発明に係るファクシ建す装
置の画信号2値化回路は、原稿を読み取ったアナログ画
信号をNビットのディジタル画素信号に変換する原稿読
み取り回路と、該原稿読み取り回路からのディジタル画
素を数ライン分記憶することができるラインメモリ回路
と、ディジタル画素に対して任意の領域の平均濃度を出
力する平均濃度算出回路とh2値化[、ようとする画素
が平均した領域の中央にくる様にディジタル画素を遅延
させる第1の遅延回路と、遅延させたディジタル画素に
ついて N=A+k (A−B ) N:強調回路出力 A:着目−yg(ディジタル画1g) B;平均濃度 に:強調係数 の演算を行なう強調回路と、前記平均濃度算出回路から
の出力を第2の遅延回路にて遅延させ前記強調回路から
の出力とを比較【7て2値化するスレッシ田ルド回路と
を具備して構成される。
Means for Solving the Problems In order to achieve the above objects, the image signal binarization circuit of the facsimile machine according to the present invention converts an analog image signal obtained by reading a document into an N-bit digital pixel signal. A document reading circuit, a line memory circuit that can store several lines of digital pixels from the document reading circuit, an average density calculation circuit that outputs the average density of an arbitrary area for the digital pixels, and h2 value conversion [ , a first delay circuit that delays a digital pixel so that the pixel to be measured is in the center of the averaged area, and N=A+k (A-B) for the delayed digital pixel. N: Emphasis circuit output A: Attention - yg (digital image 1g) B: To average density: The output from the emphasis circuit that calculates the emphasis coefficient and the average density calculation circuit are delayed by a second delay circuit, and the output from the emphasis circuit is compared [ 7 and a threshold circuit that performs binarization.

実権例 次に本発明をその好ましい一5A−例について図面を参
照して具体的に説明する。
Practical Example Next, a preferred example of the present invention will be explained in detail with reference to the drawings.

第1図は本発明の一実陶例を示すブロック構成図である
FIG. 1 is a block diagram showing an example of the present invention.

図において、原稿読み取り回路111.Il[K積面を
光学走査してその反射光を光電変換」7、光電変換され
たアナログ画信号をディジタルに変換してディジタル画
信号11を出力する(例えば4ビット画信号)、ライン
メモリ回路2は、1ラインずつ2ライン記憶できるよう
になっており、lライン遅延画信号12.2ライン遅延
画信号13をそれぞれ出力する。平均濃度(算出)回路
3は1両省号11゜1ライン遅延信号12.及び2ライ
ン遅延信号13を入力し、3ラインの平均濃度信号@1
4を出力する。
In the figure, a document reading circuit 111. Il [K area is optically scanned and the reflected light is photoelectrically converted] 7, converts the photoelectrically converted analog image signal into digital and outputs digital image signal 11 (for example, 4-bit image signal), line memory circuit 2 is capable of storing two lines one by one, and outputs an 1-line delayed image signal 12 and a 2-line delayed image signal 13, respectively. The average density (calculation) circuit 3 has one line delay signal 11. and the 2-line delayed signal 13 are input, and the 3-line average density signal @1 is input.
Outputs 4.

また、遅延回路4では、1ライン遅延信号12を入力し
、これを平均濃度域(平均濃度回路3の内部で平均した
画信号の範囲)の中心となる様に数ビツト遅延させた遅
延画信号17を出力する。
In addition, the delay circuit 4 inputs the 1-line delayed signal 12 and produces a delayed image signal which is delayed by several bits so as to be in the center of the average density range (the range of the image signal averaged inside the average density circuit 3). Outputs 17.

強調回路6は N=A+k(A−B) N:強調出力20   白MAX≦N≦黒MAXA:遅
延画信号17 B:平均濃度回路14 に:強調係数(任意の値、可変) の演算を行なう回路である。kO値は任意であり。
Enhancement circuit 6 calculates N=A+k(A-B) N: Enhancement output 20 White MAX≦N≦Black MAXA: Delayed image signal 17 B: Average density circuit 14 To: Enhancement coefficient (arbitrary value, variable) It is a circuit. The kO value is arbitrary.

可変である為に1画質及び2値化償号16をみながら、
最適な値を決定することができる。
Since it is variable, while looking at the 1 image quality and the binarization code 16,
The optimal value can be determined.

強調回路6には、遅延画信号17及び平均濃度信号14
が入力され、減算回路8にて前述の式の(A−B)の演
算が行なわれる。減算回路8の減算出力18は乗算回路
9に入力され、に・(A−B)の演算が行なわれる。乗
算回路90乗算出力19と遅延回路4の遅延画信号17
はそれぞれ加算回路10に入力され。
The emphasis circuit 6 includes a delayed image signal 17 and an average density signal 14.
is input, and the subtraction circuit 8 calculates (A-B) in the above-mentioned equation. The subtraction output 18 of the subtraction circuit 8 is input to the multiplication circuit 9, where the calculation of .multidot.(A-B) is performed. Multiplier circuit 90 multiplier output 19 and delay image signal 17 of delay circuit 4
are respectively input to the adder circuit 10.

A−1−k (A−B )の演算が行なわれる。遅延回
路5は平均濃度信号を強調回路6による演算の遅延分を
補正する機能を有し、遅延をもたせた平均濃度信号15
と強調回路出力20けスレッシ冒ルド回路7に入力され
、そこでスレツショルドレベルカ決定され、ディジタル
画素を2値化するスレッショルド回路7にて2値化信号
16が出力される。
The calculation A-1-k (A-B) is performed. The delay circuit 5 has a function of correcting the delay in calculation by the emphasizing circuit 6 for the average density signal, and outputs the delayed average density signal 15.
20 emphasis circuit outputs are input to a threshold circuit 7, where a threshold level is determined, and a binarized signal 16 is outputted by a threshold circuit 7 which binarizes the digital pixel.

発明の詳細 な説明したように1本発明によれば、原稿を読み取った
アナログ信号を2値化しようとする場合に1画情号その
ものを周辺の平均濃度と比較するのではなく1強調回路
にて強調をかけた画素信号と平均濃度を比較してスレッ
ショルドを決定することにより、読み取り素子の能力等
圧よる画信号の劣化を補正することが可能となり、シャ
ープな2値開号出力が得られるという効果が得られる。
As described in detail, according to the present invention, when an analog signal obtained by reading a document is to be binarized, one image information signal itself is not compared with the average density of the surrounding area, but an emphasis circuit is used. By comparing the emphasized pixel signal and the average density to determine the threshold, it is possible to correct the deterioration of the image signal due to the equal pressure of the reading element, and a sharp binary decoding output can be obtained. This effect can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一夾一例を示すブロック構成図である
。 1・・・原稿読み取り回路、2・・・ラインメモリ回路
。 3・・・平均濃度回路、4・・・遅延回路、5・・・遅
延回路。
FIG. 1 is a block diagram showing one example of the present invention. 1... Original reading circuit, 2... Line memory circuit. 3... Average density circuit, 4... Delay circuit, 5... Delay circuit.

Claims (1)

【特許請求の範囲】[Claims] 原稿面を光学走査し原稿面の透過光又は反射光を集光し
て光電変換することにより書画情報を読みとるファクシ
ミリ走査装置において、光電変換されたアナログ画信号
をビットパラレルなディジタル信号に変換して出力する
原稿読み取り回路と、該原稿読み取り回路から出力され
るディジタル画素を数ライン分記憶することができるラ
インメモリ回路と、ディジタル画素に対して所定の領域
の平均濃度を出力する平均濃度算出回路と、2値化しよ
うとする画素が平均した領域の中央にくる様にディジタ
ル画素を遅延させる第1の遅延回路と、該第1の遅延回
路により遅延させたディジタル画素と前記平均濃度算出
回路からの平均濃度出力とを入力して強調演算を行ない
強調されたディジタル信号を出力する強調回路と、前記
平均濃度算出回路からの出力を強調演算回路で遅延した
分を遅延させる第2の遅延回路と、該第2の遅延回路の
出力と前記強調回路からの出力とを用いてディジタル画
素を2値化するスレッショルド回路とを有することを特
徴としたファクシミリ装置の画信号2値化回路。
In a facsimile scanning device that reads document information by optically scanning the document surface, condensing transmitted or reflected light from the document surface, and photoelectrically converting it, the photoelectrically converted analog image signal is converted into a bit-parallel digital signal. An original reading circuit that outputs an original, a line memory circuit that can store several lines of digital pixels output from the original reading circuit, and an average density calculation circuit that outputs an average density of a predetermined area for the digital pixels. , a first delay circuit that delays a digital pixel so that the pixel to be binarized comes to the center of the averaged area, and a digital pixel delayed by the first delay circuit and a signal from the average density calculation circuit. an emphasis circuit that inputs the average density output, performs emphasis calculation, and outputs an emphasized digital signal, and a second delay circuit that delays the output from the average density calculation circuit by an amount delayed by the emphasis calculation circuit; An image signal binarization circuit for a facsimile machine, comprising a threshold circuit that binarizes a digital pixel using the output of the second delay circuit and the output from the emphasis circuit.
JP60183520A 1985-08-21 1985-08-21 Binarization circuit for picture signal in facsimile equipment Pending JPS6243972A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60183520A JPS6243972A (en) 1985-08-21 1985-08-21 Binarization circuit for picture signal in facsimile equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60183520A JPS6243972A (en) 1985-08-21 1985-08-21 Binarization circuit for picture signal in facsimile equipment

Publications (1)

Publication Number Publication Date
JPS6243972A true JPS6243972A (en) 1987-02-25

Family

ID=16137283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60183520A Pending JPS6243972A (en) 1985-08-21 1985-08-21 Binarization circuit for picture signal in facsimile equipment

Country Status (1)

Country Link
JP (1) JPS6243972A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02163883A (en) * 1988-12-16 1990-06-25 Pfu Ltd Picture processing system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02163883A (en) * 1988-12-16 1990-06-25 Pfu Ltd Picture processing system
JPH0561677B2 (en) * 1988-12-16 1993-09-06 Pfu Ltd

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