JPH06292005A - Picture signal processing unit - Google Patents

Abstract

PURPOSE:To obtain a sharp binary picture by eliminating occurrence of moire. CONSTITUTION:A filter 2 attenuates a high frequency component in the tilt direction of a noted picture element and amplifies a high frequency component in the main scanning and subscanning directions. The filter coefficient is inputted from an input means 32 based on a characteristic of an input picture to vary the filter characteristic. An error correction circuit 3 obtains a difference between an output of the filter 2 and its weight and a thresholding comparator 5 threshold processes the difference. A difference between the binary value and the output of the error correction circuit 3 is obtained and stored in an error storage circuit 8, a weight addition circuit 9 calculates a weight multiplying a predetermined weight coefficient with a difference of a succeeding noted picture element with respect to its peripheral picture elements to provide an output to the error correction circuit 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing device for binarizing a multi-tone image input.

[0002]

2. Description of the Related Art An output image obtained by binarizing a multi-tone image obtained by reading an original with a scanner or the like in pixel units generally blurs or produces fine light and shade. Therefore, the blur is restored and the image is sharpened. Processing is required.

An example of such processing will be described. As shown in FIG. 16, a multi-gradation image input 1 has a Laplacian edge enhancement filter 2 that amplifies high-frequency components in the main scanning direction, sub-scanning direction, and diagonal direction of a pixel of interest to generate an image of character edges and line alternations. Is emphasized. Next, in synchronization with the filter output data, the dither pattern read from the dither pattern generating circuit 73 and the filter output data are compared by the binarizing comparator 5 and binarized to become a halftone image output 6.

FIG. 17 shows the coefficients of the Laplacian type edge enhancement filter, and FIG. 18 shows the spatial frequency of the Laplacian type filter.
Amplitude gain characteristics are shown. This edge enhancement filter is shown in Figure 17
As shown in, the filter coefficient of the pixel adjacent to the target pixel in the main scanning / sub scanning direction is set to a negative value, and the filter coefficient of the pixel adjacent to the diagonal direction is set to zero or a negative coefficient. FIG. 18 shows the amplitude characteristics of the spatial frequency spatial filter from the pixel of interest in the main scanning direction and the sub-scanning direction. The spatial frequency obtained by applying the matrix shown in FIG. 17 to the pixel of interest and the pixel adjacent to this pixel of interest.・ Shows amplitude gain characteristics. According to this figure, in the case of the filter shown in FIG. 17, it is understood that the high-frequency component in the main scanning direction and the sub-scanning direction is amplified, and at the same time, the high-frequency component in the oblique direction is further amplified.

[0005]

A commonly used photographic image with a screen angle of 45 degrees and a hatched 133 to 150 lines is a resolution of 8 lines / mm (4 line pairs / mm).
When the image was read in and the edge was emphasized by the conventional Laplacian type spatial filter, a remarkable moire occurred in the multi-valued image of the filter output.

This is because the reading sampling frequency (4
Frequency components in the main scanning direction of the shaded image near the line pair / mm) (133 lines: about 3.8 line pairs / mm, 15
This is because there are 0 lines: about 4.2 line pairs / mm). FIG. 19 shows the relationship between the phase of the reading sampling window and the phase of the shaded image.The squares shown by the thick lines in the figure indicate the sampling windows of each line and correspond to the average reflectance in each window. The image signal level is obtained.

The multi-valued image input to the spatial filter is shown in FIG.
As shown in (a), an image signal of 1-pixel alternation is generated in a portion where the phase of the read sampling and the phase of the shaded image match, and in a portion where the phase shift is large as shown in FIG. The intermediate level corresponds to the dot pattern.

When an image signal input at such a multi-valued level is processed by a conventional Laplacian type edge enhancement filter, the diagonal direction is enhanced (stronger than the main scanning / sub scanning direction), so that one pixel alternates. Image signal is amplified
In the image having the same phase shown in 19 (a), the 1-pixel alternation is emphasized to become an image of 1-pixel alternation of white and black levels.

On the other hand, in the image in which the phases do not match as shown in FIG. 19 (b), there is little difference in level between black and white, and even if they are emphasized, the level becomes an intermediate level. As a result, moire was generated.

Further, when the data is subjected to dither processing, there is a problem that significant moire occurs due to the interference between the black-and-white periodic pattern of the shaded image and the period of the dither pattern when the phases match. .

Further, when the error diffusion process is performed instead of the dither process, different textures are generated at a part where the phase matches and a part where the phase does not match, resulting in moire. If the emphasis of the filter is weakened, the moire will be reduced, but it will not be perfect, and the problem that the resolution of the character / line drawing will be lost has occurred.

As a pre-processing of the conventional Laplacian filter, it is possible to convert an image of one pixel alternating to an average level and remove moire by performing an arithmetic mean of two pixels in the main scanning direction. The edge enhancement effect is lost due to the arithmetic mean calculation, and an image of alternating one line such as a resolution pattern cannot be reproduced.

The present invention has been made in view of the above problems, and an image signal processing apparatus for binarizing a multi-tone image by using a filter which removes moire and obtains a sharp image. The purpose is to provide.

[0014]

In order to achieve the above object, input means for inputting a positive value A and a negative value -B as a filter coefficient, and the input value A in the main scanning and sub-scanning directions of a pixel of interest. The input value −B as the filter coefficient of the pixel adjacent to the target pixel in the diagonal direction, 1 + 4B-4A as the filter coefficient of the target pixel, and the target pixel of the input multi-tone image. A saddle-type edge enhancement filter that multiplies the peripheral pixels by each filter coefficient and outputs the sum as a filter correction value, an error correction circuit that calculates the difference between this filter correction value and the error integrated value, and this error correction circuit , A difference circuit for calculating the difference between the output of the binarization unit and the output of the error correction circuit, and the periphery of the pixel of interest next to the difference value. Pixel correspondence That is a by multiplying the predetermined error distribution coefficient difference value the error integrated value is the sum that a error integrated value calculating means for outputting to said error correcting circuit.

Further, a binarization decoder for computing a binarization level from the sign bit and upper bits of the data output from the error correction circuit is provided in place of the binarization means.

Further, the error integrated value calculating means stores an error storage circuit for storing the difference value as an error value corresponding to the target pixel and its peripheral pixel, and a peripheral pixel of the next target pixel from the error storage circuit. The weighting addition circuit reads out the corresponding error value, multiplies it by a predetermined error distribution coefficient, and outputs the sum of the error integrated values to the error correction circuit.

Further, the error integrated value calculating means associates the difference value with the target pixel and its peripheral pixels, multiplies a predetermined weighting coefficient and outputs the error weighting distribution circuit for each peripheral pixel, and the error weighting circuit. The output of the distribution circuit is made to correspond to each peripheral pixel position of the next pixel of interest, and an integrated addition circuit for outputting the error integrated value, which is a value sequentially integrated and added, to the error correction circuit.

Further, input means for inputting a positive value A and a negative value -B as a filter coefficient, and the input value A as a filter coefficient of a pixel adjacent in the main scanning and sub-scanning directions of the pixel of interest, the input The value -B is used as the filter coefficient of the pixel adjacent in the diagonal direction to the target pixel, 1 + 4B-4A is used as the filter coefficient of the target pixel, and the target pixel of the input multi-gradation image and its peripheral pixels are multiplied by the filter coefficients. , A saddle-type edge enhancement filter that outputs the sum as a filter correction value, a dither pattern generation circuit, a dither pattern that is output from this dither pattern generation circuit in synchronization with the input multi-tone image, and the filter correction value. Compare
And a binarization comparator for determining the binarization level of the pixel of interest.

Further, input means for inputting a positive value A and a negative value -B as a filter coefficient, and the input value A as a filter coefficient of a pixel adjacent in the main scanning direction and the sub scanning direction of the target pixel The value -B is used as the filter coefficient of the pixel adjacent in the diagonal direction to the target pixel, 1 + 4B-4A is used as the filter coefficient of the target pixel, and the target pixel of the input multi-gradation image and its peripheral pixels are multiplied by the filter coefficients. , A saddle-type edge enhancement filter that outputs the sum as a filter correction value, a dither pattern generation circuit, a dither pattern that is output from this dither pattern generation circuit in synchronization with the input multi-tone image, and the filter correction value. And an binarizing means for binarizing the output of the added value.

The binarizing means compares the output of the adder with a predetermined slice level to determine the binarizing level of the pixel of interest.

Further, the binarizing means outputs the presence or absence of the carry bit of the adder as a binarized value.

[0022]

The saddle type edge emphasizing filter of the present invention is composed of the spatial filter coefficients shown in FIG. 2, and attenuates the high frequency components in the diagonal direction of the target pixel and amplifies the high frequency components in the main scanning direction and the sub scanning direction. . From the input means, A, B
For, enter an appropriate value for the input image. As a result, the image of the alternating edge lines in the main scanning direction and the sub-scanning direction, which is often found in the character portion, is emphasized, and the image of the one-pixel alternating portion in the shaded photograph portion is smoothed.

An error correction circuit obtains the difference between the filter correction value passed through this filter and an error integrated value, which will be described later, and binarizes it by a predetermined milling level to output a halftone image. . The difference circuit obtains a difference value between the binarized value and the output of the error correction circuit, and of the difference values, the difference value corresponding to the peripheral pixel of the next pixel of interest is multiplied by a predetermined error distribution coefficient. , The sum of the errors is output to the error correction circuit. As a result, the error caused by binarization can be corrected and a halftone image can be output.

At this time, instead of the binarizing means, the sign bit and the high-order bit of the data output from the error correction circuit are binarized by the binarizing decoder. The slice level of the binarized value obtained from the sign bit and the upper bit can be arbitrarily set by the setting of the binarized decoder.

Further, the error integrated value calculating means stores the difference value from the difference circuit in the error storage circuit corresponding to the peripheral pixels of the target pixel as shown in FIG. The values indicated by K, L, M, and N are weighted to the difference value with respect to the periphery of the pixel of interest, and the sum is input to the error correction circuit as the above-described error integrated value. As a result, the error caused by binarization can be corrected and a halftone image can be output.

The error integrated value calculating means divides the difference value from the difference circuit by the error weighting distribution circuit into peripheral pixels of the target pixel as shown in FIG. 8B, multiplies the weighting coefficient, and multiplies the integrated addition circuit. Then, an error integrated value, which is a value obtained by sequentially integrating and adding it corresponding to each peripheral pixel position of the next target pixel, is input to the error correction circuit. As a result, the error caused by binarization can be corrected and a halftone image can be output.

The filter correction value described above and the dither pattern output from the dither pattern generation circuit in synchronization with the multi-tone image input to the saddle type edge enhancement filter are compared by the binarization comparison circuit to obtain 2 Quantize and output halftone image.

Further, the above-mentioned filter correction value and the dither pattern output from the dither pattern generating circuit in synchronization with the multi-tone image input to the saddle type edge enhancement filter are added by an adder, and the added value is added. The output is binarized by the binarizing means and a halftone image is output.

The binarizing means compares the added value with a predetermined slice level by a binarizing comparator to binarize it, and outputs a halftone image.

Further, the binarizing means can output a halftone image by outputting as the binarized value when the adder adds, the case with the carry bit and the case without the carry bit.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. In the figure, 1 is a multi-gradation image input, 2 is a saddle type edge enhancement filter that attenuates high frequency components in the diagonal direction of the pixel of interest and amplifies high frequency components in the main scanning direction and the sub scanning direction, and 32 is a filter. An emphasis coefficient input unit for inputting the coefficients A and B, 3 is an error correction circuit for adding integration errors of peripheral pixels, 4 is a predetermined slice level, and 5 is the output of the error correction circuit 3 and slice level 4. A binary comparator, 6 is a halftone image output, and 7 is a difference circuit for calculating the difference between the output value of the error correction circuit 3 and the binarized value as error data.

Reference numeral 8 is an error storage circuit for storing error data corresponding to the position of the pixel of interest and reading a set of error data at the peripheral pixel position of the pixel of interest. Reference numeral 9 is a peripheral error read from the error storage circuit 8. A weighting addition circuit that multiplies the data by a predetermined coefficient and outputs a weighted value that is the sum thereof to the error correction circuit 3, 40 is for shifting 1 line data 1
Line error memories, 41 to 43 are 1 pixel shift registers for shifting 1 pixel data, 44 to 47 are multipliers for multiplying weighting coefficients, and 48 to 50 are adders for calculating summation.

FIG. 2 shows the spatial filter coefficient of 3 × 3 pixels in the saddle emphasis filter according to the embodiment of the present invention.
Since the pixel adjacent to the center pixel of interest in the main scanning direction and the sub-scanning direction has a positive coefficient A and the pixel adjacent to the diagonal direction has a negative coefficient -B, the coefficient of the entire filter is set to 1 Is 1 + 4B-4A.

FIG. 3 shows that A = 1 in the filter shown in FIG.
It is a figure which shows / 8 and B = K, and shows an example of a circuit structure of the filter which has the filter coefficient shown in FIG. In FIG. 3, reference numerals 11 and 12 are accumulated from one line in the main scanning direction, respectively.
1 line buffer memory for line shift, 17 and 18 are stored in 1 line buffer memory 12 respectively
A pixel shift register for generating pixel information of pixels (h) and (i) in FIG. 4 by shifting the pixel information for each row for each pixel, and 15 and 16 are the same as those described above from the 1-line buffer memory 11 in FIG. A 1-pixel shift register for generating pixel information of pixels (e) and (f), and 13 and 14 are 1-pixel shift registers for generating pixel information of pixels (b) and (c) in FIG. 4, respectively.

Reference numerals 19, 20 and 21 denote adders for adding the pixel information of pixels adjacent to each other in the main scanning direction and the sub-scanning direction of the target pixel, and 29 denotes a multiplier for multiplying the addition result by a positive coefficient ⅛, 22,2
Reference numerals 3 and 24 denote adders for adding the pixel information of pixels adjacent to the target pixel in the diagonal direction, 28 denotes a multiplier for multiplying the addition result by a negative coefficient −K, and 27 denotes the target pixel as a whole filter coefficient of 1
A multiplier that multiplies the coefficient 4K + 1/2 for
Reference numeral 26 is an adder for adding each pixel information multiplied by each coefficient by the above-mentioned multipliers 27, 28, 29. Reference numeral 30 is a filter output, 31 is a filter coefficient conversion circuit for converting an emphasis coefficient into a filter coefficient, and 32 is an emphasis coefficient input unit.

The operation of the saddle-type edge emphasizing filter configured as described above will be described below. In FIG. 3, the emphasis coefficient K input from the emphasis coefficient input unit 32.
Is a filter coefficient 4K + 1 by the filter coefficient conversion circuit 31.
The image signal converted into / 2 and -K and input by a scanner (not shown) stores the pixel information of the first line in the main scanning direction in the 1-line buffer memory 11, and in the second line input next, After storing the information of the 1-line buffer memory 11 in the 1-line buffer memory 12,
The pixel information of the second line is stored in the one-line buffer memory 11, and this operation is repeated for each line to constantly generate an image signal shifted by three lines. Then, the image signals for the three lines are shifted pixel by pixel by the 1-pixel shift registers 13 to 18 to generate the input image signal of the pixel information to the 3 × 3 matrix shown in FIG. 4 for each pixel. Signals a to i corresponding to the matrix shown in FIG. 4 are generated.

Here, as shown in FIG. 3, the multiplier 27 multiplies the target pixel e by the coefficient 4K + 1/2. Also adder 19,2
The pixels 0 and 21 cumulatively add the pixels b, d, f, and h that are adjacent to the pixel of interest e in the main scanning and sub scanning directions, and the multiplier 29 multiplies the addition result by 1/8. Further, the adders 22, 23, 24 cumulatively add the pixels a, c, g, i adjacent to the pixel of interest e in the diagonal direction, and the multiplier 28 multiplies the addition result by a negative coefficient -K. The adders 25 and 26 add the results obtained by the multipliers 27, 28 and 29 to obtain the image processing result for the target pixel e. Thereafter, the pixel of interest is shifted pixel by pixel to the next pixel and the same calculation is performed.

FIG. 5 shows the spatial frequency / amplitude gain characteristics of the filter when K = 1/8, FIG. 6 is K = 1/4, and FIG. 7 is K = 3/8. As the value of K is increased, the amplitude gain of the high-frequency component in the main scanning direction and the sub-scanning direction is increased, and the amplitude gain of the high-frequency component in the oblique direction is suppressed to be low in any case. The one-pixel alternating moire image generated in the image is attenuated. Furthermore, K
It can be seen that the strength of the emphasis can be controlled while maintaining the characteristics of the filter only by the value of.

For the coefficient K, the frequency response is given as a two-dimensional Fourier transform of the spatial filter coefficient h (K1, K2), and in this case, it is expressed by the following equation.

[0041]

[Equation 1]

Returning to FIG. 1, in the multi-gradation image input 1, the high frequency components in the diagonal direction of the target pixel are attenuated by the saddle type edge enhancement filter 2, and the high frequency components in the main scanning direction and the sub scanning direction are amplified. . Therefore, there are many main scans in the character part.
The image of alternating edges and lines in the sub-scanning direction is emphasized, and the image of alternating 1-pixel in the shaded photograph portion is smoothed.

Next, the sum of the weighting errors of the peripheral pixels that have already been halftoned is subtracted by the error correction circuit 3, and the data is binarized by the binarized comparator 5 to become the halftone image output 6. Next, in the difference circuit 7, 1 of the binarized data is set to the white level ((6F) hexadecimal display for 6-bit processing), 0
The black level ((00) hexadecimal display for 6-bit processing)
Then, the data before binarization is subtracted from the value to obtain error data.

Next, the error data is stored in the error storage circuit 8 as 1
One pixel is shifted by the pixel shift register 43, and the current pixel address of interest in the one-line error memory 40 is written. Next, the data of the address of the current pixel-of-interest address + 1 from the 1-line error memory 40 (data written in the line 1 line before)
Is read out and shifted for each pixel by the 1-pixel shift registers 42 and 43. From the above operation of the error storage circuit 8, 1 pixel before the current pixel of interest, 1 pixel before 1 line, 1 line before,
The error data of the peripheral pixel position of one pixel before one line before is output to the weighting addition circuit 9.

In the weighting adder circuit 9, the multipliers 44 to 47 multiply the weighting coefficients K, L, M, N and (K + L + M + N = 1), and the adders 48 to 50 calculate the sum and output it to the error correction circuit 3.

FIG. 8 shows a target pixel X and weighting factors K, L,
It is a figure showing the physical relationship of the peripheral pixel to which M and N correspond.

The above operation is repeated for each pixel.

Next, a second embodiment will be described. FIG. 9 is a block diagram showing the configuration of this embodiment. In this embodiment, the binarization comparator 5 of the first embodiment shown in FIG. 1 is replaced by a binarization decoder 5a, and the same symbols as those in FIG. 1 indicate the same members.

In this embodiment, the multi-tone image input is 4 bits (16
The description will be made assuming that the input is in gradation. As a result, the output of the saddle type edge enhancement filter 2 is also 4 bits. On the other hand, the number of bits output from the weighted addition circuit 9 is a total of 5 bits, that is, a sign bit and 4 bits. Considering the case where carry occurs when the difference between 4 bits and sign + 4 bits is calculated by the error correction circuit 3, a total of 6 bits of sign + 5 bits are output.

The binarization decoder 5a is assumed to perform decoding with a code bit and two high-order bits of 3 bits.

FIG. 10A shows the decoding contents of the binarization decoder 5a. As a result, an input multi-tone image can be output at a level of 50%. The slice level can be changed by changing the decoding method. Figure 10
(B) is a figure which shows an example of the gate which implement | achieves the binary decoding 5a. This figure shows the case where the output of the error correction circuit 3 is the sign bit + 5 bits.

In the present embodiment, the input multi-gradation image is 4 bits and the decoding is the sign bit + higher 2 bits, but these are examples and other values are also possible.

Next, the third embodiment will be described. Figure 11 is the third
The structure of an Example is shown. This embodiment differs from the first embodiment in the error weight distribution circuit 60 and the integrated addition circuit 61, and
The same reference numerals denote the same members. The same applies to the subsequent drawings.

An error weight distribution circuit 60 distributes the error data to the peripheral pixels by a predetermined weighting coefficient,
Reference numeral 61 is an integrated adder circuit that performs integrated addition while sequentially shifting the errors distributed by the error weighting distribution circuit in correspondence with peripheral pixel positions, 62 to 65 are multipliers for multiplying weighting coefficients, and 66 to 68 are 1 pixel data. 1-pixel shift register for shifting, 69 to 71 are adders for performing integrated addition, and 72 is a 1-line error memory for shifting 1-line data.

Next, an error weight distribution circuit peculiar to this embodiment
The operation of 60 and the integrated adder circuit 61 will be described.

The error data from the difference circuit 7 is weighted by the weighting coefficient K, by the multipliers 62 to 65 of the error weight distribution circuit 60.
L, M, N, (K + L + M + N = 1) are multiplied to obtain FIG.
The error is distributed to the peripheral pixels as shown in FIG.
Output to 61. The arrangement of the peripheral pixels corresponding to K, L, M, and N is the same as in FIG.

In the integrated adder circuit 61, the error data multiplied by the L, M and N coefficients are integrated and added while shifting the data for each pixel by the 1-pixel shift registers 67, 68 and the adders 70, 71, The data of the address of the current pixel of interest of the one-line error memory 72 is written, and then the data of the address of the current pixel of interest address + 1 (the data written one line before) is input to the read adder 69. Meanwhile K
The error data multiplied by the coefficient is the 1-pixel shift register
One pixel is shifted by 66, and added by the adder 69 with the integration error of one line before (1 pixel before data × L, 1 line before data × M, 1 line before 1 pixel after data × N) And output to the error correction circuit 3. The above operation 1
Repeated for each pixel.

Next, a fourth embodiment will be described. FIG. 12 shows the configuration of this embodiment. In this embodiment, the binarization comparator 5 is replaced with a binarization decoder 5a in the third embodiment shown in FIG. The operation of the binarization decoder 5a is the same as that shown in FIG. 10 described in the second embodiment.

Next, a fifth embodiment will be described. FIG. 13 shows the configuration of this embodiment. In the figure, reference numeral 73 is a dither pattern generation circuit for generating a dither pattern in synchronization with the output data of the saddle type edge enhancement filter 2, and a binary comparator 5
Compares the output data of filter 2 with the dither pattern
The binarized value is determined and the halftone image 6 is obtained.

Next, a sixth embodiment will be described. FIG. 14 shows the configuration of this embodiment. In the figure, 73 is a dither pattern generator, which is the same as that of the fifth embodiment.

The dither pattern data read from the dither pattern generating circuit 73 and the filter output data in synchronization with the output data of the saddle type edge enhancement filter 2 are added by an adder.
The value is added at 74, and compared with the predetermined slice level 4 by the binarization comparator 5, and binarized to obtain the halftone image output 6.

Next, a seventh embodiment will be described. FIG. 15 shows the configuration of this embodiment. This embodiment is the second embodiment of the sixth embodiment shown in FIG.
Except for the binarizing comparator 5, the adder is changed to an adder with a carry bit.

The binarized value is determined depending on whether or not the adder with carry bit outputs the carry bit, whereby the halftone image output 6 is obtained.

[0064]

As is apparent from the above description, according to the present invention, the saddle-type edge enhancement filter output is obtained by inputting the saddle-type edge enhancement filter coefficient from the input means according to the characteristics of the input image. When halftone processing is performed, halftone images of mixed characters, photographs and half-tone photographs are printed in order to prevent moire from appearing in the shaded photo areas such as gravure printing, and to emphasize letters and line drawings to prevent irregularities and discontinuities. It is possible to improve both the gradation and resolution of the image quality of a toned image.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a diagram showing coefficients of a saddle type edge enhancement filter of the present invention.

FIG. 3 is a configuration diagram of a saddle type edge enhancement filter of the present invention.

FIG. 4 is a diagram showing saddle type edge enhancement filter coefficients used in the present embodiment.

FIG. 5 is a spatial frequency / amplitude gain characteristic diagram of a saddle type edge enhancement filter when K = 1/8.

FIG. 6 is a spatial frequency / amplitude gain characteristic diagram of a saddle type edge enhancement filter when K = 1/4.

FIG. 7 is a spatial frequency / amplitude gain characteristic diagram of a saddle type edge enhancement filter when K = 3/8.

FIG. 8 is a diagram showing peripheral pixels corresponding to weighting coefficients.

FIG. 9 is a configuration diagram of a second embodiment.

FIG. 10 is a diagram showing a configuration example of a binarization decoder.

FIG. 11 is a configuration diagram of a third embodiment.

FIG. 12 is a configuration diagram of a fourth embodiment.

FIG. 13 is a configuration diagram of a fifth embodiment.

FIG. 14 is a configuration diagram of a sixth embodiment.

FIG. 15 is a configuration diagram of a seventh embodiment.

FIG. 16 is a block diagram of an image signal processing device using a conventional Laplacian edge enhancement filter.

FIG. 17 is a diagram showing coefficients of a conventional Laplacian edge enhancement filter.

FIG. 18 is a spatial frequency / amplitude gain characteristic diagram of a conventional Laplacian edge enhancement filter.

FIG. 19 is a diagram showing a relationship between a sampling frequency for image reading and a frequency component of a shaded image.

[Explanation of symbols]

 1 multi-tone image input 2 saddle type edge enhancement filter 3 error correction circuit 32 enhancement coefficient input section 4 slice level 5 binarization comparator 5a binarization decoder 6 halftone image output 7 difference circuit 8 error storage circuit 9 weighted addition Circuit 60 Error weight distribution circuit 61 Integrated addition circuit 73 Dither pattern generation circuit 74 Adder

Claims (8)

[Claims] 1. A positive value A and a negative value − as a filter coefficient.
Input means for inputting B, the input value A as a filter coefficient of a pixel adjacent to the target pixel in the main scanning and sub-scanning directions, and the input value -B as a filter coefficient of a pixel adjacent to the target pixel in an oblique direction. , 1 + 4B-4A as a filter coefficient of the pixel of interest, a pixel of interest of the input multi-tone image and its surrounding pixels are multiplied by each of the filter coefficients, and a saddle type edge enhancement filter that outputs the sum as a filter correction value, An error correction circuit that calculates the difference between the filter correction value and the error integrated value, a binarization unit that binarizes the output of the error correction circuit, an output of the binarization unit, and an output of the error correction circuit. And a difference circuit for calculating the difference value of the difference pixel, and the difference value corresponding to the peripheral pixel of the next pixel of interest is multiplied by a predetermined error distribution coefficient, and the error integrated value, which is the sum of the difference values, is corrected by the error correction. To the circuit An image signal processing apparatus is characterized in that a error integrated value calculating means for force. 2. A binarization decoder for computing a binarization level from a sign bit and upper bits of data output from the error correction circuit is provided in place of the binarization means. 1. The image signal processing device according to 1. 3. The error integrated value calculation means stores an error storage circuit for storing the difference value as an error value corresponding to the target pixel and its peripheral pixel, and a peripheral pixel of the next target pixel from the error storage circuit. 3. A weighted addition circuit for reading the corresponding error value, multiplying it by a predetermined error distribution coefficient, and outputting the sum of the error integrated values to the error correction circuit. Image signal processing device. 4. An error weight distribution circuit, in which the error integrated value calculation means associates the difference value with a pixel of interest and its peripheral pixels, multiplies by a predetermined weighting coefficient, and outputs for each peripheral pixel, and this error weighting. 2. An integrated addition circuit for outputting the error integrated value, which is a value obtained by sequentially integrating and adding the output of the distribution circuit to each peripheral pixel position of the next target pixel, to the error correction circuit. Alternatively, the image signal processing device according to item 2. 5. A positive value A and a negative value − as a filter coefficient.
Input means for inputting B, the input value A as a filter coefficient of a pixel adjacent to the target pixel in the main scanning and sub-scanning directions, and the input value -B as a filter coefficient of a pixel adjacent to the target pixel in an oblique direction. , 1 + 4B-4A as a filter coefficient of the pixel of interest, a pixel of interest of the input multi-tone image and its surrounding pixels are multiplied by each of the filter coefficients, and a saddle type edge enhancement filter that outputs the sum as a filter correction value, Binarization for comparing the dither pattern generation circuit, the dither pattern output from the dither pattern generation circuit in synchronization with the input multi-tone image with the filter correction value, and determining the binarization level of the pixel of interest. An image signal processing device comprising: a comparator. 6. A positive value A and a negative value − as a filter coefficient.
Input means for inputting B, the input value A as a filter coefficient of a pixel adjacent to the target pixel in the main scanning and sub-scanning directions, and the input value -B as a filter coefficient of a pixel adjacent to the target pixel in an oblique direction. , 1 + 4B-4A as a filter coefficient of the pixel of interest, a pixel of interest of the input multi-tone image and its surrounding pixels are multiplied by each of the filter coefficients, and a saddle type edge enhancement filter that outputs the sum as a filter correction value, A dither pattern generation circuit, an adder that adds the dither pattern output from the dither pattern generation circuit in synchronization with the input multi-tone image and the filter correction value, and the output of this addition value is binarized. An image signal processing device, comprising: a binarizing unit. 7. The binarization unit compares the output of the adder with a predetermined slice level to determine the binarization level of the pixel of interest.
The image signal processing device described. 8. The image signal processing apparatus according to claim 6, wherein the binarizing means outputs the presence or absence of a carry bit of the adder as a binarized value.