JPH06291993A - Picture signal processing unit - Google Patents

Abstract

PURPOSE:To obtain a sharp binary picture in which occurrence of moire is eliminated. CONSTITUTION:A high frequency component of a picture element of interest in a slant direction is attenuated by a filter 2 and a high frequency component in the main scanning/subscanning direction is amplified. A difference between an output of the filter 2 and its weight value is obtained by an error correction circuit 3 and threshold processed by a thresholding comparator 5. A difference value between the threshold processed valve and an output of the error correction circuit 3 is obtained and stored in an error storage circuit 8, a weighting addition circuit 9 calculates a weight value resulting from multiplying a predetermined weight coefficient with a difference value between a succeeding picture element of interest and its surrounding picture elements and provides an output to the error correction circuit 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing device for binarizing a multi-tone image input.

[0002]

2. Description of the Related Art An output image obtained by binarizing a multi-tone image obtained by reading an original with a scanner or the like in pixel units generally blurs or produces fine light and shade. Therefore, the blur is restored and the image is sharpened. Processing is required.

An example of such processing will be described. As shown in FIG. 14, a multi-gradation image input 1 has a Laplacian edge enhancement filter 2 that amplifies high-frequency components in the main scanning direction, sub-scanning direction, and diagonal direction of a pixel of interest, and creates an image of character edges and line alternations. Is emphasized. Next, in synchronization with the filter output data, the dither pattern read from the dither pattern generating circuit 73 and the filter output data are compared by the binarizing comparator 5 and binarized to become a halftone image output 6.

FIG. 15 shows the coefficients of the Laplacian edge enhancement filter, and FIG. 16 shows the spatial frequency characteristics of the Laplacian filter. FIG. 16 shows the amplitude characteristics of the spatial frequency spatial filter from the pixel of interest in the main scanning direction and the sub-scanning direction.
The spatial frequency vs. amplitude characteristics obtained by applying the matrix shown in FIG. According to this figure, in the case of the filter shown in FIG. 15, it is understood that the high frequency components in the main scanning direction and the sub scanning direction are amplified, and at the same time, the high frequency components in the oblique direction are further amplified.

[0005]

In the above-mentioned case, since the Laplacian type edge enhancement filter also enhances the diagonal direction (stronger than the main scanning direction and the sub scanning direction), in the halftone photograph block diagram such as gravure printing, As shown in (a) of FIG. 17, the black-and-white pattern of the shaded image is more emphasized at the portion where the phase of the read sampling and the phase of the shaded image match, while the portion where the phase does not match is intermediate as shown in (b). Image data with the multi-valued level maintained and the phase matching / mismatching emphasized more, and when the data is further dithered, the black-and-white periodic pattern and the dither pattern of the shaded image are matched at the phase matching. There was a problem that remarkable moire was caused in the interference of the cycle.

FIG. 17 shows the relationship between the phase of the sampling frequency for reading and the phase of the shaded image. The nine bold pixels in the figure correspond to the pixels of the spatial filter shown in FIG. As shown in (a), the pixel-valued multi-valued image input to the spatial filter becomes a pixel alternating image signal at a position where the phase of the reading sampling frequency and the phase of the shaded image match, and (b) As shown in (3), in the areas where the phases do not match, the halftone multilevel corresponding to the halftone dot pattern is obtained.

When the error diffusion process is performed instead of the dither process, different textures are generated at a part where the phase matches and a part where the phase does not match, resulting in moire. If the emphasis of the filter is weakened, the moire will be reduced, but it will not be perfect, and the problem that the resolution of the character / line drawing will be lost has occurred.

The present invention has been made in view of the above problems, and an image signal processing apparatus for binarizing a multi-tone image by using a filter and a filter capable of removing a moire and obtaining a sharp image. The purpose is to provide.

[0009]

In order to achieve the above object, a filter coefficient of a pixel adjacent to a target pixel in the main scanning direction and the sub-scanning direction is set to a positive value, and a filter coefficient of a pixel adjacent to the target pixel in an oblique direction is set. Is a negative value, and has a filter coefficient in which the sum of coefficients including the filter coefficient of the target pixel is 1, and the target pixel of the input multi-tone image and its peripheral pixels are multiplied by each of the filter coefficients, and the total sum thereof is obtained. A saddle type edge enhancement filter for calculating a filter correction value, an error correction circuit for calculating a difference between the filter correction value and an error integrated value, and a binarization unit for binarizing an output of the error correction circuit, A difference circuit that calculates the difference value between the output of the binarizing unit and the output of the error correction circuit, and an error distribution coefficient that is predetermined for the difference value corresponding to the peripheral pixel of the next target pixel among the difference values. And multiply it by the sum That the one in which the error integrated value and a error integrated value calculating means for outputting to said error correcting circuit.

Further, a binarization decoder for computing a binarization level from the sign bit and the upper bit of the data output from the error correction circuit is provided in place of the binarization means.

Further, the error integrated value calculating means stores an error storage circuit for storing the difference value as an error value corresponding to the target pixel and its peripheral pixel, and a peripheral pixel of the next target pixel from the error storage circuit. The weighting addition circuit reads out the corresponding error value, multiplies it by a predetermined error distribution coefficient, and outputs the sum of the error integrated values to the error correction circuit.

Further, the error integrated value calculating means associates the difference value with the pixel of interest and its peripheral pixels, multiplies a predetermined weighting coefficient and outputs the error weight distribution circuit for each peripheral pixel, and the error weighting circuit. The output of the distribution circuit is made to correspond to each peripheral pixel position of the next pixel of interest, and an integrated addition circuit for outputting the error integrated value, which is a value sequentially integrated and added, to the error correction circuit.

Further, the filter coefficient of the pixel adjacent to the target pixel in the main scanning direction and the sub-scanning direction is a positive value, and the filter coefficient of the pixel adjacent to the target pixel in an oblique direction is a negative value.
The filter coefficient has a sum of 1 including the filter coefficient of the target pixel, and the target pixel of the input multi-tone image and its peripheral pixels are multiplied by each of the filter coefficients to obtain a filter correction value that is the sum. Saddle type edge enhancement filter to calculate, a dither pattern generating circuit, comparing the dither pattern output from the dither pattern generating circuit in synchronization with the input multi-tone image and the filter correction value,
And a binarization comparator for determining the binarization level of the pixel of interest.

Further, the filter coefficient of the pixel adjacent to the target pixel in the main scanning direction and the sub-scanning direction is a positive value, and the filter coefficient of the pixel adjacent to the target pixel in the diagonal direction is a negative value.
The filter coefficient has a sum of 1 including the filter coefficient of the target pixel, and the target pixel of the input multi-tone image and its peripheral pixels are multiplied by each of the filter coefficients to obtain a filter correction value that is the sum. A saddle type edge enhancement filter for calculation, a dither pattern generating circuit, an adder for adding the dither pattern output from the dither pattern generating circuit in synchronization with the input multi-tone image and the filter correction value, and And a binarizing means for binarizing the output of the added value.

The binarizing means compares the output of the adder with a predetermined slice level to determine the binarization level of the pixel of interest.

Further, the binarizing means outputs the presence or absence of a carry bit of the adder as a binarized value.

[0017]

Since the saddle type edge enhancement filter of the present invention is composed of the spatial filter coefficients shown in FIG. 2, the high frequency components in the diagonal direction of the target pixel are attenuated and the high frequency components in the main scanning direction and the sub scanning direction are reduced. Is amplified. As a result, the image of the alternating edge lines in the main scanning direction and the sub-scanning direction, which is often found in the character portion, is emphasized, and the image of the one-pixel alternating portion in the shaded photograph portion is smoothed.

An error correction circuit obtains a difference between a filter correction value passed through this filter and an error integrated value which will be described later, and binarizes it by a predetermined milling level to output a halftone image. . The difference circuit obtains a difference value between the binarized value and the output of the error correction circuit, and of the difference values, the difference value corresponding to the peripheral pixel of the next pixel of interest is multiplied by a predetermined error distribution coefficient. , The sum of the errors is output to the error correction circuit. As a result, the error caused by binarization can be corrected and a halftone image can be output.

At this time, instead of the binarizing means, the sign bit and the high-order bit of the data output from the error correction circuit are binarized by the binarizing decoder. The slice level of the binarized value obtained from the sign bit and the upper bit can be arbitrarily set by the setting of the binarized decoder.

Further, the error integrated value calculating means stores the difference value from the difference circuit in the error storage circuit corresponding to the peripheral pixels of the pixel of interest as shown in FIG. The values indicated by K, L, M, and N are weighted to the difference value with respect to the periphery of the pixel of interest, and the sum is input to the error correction circuit as the above-described error integrated value. As a result, the error caused by binarization can be corrected and a halftone image can be output.

The error integrated value calculating means divides the difference value from the difference circuit into peripheral pixels of the target pixel as shown in FIG. 5 (b) by the error weighting distribution circuit, multiplies the weighted coefficient and multiplies the integrated addition circuit. Then, an error integrated value, which is a value obtained by sequentially integrating and adding it corresponding to each peripheral pixel position of the next target pixel, is input to the error correction circuit. As a result, the error caused by binarization can be corrected and a halftone image can be output.

Further, the above-mentioned filter correction value and the dither pattern output from the dither pattern generating circuit in synchronization with the multi-gradation image input to the saddle type edge enhancement filter are compared by a binarization comparing circuit, and the result is 2 Quantize and output halftone image.

Further, the above-mentioned filter correction value and the dither pattern output from the dither pattern generating circuit in synchronization with the multi-tone image input to the saddle type edge enhancement filter are added by an adder, and the added value is added. The output is binarized by the binarizing means and a halftone image is output.

The binarizing means compares the added value with a predetermined slice level by a binarizing comparator to binarize it, and outputs a halftone image.

Further, the binarizing means can output a halftone image by outputting as a binarized value when the adder performs addition, when there is a carry bit at that time, and when there is no carry bit.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. In the figure, 1 is a multi-gradation image input, 2 is a saddle type edge enhancement filter that attenuates the high frequency components in the diagonal direction of the pixel of interest and amplifies the high frequency components in the main scanning direction and the sub scanning direction, and 3 is the periphery. An error correction circuit for adding integrated errors of pixels, 4 is a predetermined slice level, 5 is a binarizing comparator for comparing the output of the error correction circuit 3 with the slice level 4, 6 is a halftone image output, and 7 is It is a difference circuit that calculates the difference between the output value of the error correction circuit 3 and the binarized value as error data.

Reference numeral 8 denotes an error storage circuit which stores error data corresponding to the position of the pixel of interest, and which reads a set of error data at the peripheral pixel positions of the pixel of interest, and 9 denotes a peripheral error read from the error storage circuit 8. A weighting addition circuit that multiplies the data by a predetermined coefficient and outputs a weighted value that is the sum thereof to the error correction circuit 3, 40 is for shifting 1 line data 1
Line error memories, 41 to 43 are 1 pixel shift registers for shifting 1 pixel data, 44 to 47 are multipliers for multiplying weighting coefficients, and 48 to 50 are adders for calculating summation.

FIG. 2 shows the spatial filter coefficient of 3 × 3 pixels in the saddle emphasis filter according to the embodiment of the present invention.
Since the pixel adjacent to the center pixel of interest in the main scanning direction and the sub scanning direction has a positive coefficient A and the pixel adjacent to the diagonal direction has a negative coefficient B, the coefficient of the entire filter is set to 1 The coefficient is 1 + 4B-4A.

FIG. 3 is a diagram showing an example of a circuit configuration of the filter shown in FIG. In FIG. 3, 11 and 12 are 1-line buffer memories for accumulating 1 line in the main scanning direction and shifting 1-line sequentially from 11 to 12 at the same time when the processing for 1 line is completed, and 17 and 18 are 1 line each. A one-pixel shift register that shifts pixel information for one row stored in the buffer memory 12 for each pixel and generates pixel information of pixels (h) and (i) in FIG. A 1-pixel shift register for generating pixel information of the pixels (e) and (f) in FIG. 2 from the 1-line buffer memory 11, 13 and 14 are pixels (b) and (b) in FIG. 2, respectively.
It is a 1-pixel shift register for generating the pixel information of (c).

Reference numerals 19, 20, 23 denote adders for adding pixel information of pixels adjacent to each other in the main scanning direction and sub-scanning direction of the target pixel, 28 denotes a multiplier for multiplying the addition result by a positive coefficient A, 21, 22,24
Is an adder for adding the pixel information of pixels adjacent to the target pixel in the diagonal direction, 29 is a multiplier for multiplying the addition result by a negative coefficient -B, and 27 is for setting the coefficient of the entire filter to be 1 for the target pixel. A multiplier for multiplying the coefficient of 1 + 4B-4A of 25,26
Is an adder that adds each pixel information multiplied by each coefficient by the above-mentioned multipliers 27, 28, 29.

The operation of this saddle type edge enhancement filter constructed as described above will be described below. In the image signal input by a scanner (not shown), the pixel information of the first line in the main scanning direction is input to the 1-line buffer memory 11 After being stored in the memory 12, the pixel information of the second line is stored in the 1-line buffer memory 11, and this operation is repeated for each line to constantly generate an image signal shifted by 3 lines. Then, the image signals for these three lines are shifted pixel by pixel by the 1-pixel shift registers 13-18.
The input image signal of the pixel information to the 3 × 3 matrix shown in is generated for each pixel, and the signals a to i corresponding to the matrix shown in FIG. 2 are generated.

Here, as shown in FIG. 3, the multiplier 27 multiplies the target pixel e by the coefficient 1 + 4B-4A. Also adder 1
9,20,23 cumulatively add the pixels b, d, f, h adjacent to the pixel of interest e in the main scanning / sub scanning direction, and the multiplier 28 multiplies the addition result by a positive coefficient A. Further, the adders 21, 22, 24 cumulatively add the pixels a, c, g, i that are adjacent to the target pixel e in the diagonal direction, and the multiplier 29 multiplies the addition result by a negative coefficient -B. The adders 25 and 26 add the results obtained by the multipliers 27, 28 and 29 to obtain the image processing result for the target pixel e. Thereafter, the pixel of interest is shifted pixel by pixel to the next pixel and the same calculation is performed.

FIG. 4 shows the spatial frequency / amplitude characteristics of the saddle type edge enhancement filter according to the present invention when A is 1/8 and B is 1/4. FIG. 4 shows the amplitude characteristics of the spatial frequency spatial filter in the main scanning direction and the sub scanning direction obtained by this spatial filter. The pixel of interest and the pixel adjacent to this pixel of interest, that is, the calculation result of the matrix shown in FIG. It shows the amplitude characteristic obtained by. As compared with FIG. 16 showing the amplitude characteristic of the conventional example, it can be seen that the amplitude of the pixels adjacent in the diagonal direction is the minimum.

Returning to FIG. 1, in the multi-tone image input 1, the high frequency components in the diagonal direction of the target pixel are attenuated by the saddle type edge enhancement filter 2, and the high frequency components in the main scanning direction and the sub scanning direction are amplified. . Therefore, there are many main scans in the character part.
The image of alternating edges and lines in the sub-scanning direction is emphasized, and the image of alternating 1-pixel in the shaded photograph portion is smoothed.

Next, the sum of the weighting errors of the peripheral pixels which have already been halftoned is subtracted by the error correction circuit 3, and the data is binarized by the binarization comparator 5 to become the halftone image output 6. Next, in the difference circuit 7, 1 of the binarized data is set to the white level ((6F) hexadecimal display for 6-bit processing), 0
The black level ((00) hexadecimal display for 6-bit processing)
Then, the data before binarization is subtracted from the value to obtain error data.

Next, the error data is stored in 1 of the error storage circuit 8.
One pixel is shifted by the pixel shift register 43, and the current pixel address of interest in the one-line error memory 40 is written. Next, the data of the address of the current pixel-of-interest address + 1 from the 1-line error memory 40 (data written in the line 1 line before)
Is read out and shifted for each pixel by the 1-pixel shift registers 42 and 43. From the above operation of the error storage circuit 8, 1 pixel before the current pixel of interest, 1 pixel before 1 line, 1 line before,
The error data of the peripheral pixel position of one pixel before one line before is output to the weighting addition circuit 9.

In the weighting addition circuit 9, the multipliers 44 to 47 multiply the weighting coefficients K, L, M, N, (K + L + M + N = 1), and the adders 48 to 50 calculate the sum and output it to the error correction circuit 3.

FIG. 5 shows a target pixel X and weighting factors K, L,
It is a figure showing the physical relationship of the peripheral pixel to which M and N correspond.

The above operation is repeated for each pixel.

Next, a second embodiment will be described. FIG. 6 is a block diagram showing the configuration of this embodiment. In this embodiment, the binarization comparator 5 of the first embodiment shown in FIG. 1 is replaced by a binarization decoder 5a, and the same symbols as those in FIG. 1 indicate the same members.

In this embodiment, multi-tone image input is 4 bits (16 bits).
The description will be made assuming that the input is in gradation. As a result, the output of the saddle type edge enhancement filter 2 is also 4 bits. On the other hand, the number of bits output from the weighted addition circuit 9 is a total of 5 bits, that is, a sign bit and 4 bits. Considering the case where carry occurs when the difference between 4 bits and sign + 4 bits is calculated by the error correction circuit 3, a total of 6 bits of sign + 5 bits are output.

The binarization decoder 5a is assumed to be coded by the sign bit and the two upper bits of 3 bits.

FIG. 7 shows the decoding contents of the binary decoder 5a. As a result, an input multi-tone image can be output at a level of 50%. The slice level can be changed by changing the decoding method. FIG. 8 is a diagram showing an example of a gate that realizes the binary decoding 5a.

In the present embodiment, the input multi-gradation image is 4 bits and the decoding is the sign bit + higher 2 bits, but these are examples and other values are also possible.

Next, the third embodiment will be described. FIG. 9 is the third
The structure of an Example is shown. This embodiment differs from the first embodiment in the error weight distribution circuit 60 and the integrated addition circuit 61, and
The same reference numerals denote the same members. The same applies to the subsequent drawings.

Reference numeral 60 denotes an error weight distribution circuit for distributing error data to peripheral pixels according to a predetermined weighting coefficient,
Reference numeral 61 is an integrated adder circuit that performs integrated addition while sequentially shifting the errors distributed by the error weighting distribution circuit in correspondence with peripheral pixel positions, 62 to 65 are multipliers for multiplying weighting coefficients, and 66 to 68 are 1 pixel data. 1-pixel shift register for shifting, 69 to 71 are adders for performing integrated addition, and 72 is a 1-line error memory for shifting 1-line data.

Next, an error weight distribution circuit peculiar to this embodiment
The operation of 60 and the integrated adder circuit 61 will be described.

The error data from the difference circuit 7 is weighted by the weighting coefficient K, by the multipliers 62 to 65 of the error weight distribution circuit 60.
L, M, N, (K + L + M + N = 1) are multiplied to obtain FIG.
The error is distributed to the peripheral pixels as shown in FIG.
Output to 61. The arrangement of the peripheral pixels corresponding to K, L, M and N is the same as in FIG.

In the integrated adder circuit 61, the error data multiplied by the L, M and N coefficients are integrated and added by shifting the data for each pixel by the 1-pixel shift registers 67, 68 and the adders 70, 71, The data of the address of the current pixel of interest of the one-line error memory 72 is written, and then the data of the address of the current pixel of interest address + 1 (the data written one line before) is input to the read adder 69. Meanwhile K
The error data multiplied by the coefficient is the 1-pixel shift register
One pixel is shifted by 66, and added by the adder 69 with the integration error of one line before (1 pixel before data × L, 1 line before data × M, 1 line before 1 pixel after data × N) And output to the error correction circuit 3. The above operation 1
Repeated for each pixel.

Next, a fourth embodiment will be described. FIG. 10 shows the configuration of this embodiment. In this embodiment, the binarization comparator 5 is changed to a binarization decoder 5a in comparison with the third embodiment shown in FIG. The operation of the binarization decoder 5a is the same as that shown in FIGS. 7 and 8 described in the second embodiment.

Next, a fifth embodiment will be described. FIG. 11 shows the configuration of this embodiment. In the figure, reference numeral 73 is a dither pattern generation circuit for generating a dither pattern in synchronization with the output data of the saddle type edge enhancement filter 2, and a binary comparator 5
Compares the output data of filter 2 with the dither pattern
The binarized value is determined and the halftone image 6 is obtained.

Next, a sixth embodiment will be described. FIG. 12 shows the configuration of this embodiment. In the figure, 73 is a dither pattern generator, which is the same as that of the fifth embodiment.

The dither pattern data read from the dither pattern generating circuit 73 and the filter output data in synchronization with the output data of the saddle type edge enhancement filter 2 are added by an adder.
The value is added at 74, and compared with the predetermined slice level 4 by the binarization comparator 5, and binarized to obtain the halftone image output 6.

Next, a seventh embodiment will be described. FIG. 13 shows the configuration of this embodiment. This embodiment is the second embodiment of the sixth embodiment shown in FIG.
Except for the binarizing comparator 5, the adder is changed to an adder with a carry bit.

The binarized value is determined depending on whether or not the adder with carry bit outputs the carry bit, whereby the halftone image output 6 is obtained.

[0057]

As is apparent from the above description, according to the present invention, the spatial frequency characteristic of the saddle type edge enhancement filter attenuates the high frequency component in the diagonal direction of the pixel of interest, and the high frequency in the main scanning direction and the sub scanning direction. In order to amplify the component, the image in the main scanning direction, the sub-scanning direction, which is often found in the character portion, and the line alternating image are emphasized, and the one-pixel alternating image in the shaded photograph portion is smoothed. Therefore, when halftone processing is applied to the saddle-type edge enhancement filter output, moire does not occur in the shaded photo area such as gravure printing, and characters and line drawings are emphasized to prevent unevenness and discontinuity.・
It is intended to improve both the gradation and the resolution of the image quality of the halftone image of the halftone photograph mixed original.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a diagram showing coefficients of a saddle type edge enhancement filter of the present invention.

FIG. 3 is a configuration diagram of a saddle type edge enhancement filter of the present invention.

FIG. 4 is a spatial frequency vs. amplitude characteristic diagram of the saddle type edge enhancement filter of the present invention.

5 is a diagram showing peripheral pixels corresponding to the weighting coefficients shown in FIG.

FIG. 6 is a configuration diagram of a second embodiment.

FIG. 7 is a diagram for explaining decoding of a binary decoder.

FIG. 8 is a diagram showing a configuration example of a binarization decoder.

FIG. 9 is a configuration diagram of a third embodiment.

FIG. 10 is a configuration diagram of a fourth embodiment.

FIG. 11 is a configuration diagram of a fifth embodiment.

FIG. 12 is a configuration diagram of a sixth embodiment.

FIG. 13 is a configuration diagram of a seventh embodiment.

FIG. 14 is a configuration diagram of a conventional image signal processing device using a Laplacian edge enhancement filter.

FIG. 15 is a diagram showing coefficients of a conventional Laplacian edge enhancement filter.

FIG. 16 is a spatial frequency vs. amplitude characteristic diagram of a conventional Laplacian edge enhancement filter.

FIG. 17 is a diagram showing a relationship between a sampling frequency for image reading and a frequency component of a halftone image.

[Explanation of symbols]

 1 multi-gradation image input 2 saddle type edge enhancement filter 3 error correction circuit 4 slice level 5 binarization comparator 5a binarization decoder 6 halftone image output 7 difference circuit 8 error storage circuit 9 weighting addition circuit 60 error weight distribution Circuit 61 Integrated adder circuit 73 Dither pattern generation circuit 74 Adder

Claims (8)

[Claims] 1. A filter coefficient of a pixel of interest has a positive value and a filter coefficient of a pixel adjacent to the pixel of interest in a main scanning direction and a sub-scanning direction has a negative value. Saddle-type edge which has a filter coefficient such that the sum of the coefficients including 1 becomes 1 and the pixel of interest of the input multi-tone image and its peripheral pixels are multiplied by each of the filter coefficients, and a filter correction value which is the sum thereof is calculated. An emphasis filter, an error correction circuit that calculates the difference between the filter correction value and the error integrated value, and the output of this error correction circuit is binarized 2
Of the difference values, a value conversion means, a difference circuit for calculating a difference value between the output of the binarization means and the output of the error correction circuit,
An error integrated value calculating means for multiplying a difference value corresponding to a peripheral pixel of the next target pixel by a predetermined error distribution coefficient and outputting the error integrated value which is the sum thereof to the error correction circuit. Image signal processing device. 2. A binarization decoder for computing a binarization level from a sign bit and upper bits of data output from the error correction circuit is provided in place of the binarization means. 1. The image signal processing device according to 1. 3. The error integrated value calculation means stores an error storage circuit for storing the difference value as an error value corresponding to the target pixel and its peripheral pixel, and a peripheral pixel of the next target pixel from the error storage circuit. 3. A weighted addition circuit for reading the corresponding error value, multiplying it by a predetermined error distribution coefficient, and outputting the sum of the error integrated values to the error correction circuit. Image signal processing device. 4. An error weight distribution circuit, in which the error integrated value calculation means associates the difference value with a pixel of interest and its peripheral pixels, multiplies by a predetermined weighting coefficient, and outputs for each peripheral pixel, and this error weighting. 2. An integrated addition circuit for outputting the error integrated value, which is a value obtained by sequentially integrating and adding the output of the distribution circuit to each peripheral pixel position of the next target pixel, to the error correction circuit. Alternatively, the image signal processing device according to item 2. 5. The filter coefficient of a pixel of interest has a positive value, the filter coefficient of a pixel adjacent to the pixel of interest in the main scanning and sub-scanning directions has a negative value, and the filter coefficient of a pixel adjacent to the pixel of interest in an oblique direction has a negative value. Saddle-type edge which has a filter coefficient such that the sum of the coefficients including 1 becomes 1 and the pixel of interest of the input multi-tone image and its peripheral pixels are multiplied by each of the filter coefficients, and a filter correction value which is the sum thereof is calculated. The enhancement filter, the dither pattern generation circuit, the dither pattern output from the dither pattern generation circuit in synchronization with the input multi-tone image and the filter correction value are compared to determine the binarization level of the pixel of interest. An image signal processing device, comprising: 6. The filter coefficient of a pixel of interest has a positive value and the filter coefficient of a pixel adjacent to the pixel of interest in the main scanning and sub-scanning directions has a negative value. Saddle-type edge which has a filter coefficient such that the sum of the coefficients including 1 becomes 1 and the pixel of interest of the input multi-tone image and its peripheral pixels are multiplied by each of the filter coefficients, and a filter correction value which is the sum thereof is calculated. An enhancement filter, a dither pattern generation circuit, an adder for adding the dither pattern output from the dither pattern generation circuit in synchronization with the input multi-tone image and the filter correction value, and an output of the addition value. An image signal processing device, comprising: a binarizing unit for binarizing. 7. The binarization unit compares the output of the adder with a predetermined slice level to determine the binarization level of the pixel of interest.
The image signal processing device described. 8. The image signal processing apparatus according to claim 6, wherein the binarizing means outputs the presence or absence of a carry bit of the adder as a binarized value.