JPH03136574A - Picture processing unit - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and to reduce the cost of a picture processing unit by correcting a 2nd picture signal to realize the error spread method in response to a 1st picture signal from a picture signal correction means and a 1st binary data from a data compression means and discriminating the level. CONSTITUTION:An error spread circuit 26 corrects a 2nd gradation data S2 so as to decrease a deviation between a gradation level represented by a 2nd gradation data S2 and a threshold level Sh for binarization with respect to a picture element near the photoelectric conversion section with a larger deviation and applies data processing discriminating the level as the deviation is larger with respect to a 1st binary data PD corresponding to picture elements near picture signals corresponding to outputs S2, PS from a MTF correction means and a 2nd gradation data S2 and a 1st binary data D1 of the 1st gradation data S1 is given to a compression processing circuit 27.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is suitably implemented in an image reading device used in a facsimile machine, etc., and performs image processing to express read image information as black and white binary pixels. Regarding equipment.

Conventional technology facsimile machines and optical character readers (abbreviated as OCR)
A reading device that reads the surface of a document in predetermined pixel units and outputs it as a signal having a binary level corresponding to the document image is installed in the device. The reading device scans the reflected light from the surface of the document using a reading sensor realized by, for example, a charge-coupled device (approximately #CCD), and sequentially generates an image signal representing the density of each pixel for each wire.

An aspirational prior art is shown in FIG. The image signal S, which is sequentially output from the CCD or the like for each pixel and subjected to analog/digital conversion, is given to the line buffer 1, and the image signal stored in the line buffer 1 is
Another line buffer 2 is provided. The line buffers 1 and 2 each have a storage capacity corresponding to a scanning line on the document surface. Based on the image signal and image signal S stored in the two line buffers 1 and 2, the binarization processing circuit 3 outputs binary data D for each pixel. The binary data D is stored in the line buffer 4, and is output as final binary data by the binary data correction circuit 5 based on the binary data D and the image signal stored in the line buffer 4.

Problems to be Solved by the Invention Conventionally, when binarizing an intermediate gradation image, two of, for example, four peripheral pixels adjacent to the pixel of interest, which is a specific pixel of interest, in the vertical and horizontal directions have been used. After adding the error E obtained from the value conversion situation to the image signal S of the pixel of interest,
An error diffusion method is used to perform the value conversion process.

FIG. 8 is a block diagram showing a circuit configuration for implementing the error diffusion method. The image signal S for each pixel is sent to the adding circuit 6
given to. The adder circuit 6 also receives an error signal E, which will be described later.
A sum signal 5E=S+F of the image signal S and the error signal E is provided to the comparator circuit 7. The comparison circuit 7 converts the sum signal SR into a threshold value S from the threshold value setting circuit 8.
Level discrimination is performed using h, and binary data D of the image signal S is output.

The binary data D is given to the error calculation circuit 9.

Further, the image signal S is given to the error calculation circuit 9, and the error e at the pixel corresponding to the image signal S is calculated. That is, when the binary data D from the comparator circuit 7 is "1.", the error calculation circuit 9 assumes the error is e-8, and the binary data D
When =rOJ, the error is set as e=SR (R is a constant).

The error e from the error calculation circuit 9 is delayed by one pixel by the delay circuit 10 and given to the line buffer 11, and the error e0 delayed by one pixel is sent to the multiplier circuit 1.
given to 2.

The line buffer 11 has a storage capacity that is two pixels smaller than the number of pixels in one scanning line. Therefore, when assuming the error θ corresponding to each pixel as shown in FIG. 5(3), the delay circuit 10 outputs an error e.

is given to the line buffer 11, and the line buffer 11
The error eA is output from. Output es from line buffer 11 and error es via delay circuits 13 and 14
, ec are respectively provided to the multiplication circuit 12.

The multiplication circuit 12 calculates the error e^+ e s + e e +
e Weighting is done by coefficient kl, and 2. 3. The value obtained by multiplying 4 by 4 is applied to the adder circuit 15, and the adder circuit 15 outputs these added values as an error signal E. That is, E=kl ・eA + 2 ・es + 3 ・ec
+4 ・e.

It is.

The circuit configuration shown in FIG. 8 for implementing the error diffusion method is usually realized by being added to the circuit configuration shown in FIG. 7. Therefore, in such a conventional image processing device, the input image signal S
In addition to two line buffers 1 and 2 for temporarily storing the data and one line buffer 4 for storing the binarized data D, the error e shown in FIG. 8 is stored. It is necessary to provide one line buffer 11 for this purpose, which increases the cost of the image processing apparatus.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image processing apparatus that can perform binarization processing of an image signal using an error diffusion method without providing a new storage means such as a line buffer memory.

Means for Solving the Problems The present invention includes an image signal generating means that sequentially generates a first image signal representing the density of each pixel for each pixel, and improving contrast in response to the output of the image signal generating means. an image signal correction means for deriving a second image signal corrected for the purpose of the image signal and a first image signal corresponding to a pixel in the vicinity of the pixel corresponding to the second image signal; each output from the image signal correction means; In response to the input first binary data, the second image is adjusted such that the larger the deviation between the level of the second image signal and the predetermined discrimination level, the smaller the deviation of pixels near the pixel with the larger deviation. error diffusion means for correcting the signal and level discrimination to obtain first binary data of the first image signal; responsive to the output from the error diffusion means, compressing the first binary data; data compression means for obtaining second binary data of one image signal and providing first binary data corresponding to pixels in the vicinity of the pixel corresponding to the second binary data to the error diffusion means; This is an image processing device characterized by the following.

According to the present invention, the first image signal representing the density of each pixel generated by the image signal generating means is given to the image signal correcting means, and the second image signal is corrected to improve the contrast. Derived as an image signal. Further, the image signal correction means derives, from the inputted first image signal, a first image signal corresponding to a pixel in the vicinity of the pixel corresponding to the second image signal to be derived.

These second image signals and first image signals corresponding to pixels in the vicinity of the pixels corresponding to the second image signals are given to the error diffusion means. Further, the error diffusion means receives a first image signal corresponding to a first image signal inputted earlier than the inputted first image signal from a data compression means that performs compression processing on the first binary data after level discrimination. binary data is given.

The larger the deviation between the level of the input second image signal and the predetermined discrimination level, the larger the error diffusion means, the larger the deviation is, the larger the deviation is, the larger the deviation is, the larger the deviation is, the larger the deviation is, the error diffusion means is input to the second image signal. The second image signal is corrected so that the deviation of the second image signal inputted from the image signal correcting means is reduced after the error is detected, the level is discriminated, and the first image signal of the first image signal according to such an error diffusion method is binary data is created and given to the data compression means.

The data compression means performs compression processing from the first binary data input by five people to create second binary data of the first image signal, and also corresponds to this second binary data as described above. First binary data corresponding to a pixel in the vicinity of the pixel is given to the error diffusion means.

In this way, the error diffusion means receives pixels corresponding to the second image signal input from the image signal correction means earlier than the second image signal whose level is to be discriminated by performing correction according to the error diffusion method. Since the first image signal and the first binary data are provided from the image signal correction means and the data compression means, respectively, there is no need to provide a storage means such as a line buffer memory when performing the error diffusion method.

Therefore, the circuit configuration is simplified and costs are reduced.

Embodiment No. 1171 is an image processing device 2 which is an embodiment of the present invention.
FIG. 2 is a block diagram showing a simplified basic configuration of 0. The original image of the original 21 is sequentially scanned and read by a reading means 22 including a CCD (charge coupled device) or the like. The analog image signal output by the reading means 22 is analog/digital.
(abbreviated as J) conversion circuit 23, where it is converted into a digital image signal. This digital image signal corresponds to, for example, 8-bit data, and each read pixel is 0.
~255 of 256 (=2”) t'l tone image data S1
The density is expressed by.

The gradation data S1 output from the A/D conversion circuit 23 is given to the image processing circuit 24. The image processing circuit 24 is an MT
It is configured to include an F correction means 25, an error diffusion circuit 26, and a compression processing circuit 27.

The MTF correction means 25 applies MTF (Modulation Tran) to the first gradation data S1, which is the first image signal, to improve the contrast thereof.
sfer Function) The corrected second image signal S2 is derived and given to the error diffusion circuit 26, and
The first gradation data S1 26 corresponding to the pixels near the pixel corresponding to the second gradation data S2 is given.

In the error diffusion circuit 26, each output S2. PS and the second gradation data from the first binary data PD corresponding to the pixel near the pixel corresponding to the second gradation data S2.
The second gradation data S2 is set such that the larger the deviation between the gradation level represented by the gradation data S2 and the threshold level Sb for performing binarization, the smaller the deviation of the pixels near the pixel with the larger deviation. After correcting, data processing according to the error diffusion method to be described later is performed to perform level discrimination, and the first binary data D1 of the first gradation data S1 is provided to the compression processing circuit 27.

The compression processing circuit 27 converts a plurality of binary data D1 derived corresponding to each pixel of two input scanning lines into a plurality of binary data D2 corresponding to one scanning line and outputs the converted binary data D2. While performing compression processing, this second binary data D
First binary data PD corresponding to a pixel near the pixel corresponding to pixel 2 is provided to the error diffusion circuit 26.

2 is a block diagram showing the basic configuration of the MTF correction means 25, FIG. 3 is a block diagram showing the basic configuration of the error diffusion circuit 26, and FIG. 4 is a block diagram showing the basic configuration of the compression processing circuit 27. FIG. FIG. 5 is a diagram showing the correspondence between the first gradation data S1 of each pixel and the first binary data D1 of each pixel, and each error e obtained by error calculation described later.

Referring to FIG. 2, the first gradation data S1, which is the first image signal after A/D conversion, is given to the line buffer memory 28 of the MTF correction means 25, and each pixel corresponding to one scanning line is The gradation data S1 for each is once stored, and
M through each delay circuit 30 and 31 that delays one pixel.
The signal is applied to the TF correction circuit 38. The first line buffer memory 28 delays the first line by one scanning line.
The gradation data S1 is given to the next line buffer memory 29 and temporarily stored, and the delay circuits 32 and 3
3.34 and is applied to the MTF correction circuit 38. The first gradation data S1, which has been further delayed by one scanning line by the line buffer memory 29, is sent to the delay circuit 35.
, 36, and 37, and is derived as the first gradation data Sc.

Each of the delay circuits 32 to 37 outputs the input signal with a delay equivalent to one pixel.
33, the first gradation data S shown in FIG. 5(1)
, S* are provided to the MTF correction circuit 38. Similarly, the first gradation data S1 is derived from the delay circuit 35, and the first Il! data is derived from the delay circuit 36. F-tone data S6 is provided to the MTF correction circuit 38. Further, from the delay circuit 31, the first
The gradation data Sr is provided to the MTF correction circuit 38.

The MTF correction circuit 38 performs MTF correction to improve the contrast of the pixel corresponding to the first gradation data S based on the input first gradation data S, Ss, So, SF, and SN. , outputs second gradation data S2, which is a second image signal.

That is, in the MTF correction circuit 38, with respect to the target pixel to which MTF correction is applied, first gradation data S s corresponding to each pixel adjacent to the target pixel in the vertical direction and horizontal direction are obtained.
, S o , S r, and S @, the average gradation data S□ according to the following formula is calculated (see FIG. 5 (1)).

,,,, = S, + S°+ S r + S N
,, -<t>Next, second gradation data S2 is calculated according to the following equation for constants A and B having a relationship of A-B=1.

s2= Axs BXSp+tA*
”, (2) In this way, the MTF correction circuit 3
The second gradation data S2 calculated and outputted in step 8 has improved contrast compared to the first gradation data S1 originally derived from the corresponding pixel.

Referring to FIG. 3, first gradation data sA, s, , sc, s derived from the MTF correction means 25.

are the error calculation circuits 40, 41゜42 of the error diffusion circuit 26.
．． 43 respectively. Moreover, the MTF correction means 2
The second gradation data S2 from 5 is applied to the adder circuit 44. The error calculation circuits 40 to 43 receive first gradation data SA to S0 from the compression processing circuit 27 shown in FIG. 4, which will be described later.
The first binary data DA, 0 of each pixel respectively corresponding to
%, DC, D.

is given.

Each of the error calculation circuits 40 to 43 receives input first gradation data and first binary data SA, DA;

Dll; S, , Dc; Error e At required to realize the error expansion 111E method described later from So and Do
e lI, e e.

Multiplying circuits 46, 47, 48.4 each calculate eo.
Give each to 9. 1・e A k 2・es k3・ec,
4·eo is added in the adder circuit 45 and added to the adder circuit 4.
given to 4. The addition circuit 44 adds the addition result S from the addition circuit 45 to the second gradation data S2.
E is applied to the comparator circuit 50. The comparison circuit 50 performs level discrimination on the output SE from the addition circuit 44 using a threshold value Sh preset in the three threshold value setting circuits as a discrimination level, and selects the first two pixels corresponding to the second gradation data S2. Output value data D1.

Referring to No. 41"J, the first 2fti data D1 derived from the error diffusion circuit 26 is first given to the line buffer memory 51 via the changeover switch SW3, and the first 2fti data D1 corresponding to one scanning line is The binary data D1 of is stored once.

The line buffer memory 51 has a storage capacity that is two pixels smaller than the number of pixels corresponding to one scanning line. From the line buffer memory 51, the first 2
Value data D1 is applied to logical sum (OR) gate G1 via delay circuits 53, 54, and 55. When the first binary data D1 corresponding to one scanning line is stored in the line buffer memory 51, the changeover switch SW3 is then switched so that the binary data D1 is given to the delay circuit 52.

The output from delay circuit 52 is given to OR gate G1.

Each of the delay circuits 52, 53, 54, 55 outputs data delayed by one pixel, so that the first binary data D1 given from the error diffusion circuit 26 to the compression processing circuit 27 is When the binary data D is shown in FIG. 2, the output from the delay circuit 52 is binary data D0, and the output from the delay circuit 55 is binary data DC.

Furthermore, from the delay circuits 53 and 54, binary data DA, D
.

are derived respectively. The binary data Dc and Do from the delay circuits 55 and 52 are connected to these two data via the OR gate G1.
It is output as second binary data D2 of the pixel corresponding to the value data Dc and DO. Further, the first binary data DA-DO outputted from the delay circuits 52 to 55 are provided to the error calculation circuits 40 to 43 of the error diffusion circuit 26 shown in FIG. 3, respectively.

Next, the error diffusion method will be explained below with reference to FIGS. 2 to 5. The first pixel corresponding to the pixel of interest to be subjected to binarization processing.
The gradation data S, the first binary data D, and the error e, the first gradation data corresponding to the pixels in the vicinity of this pixel of interest, and the first
Assume binary data and errors as shown in Figure 5.

At this time, the second gradation data S2 after MTF correction of the pixel of interest
SE, which is obtained by adding error data E of pixels near the pixel of interest, is subjected to binary judgment using a preset threshold level S1·1 to obtain first binary data D1. That is, SE = S
+ E = S+k 1 ・2- to eA+ 3- ec to es+
+4 ・e.

(3) Here, the error e i (i=A, B, C, D) is calculated in the error calculation circuits 40 to 43 according to the following equation.

Here, the first binary data Di (i=A, B.

C, D) are set in the comparison circuit 50 as shown in the following equation.

Here, the first gradation data Si is for each pixel 1 (i=A,
B, C, D), for example r
In the case of bit data, it takes a value from 0 to 2r-1.

Further, the constant R is set to be a value obtained by adding 1 to the maximum value of the first gradation data Si, that is, 2'.

Furthermore, in the multiplication circuits 46 to 4, the weighting of each pixel by which the error eA'%eD is multiplied is a coefficient, which is set according to the mutual relationship of the following equation.

0 < kl, k2. k3. k4 < 1゜kl
+ k2 + k3 + k4 = 1...
(6) For example, kl-, 2=, 3=, 4=', and in other cases. Each value of 1 to 4 is appropriately set so as to obtain a suitable result in the image binarization process.

For example, assuming that the number of bits of IIJ tone data is r = 8, the first tone data S1 takes values from 0 to 255, and the larger the value, the whiter the shade of the corresponding pixel, and the smaller the value, the blacker. represents.

To simplify error calculation, if the minimum value of the first gradation data S1 is set to 0, which corresponds to a black pixel, and the maximum value is set to 256, which corresponds to a white pixel, this first gradation data S1 is converted into a binary value. Converting the data D1 into 2' values means that the first gradation data S
This corresponds to making a determination by regarding a value of 1 as O (black pixel) or 256 (white pixel). Therefore, an error occurs in such a determination.

In other words, when the gradation data is S-200 in decimal notation, determining it as a white pixel (gradation data 5 = 256) means that the difference of 56 is determined to be on the white pixel side, and the gradation data 5 = If the pixel is determined to be a black pixel (gradation data 520) when the value is 100, it means that the pixel is determined to be a black pixel by the difference of 100.

Therefore, in the error diffusion method, the error occurring in the binarization judgment described above is taken into account in the binarization judgment of the next pixel, and when the next pixel of interest is binarized, the pixels near this pixel of interest are Binarization determination is performed by incorporating the error generated in the above with predetermined weighting (kl, 2., 3°k4).

When the number of bits of gradation data r=8, the constant R=
2'=256. 5i=0101010 by the threshold level Sh set in advance in the threshold setting circuit 39
1. When zl=85, if Di=rQ'', that is, it is determined to be a white pixel, the error ei=Si-R=85-256=-171''=1010101, z+ is set.

On the other hand, when 5i=010101011z,=85, the error ei=Si=85=001010101 is set for the J% group determined to be a black pixel, that is, Di=rl.

Here, in the error ei expressed in binary notation, the most significant bit (M S B ) represents a positive value in decimal notation as "0" and a negative value as "1".

The error calculation circuits 40 to 43 that realize error calculation according to the fourth equation can be realized with a simple circuit configuration shown in FIG. 6. Here, Si (r-1), S
i (r-2), =-, Si (0) indicates the signal for each bit of the first gradation data Si from the most significant bit (MSB) side to the least significant bit (LSB), and the error ei (r), ei (r-1), ei (r-2>
, ..., ei(0) indicates the error ei for each bit from the most significant bit to the least significant bit.

The first binary data Di is derived as an error signal ei (r>) via an inversion buffer N1, and the first gradation data Si
(r-1) ~Si (0) are each buffer yB
The error signal ei (
r-1) to ei(0).

As described above, according to this embodiment, the error calculation circuits 40 to 43 in the error diffusion circuit 26 can be realized with a relatively simple circuit configuration as shown in FIG.

In addition, the first gradation data 5A-811 and the first binary data DA to D are required when calculating the errors e8 to eo.
0 is from the MTF correction means 25 and the compression processing circuit 27 provided in the image processing circuit 20 in order to create the second binary data D2 which is the final binary output from the input first image data S1. Therefore, as in the conventional error calculation shown in No. 80, the error ei (i=A, B,
C, D) need not be stored in the line buffer memory 11, and therefore the error storage line buffer memory 1
1 can be omitted, and the cost of the image processing device 20 can be reduced.

In the above embodiment, the first gradation data sA□-, s and the first binary data DA to D are derived and used from the MTF correction means 25 and the compression processing circuit 27. In addition, the image processing device 20 is equipped with
For example, first binary data DA-Do derived from a buffer memory such as a so-called smearing processing circuit that removes and suppresses unevenness on a pixel-by-pixel basis may be used.

In addition, in this embodiment, the error E calculated in the error diffusion method is calculated as an addition value with the weighting of the error in each pixel of 4-) near the pixel of interest, but the target area of this error calculation is The error E may be calculated by expanding the above method.

Effects of the Invention According to the present invention, in an image processing apparatus including an image signal correction means and a data compression means, the error diffusion means converts the first image signal from the image signal correction means and the first binary value from the data compression means. In response to the data, the level discrimination is performed after correcting the second image signal to realize the error diffusion method, which reduces the number of components such as storage means and delay means, and simplifies the circuit configuration. , reducing the cost of image processing devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a simplified basic configuration of an image processing device 20 which is an embodiment of the present invention, and FIG. 2 is a block diagram showing an MTF.
FIG. 3 is a block diagram showing the configuration of the error diffusion circuit 26, FIG. 4 is a block diagram showing the configuration of the compression processing circuit 27, and FIG. 5 shows the gradation data of each pixel. , a diagram showing the correspondence between binary data and errors,
FIG. 6 is a block diagram showing an embodiment of the error calculation circuits 40 to 43, FIG. 7 is a block diagram showing the configuration of conventional binarization processing, and FIG. 8 is a conventional typical example for realizing the error diffusion method. FIG. 2 is a block diagram showing a circuit configuration.

Claims (1)

[Scope of Claims] Image signal generation means for sequentially generating a first image signal representing the density of each pixel for each pixel; and correction for improving contrast in response to the output of the image signal generation means. an image signal correcting means for deriving a second image signal obtained by inputting a second image signal and a first image signal corresponding to a pixel in the vicinity of the pixel corresponding to the second image signal; In response to the binary data, the second image signal is corrected so that the larger the deviation between the level of the second image signal and the predetermined discrimination level, the smaller the deviation of the pixels in the vicinity of the pixel with the larger deviation. error diffusion means for level discriminating and obtaining first binary data of the first image signal; and responsive to the output from the error diffusion means, compressing the first binary data and and data compression means for obtaining two binary data and providing first binary data corresponding to a pixel in the vicinity of the pixel corresponding to the second binary data to the error diffusion means. Image processing device.