JPS624344A - Master-slice-type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the extent of integrating of a device, by providing, in wiring regions provided between basic cells, diffused regions connected to the well potential of the basic cell and to the substrate potential source. CONSTITUTION:A plurality of basic cells 200A each consisting of two MOS transistors are provided on a semiconductor substrate so as to form cell arrays. Wiring regions 7 and 17 for providing logic circuits in future processes are provided between the cells. An N<+> type diffused region 8 and a P<+> type diffused region 18 are provided in these wiring regions 7 and 17, respectively, and they are connected to the well potential of the basic cell and the substrate potential source. It is thereby enabled to decrease the width of the basic cell 200A to the distance defined between wires 16 with polycide structure and thus to decrease the size of the basic cell. Accordingly, the extent of integration of the device can be improved.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a master slice type semiconductor integrated circuit.

[Conventional technology]

As shown in FIG. 3, the master slice type semiconductor device includes a cell row 201 consisting of a plurality of basic cells 200B, and an I
It mainly consists of a block row 205 consisting of 10 blocks 204. The structure of the basic cell will be explained below.

4 is a detailed plan view of the basic cell 200B shown in FIG. 3, and FIG. 5 is a BB' sectional view of the basic cell shown in FIG. 4.

4 and 5, 101 is a P channel MO
8) Transistor (hereinafter referred to as PMU8T) area, 111
is an N-channel MO8) transistor (hereinafter referred to as NN08T) region. The PMOS T region is the gate electrode 1
There are two gate electrodes 02 and two gate electrodes 112 in the NMOS T region.
We have prepared two-person NAND gate, two-person NO
It is possible to configure an R gate or an inverter circuit.

The AI wirings 104 and 114 are both power supply lines, a high potential or low potential (DD) line, and a ground (GND) line, respectively. Reference numeral 106 denotes an N+ diffusion region, which is connected to the AI wiring 104 through a contact 5, and applies a vDD potential into the N well. Reference numeral 116 denotes a P+ diffusion region, to which a GND potential is similarly applied to the semiconductor substrate (hereinafter simply referred to as the substrate).These N+ diffusion regions 106 and P+ diffusion regions 116
This stabilizes the potential in the N-well and the substrate, and has contributed to improving the backgassing characteristics and latch-up characteristics of transistors.

[Problem that the invention seeks to solve]

The nine conventional basic cells described above have a structure in which an N well and a diffusion region for supplying a substrate potential are arranged around the source/drain regions 103 and 113 of the transistor.

Therefore, the source/drain regions 103 and 113 of the transistor and the diffusion regions 106 and 116 that supply the potentials of the N well and substrate become P and N opposite diffusion regions.

When creating these conflicting diffusion regions, of course the side etching amount will be large during wet etching due to the mask material, so it is necessary to ensure a sufficient distance (for example, several μm) between the conflicting diffusion regions. , the disadvantage is that the size of the basic cell becomes large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a master slice type semiconductor integrated circuit which eliminates the above-mentioned drawbacks, has a smaller basic cell size, and has an improved degree of integration.

[Means for solving problems]

The master slice type semiconductor integrated circuit of the present invention arranges cell rows consisting of a plurality of basic cells on a semiconductor substrate, and connects the basic cells as desired using wiring regions provided between the cell rows. In the master slice type semiconductor integrated circuit constituting the logic circuit, a diffusion region connected to the Fermi potential source and substrate potential source rcM1 of the basic cell is provided in the wiring region.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

The gate electrode has a polycide structure consisting of two layers of polysilicon 20B for resistivity and silicide 20A of high melting point metal, and the polysilicon is of P type.

3 is the source/drain region of PMO8T, 4 is the AI wiring connected to the VDD potential source, %6 is the wiring with polycide structure, the polysilicon is PIJ, and the gate electrode 2 of the transistor.
I am using the same type as . A contact 5 connects the An wiring and the wiring 6 having a polycide structure. Further, 7 is a polycide structured wiring connected to the AI wiring 4, and the polysilicon is Nf! It is ll. Reference numeral 8 denotes an N+ type diffusion region, which is connected to the wiring 7 having a polycide structure via a direct contact 9.

In PMO8T, the DD potential is applied to the N+ type diffusion region 8 through the An wiring 4t- and through the wiring 6 having a polycide structure.

In the NMO8T region 11, 12 is a gate electrode having a polycide structure, and the polysilicon 20B in this case is of N type. 13 is a source/drain region of the NMOS T. 14 is an AI wiring connected to the GND potential source, 16
The wiring has a polycide structure and uses a polysilicon ll1N type, which is the same type as the gate electrode 12 of the transistor. 1
5 is a contact connecting the AJ wiring 14 and the polycide structure wiring 16t. Further, reference numeral 17 denotes a wiring having a polycide structure connected to the AJ wiring 14, and the polysilicon is of P type.

18 is a P+ type diffusion region, and wiring 17 has a polycide structure.
is connected to via a direct contact 19t.

For NMO8'l''Kjr, GND potential uAl wiring 1
P+ through the 4 pipes and further through the polycide structure wiring 16
applied to the mold diffusion region 18.

The basic cell 200A constituted of two MOS transistors in this way is connected to the cell row 20 in the same way as shown in FIG.
1. A wiring region 202 is provided between the cell rows 201 for forming a logic circuit in the proofing process.

N+ type diffusion region 8 and P+ type diffusion region 1 shown in FIG.
8Fi is formed within this wiring region 202, so the width of the basic cell 200A is equal to the distance XA between the wirings 16 of the polycide structure shown in FIG. Therefore, compared to the conventional basic cell 200BC) @XB shown in FIG.
It can be made smaller by the width of 6.

In the above embodiments, the gate electrodes and interconnections have a polycide structure, but of course they may be made of polysilicon or other metals.

〔Effect of the invention〕

As described in detail above, the present invention has the advantage of being able to be integrated by forming it in the wiring region over the diffusion region for fixing the potential in the substrate and the well, thereby reducing the size of the basic cell.

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a plan view of an embodiment of the present invention.
3 is a layout diagram of a basic cell of a conventional master slice type semiconductor integrated circuit, FIG. 4 is a detailed plan view of the basic cell shown in FIG. 3, and FIG. 5 is a cross-sectional view of the basic cell shown in FIG. It is a BB' cross-sectional view. 1+10i...PMO8T area, 2,102.
......Gate electrode, 3,103...
...Source/drain region, 4,104...
AJ wiring, 5... Contact, 6.7...
...Wiring, 8,106...N+ type diffusion region,
9, 19...Direct contact layer, 10.
...isolation oxide film, 11,111...NM
UST region, 12, 112... gate electrode, 13, 113... source/drain region,
14,114・mountain・・AJ wiring, 16.17・・・・
・Wiring, 18, 116...P+ type diffusion region, 2
00A, 200B・mountain・・basic cell, 201・・・・
・Cell row, 202...Wiring area, 203...
... Cell area, 204 ... I10 block,
205... Pp tsuku row. %Example Yamotose L Bud l Figure j72 Figure Kaya 5I! I Kaya 31! I grass 4 sides

Claims (1)

[Claims] A master slice type semiconductor that configures a desired logic circuit by arranging cell rows consisting of a plurality of basic cells on a semiconductor substrate and directly reading the basic cells using wiring areas provided between the cell rows. A master slice type semiconductor integrated circuit, characterized in that a diffusion region connected to a well potential source and a substrate potential source of the basic cell is provided in the wiring region.