JPS6240736B2 - - Google Patents

Info

Publication number
JPS6240736B2
JPS6240736B2 JP56190516A JP19051681A JPS6240736B2 JP S6240736 B2 JPS6240736 B2 JP S6240736B2 JP 56190516 A JP56190516 A JP 56190516A JP 19051681 A JP19051681 A JP 19051681A JP S6240736 B2 JPS6240736 B2 JP S6240736B2
Authority
JP
Japan
Prior art keywords
register
stack
circuit
contents
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56190516A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5894038A (ja
Inventor
Koichi Tsukizoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP19051681A priority Critical patent/JPS5894038A/ja
Publication of JPS5894038A publication Critical patent/JPS5894038A/ja
Publication of JPS6240736B2 publication Critical patent/JPS6240736B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
JP19051681A 1981-11-30 1981-11-30 電子計算機 Granted JPS5894038A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19051681A JPS5894038A (ja) 1981-11-30 1981-11-30 電子計算機

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19051681A JPS5894038A (ja) 1981-11-30 1981-11-30 電子計算機

Publications (2)

Publication Number Publication Date
JPS5894038A JPS5894038A (ja) 1983-06-04
JPS6240736B2 true JPS6240736B2 (it) 1987-08-29

Family

ID=16259385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19051681A Granted JPS5894038A (ja) 1981-11-30 1981-11-30 電子計算機

Country Status (1)

Country Link
JP (1) JPS5894038A (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59146387A (ja) * 1983-02-10 1984-08-22 Fujitsu Ltd マルチプロセスにおけるスタツク制御方式
JPH0740234B2 (ja) * 1985-09-04 1995-05-01 日本電気株式会社 トレース回路
JPS6380332A (ja) * 1986-09-24 1988-04-11 Mitsubishi Electric Corp マイクロプロセツサ
US4853849A (en) * 1986-12-17 1989-08-01 Intel Corporation Multi-tasking register set mapping system which changes a register set pointer block bit during access instruction

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5398753A (en) * 1977-02-09 1978-08-29 Nippon Telegr & Teleph Corp <Ntt> Interrupt processing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5398753A (en) * 1977-02-09 1978-08-29 Nippon Telegr & Teleph Corp <Ntt> Interrupt processing system

Also Published As

Publication number Publication date
JPS5894038A (ja) 1983-06-04

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