JPS6240364A - Formation of high melting point metal silicide - Google Patents

Formation of high melting point metal silicide

Info

Publication number
JPS6240364A
JPS6240364A JP18011185A JP18011185A JPS6240364A JP S6240364 A JPS6240364 A JP S6240364A JP 18011185 A JP18011185 A JP 18011185A JP 18011185 A JP18011185 A JP 18011185A JP S6240364 A JPS6240364 A JP S6240364A
Authority
JP
Japan
Prior art keywords
melting point
point metal
high melting
vapor deposition
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18011185A
Other languages
Japanese (ja)
Inventor
Akio Tanigawa
明男 谷川
Eiji Nagasawa
長澤 英二
Hidekazu Okabayashi
岡林 秀和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18011185A priority Critical patent/JPS6240364A/en
Publication of JPS6240364A publication Critical patent/JPS6240364A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form high m.p. metal silicide having uniform and low resistance and excellent self-matching characteristic by executing vapor deposition and ionization under specific conditions in the stage of heating a substrate having a silicon layer under specific conditions so that a high-purity metal is deposited by evaporation thereon. CONSTITUTION:The substrate having the silicon layer on at least the surface is heated to the temp. at which tetragonal MoSi2 and WSi2 are respectively formed with Mo and W, the temp. at which hexagonal VSi2, NbSi2 and TaSi2 are respectively formed with V, Nb and Ta and the temp. at which rhombic TiSi2, ZrSi2 and HfSi2 are respectively formed with Ti, Zr and Hf, then these high m.p. metals are deposited by evaporation on the substrate in the stage of depositing the high m.p. metallic films on the substrate. In this stage, >=10% of the vapor deposition particles are ionized for the formation of the first several tens Angstrom film or below and the ionized vapor deposition particles are accelerated to >=0.1keV to execute the vapor deposition. The vapor deposition is then continued in the non-ionizing stage until the desired film thickness is attained to generated the silicidation reaction simultaneously with the vapor deposition.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体装置の配線や電極として周込る高融点金
属シリサイドの形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming a high melting point metal silicide to be used as wiring or electrodes in a semiconductor device.

(従来の技術) 近年、シリコン集積回路を代表とする半導体装置くお−
ては素子寸法の微細化による高密度化及び高速化が計ら
れている。かかる微細化に伴って従来よルミ極や配線と
して多用されてきた多結晶シリコンや拡散層の抵抗の増
大による信号伝播の遅延等の問題が生じてきた。この問
題を解決する方法として、耐熱性に優れた高融点金属シ
リサイドを多結晶シリコンや拡散層の上部に形成して低
抵抗化を実現する方法が提案されている。特に、微細な
寸法を持ったMI8 (Metal  In5ul a
torSem1 conductor )  型電界効
果トランジスタにおいては、多結晶シリコンゲート取極
の上部に高融点金属シリサイドを形成したいわゆるポリ
サイド電極やソース及びドレインを構成すべき不純物ド
ープ層の上部に高融点金属シリサイドを形成したシリサ
イド化ソース・ドレイン電極の検討が行われている。
(Prior art) In recent years, semiconductor devices such as silicon integrated circuits have become increasingly popular.
In recent years, efforts have been made to increase density and speed by miniaturizing element dimensions. With such miniaturization, problems have arisen, such as delays in signal propagation due to increased resistance of polycrystalline silicon and diffusion layers, which have conventionally been frequently used as luminous poles and wiring. As a method to solve this problem, a method has been proposed in which high-melting-point metal silicide with excellent heat resistance is formed on the polycrystalline silicon or the diffusion layer to achieve low resistance. In particular, MI8 (Metal In5ul a) with minute dimensions
torSem1 conductor ) type field effect transistors have a so-called polycide electrode in which a high melting point metal silicide is formed on top of a polycrystalline silicon gate arrangement, and a high melting point metal silicide is formed on top of an impurity doped layer that is to constitute the source and drain. Silicided source/drain electrodes are being considered.

高融点金属シリサイドの形成方法としては、高融点金属
とシリコンとを同時に蒸着した後、高温のアニールを行
ってシリサイド形成を行う方法、又はシリコンの表面に
高融点金属を蒸着した後、アニールを行ってシリサイド
形成を行う方法(熱アニール法)等が行われている。
Refractory metal silicide can be formed by depositing a high melting point metal and silicon simultaneously and then performing high temperature annealing to form a silicide, or by depositing a high melting point metal on the surface of silicon and then annealing. A method of forming silicide (thermal annealing method) is being used.

(発明が解決しようとする問題点) 前記の従来の方法で形成されるシリサイド薄膜の電気抵
抗は、バルクの値に比して大きい欠点がある。例えば、
ムラ−力(S、PlM・・古・)によ□るシリサイズ 
フォア VLSI  アプリケイションズ(Silic
ides  for VLSI Applicatio
ns(New york Academic Pres
s、  1983) )p、30〜31に記載されてい
る様に、MoSi2の場合にはバルクの比抵抗が〜20
μΩ・ぼであるのに対して、前記の方法で形成されたU
膜の値は100〜150μΩ@ CIILと扁い。
(Problems to be Solved by the Invention) The electrical resistance of the silicide thin film formed by the conventional method described above has a drawback that it is large compared to the bulk value. for example,
□Siri size by uneven force (S, PLM... old...)
Fore VLSI Applications (Silic
ides for VLSI Applications
ns(New York Academic Pres.
s, 1983)) p, 30-31, in the case of MoSi2 the bulk resistivity is ~20
In contrast to the μΩ・bode, the U
The value of the membrane is low at 100-150 μΩ @ CIIL.

低抵抗化のために用いられるシリサイド層の厚み#i、
浅bソース・ドレイン接合の形成及び下地シリコン層へ
の影響を少なくすると言う意力)ら、1000A程度以
下に薄くすることが望ましい。従来の形成法によるMo
Sixでは1000 Aの膜厚を用いた場合にもシート
抵抗は10〜1507口と高い値になり、不十分な低抵
抗化しか達成されてbない。
Thickness #i of the silicide layer used for lowering resistance,
In order to form a shallow b source/drain junction and to reduce the influence on the underlying silicon layer, it is desirable to reduce the thickness to about 1000A or less. Mo by conventional forming method
In Six, even when a film thickness of 1000 A is used, the sheet resistance is as high as 10 to 1507, indicating that only an insufficient reduction in resistance has been achieved.

現在、MoSi2の他にW8i ze TaSi2 f
fi、 TiSi 2等が検討されており、これらの高
融点金属シリサイドについて従来法によった場合より小
さな電気抵抗が得られれば、MIS型電界効果トランジ
スタ等の電衡や配線への応用に対して極めて有用である
Currently, in addition to MoSi2, W8i ze TaSi2 f
fi, TiSi2, etc. are being considered, and if a lower electrical resistance can be obtained with these high-melting point metal silicides than with conventional methods, it will be useful for applications in electrobalance and wiring of MIS field effect transistors, etc. Extremely useful.

更に1 前記熱アニール法によって得られる高融点金属
シリサイド膜は均一性や平滑性が悪く、し力1も8i基
板上のSin!等の層間絶縁膜パターンに対して自己整
合的に形成できないという欠点がある。
Furthermore, the high melting point metal silicide film obtained by the above-mentioned thermal annealing method has poor uniformity and smoothness, and the strength of the film is 1. It has the disadvantage that it cannot be formed in a self-aligned manner with respect to interlayer insulating film patterns such as the above.

本発明の目的は、従来法で得られる高融点金属シリサイ
ド薄膜の示す高電気抵抗の問題点を解消し、かつ膜の均
一性や平滑性を改善し、自己整合性に優れた新規な高融
点金属シリサイドの形成方法を提供することにある。
The purpose of the present invention is to solve the problem of high electrical resistance of high melting point metal silicide thin films obtained by conventional methods, improve the uniformity and smoothness of the film, and create a new high melting point film with excellent self-alignment. An object of the present invention is to provide a method for forming metal silicide.

(問題点を解決するための手段) 本発明によれば、 Mo、 W、 V、 Nb、 Ta
、 Ti、 Zr及びHf 7)zらなる高融点金属と
シリコンとを反応させて高融点金属シリサイドを形成す
る方法において、少なくとも表面にシリコン層を有した
基板に前記高融点金属膜を堆積する場合に、Mo及びW
に対してはそれぞれ正方晶系fyjoSit及びWSi
2が形成される温度、V、Nb及びTa に対してはそ
れぞれ六方晶系VSi z、 NbSi x及びTa5
ix#形成される温度、Ti、 Zr及びHfに対して
はそレソレ斜方晶系Tf8i !、 ZrSi *及び
Hf8i*が形成される温度に前記シリコン層を有した
基板を加熱せしめた状態で前記高融点金属の蒸着を行う
際に、初めの数十へ以下の膜形成に対して、蒸着粒子の
10%以上をイオン化し、且つ前記イオン化した蒸着粒
子をQ、IKeV以上加速して蒸着し、その後所望の膜
厚までイオン化しない状態で蒸着を続け、蒸着と同時に
シリサイド化反応を生じせしめることを特徴とした高融
点金属シリサイドの形成方法が得られる。
(Means for solving the problem) According to the present invention, Mo, W, V, Nb, Ta
, Ti, Zr, and Hf 7) In the method of forming a high melting point metal silicide by reacting a high melting point metal consisting of z with silicon, when the high melting point metal film is deposited on a substrate having a silicon layer on at least the surface. In, Mo and W
for tetragonal fyjoSit and WSi, respectively.
2, hexagonal VSi z, NbSi x and Ta5 for V, Nb and Ta, respectively.
ix #For the temperature at which Ti, Zr and Hf are formed, the orthorhombic system Tf8i! , When performing vapor deposition of the high melting point metal while heating the substrate with the silicon layer to a temperature at which ZrSi* and Hf8i* are formed, the vapor deposition Ionize 10% or more of the particles, accelerate the ionized deposition particles by Q, IKeV or more, and then continue the deposition without ionization until the desired film thickness is reached, causing a silicidation reaction at the same time as the deposition. A method for forming a high melting point metal silicide is obtained.

(作用) 高融点金属シリサイドの電気抵抗を小さくするためには
、低抵抗な結晶相の結晶粒の成長を促しかつ成長した結
晶粒に働く応力等のストレスを小さくすることがM要で
ある。
(Function) In order to reduce the electrical resistance of high-melting point metal silicide, it is essential to promote the growth of crystal grains of a low-resistance crystal phase and to reduce stress such as stress acting on the grown crystal grains.

本発明では、高融点金属シリサイドの低抵抗な結晶相が
得られる様な温度に基板加熱を行って高融点金属を蒸着
させるため、蒸着と同時に結晶粒の成長を促進せしめた
低抵抗な結晶相が得られ、かつ結晶粒に働くストレスを
極めて小さくすることができる。
In the present invention, the substrate is heated to a temperature that allows a low-resistance crystalline phase of high-melting-point metal silicide to be vapor-deposited. can be obtained, and the stress acting on the crystal grains can be extremely reduced.

また、熱反応による場合に高融点金属シリサイド膜の平
滑性、均−性及び自己整合性を劣化させる原因は、高融
点金属とシリコンの反応が不均一に始まるからである。
Furthermore, the reason why the smoothness, uniformity, and self-alignment of the high melting point metal silicide film deteriorates due to thermal reaction is that the reaction between the high melting point metal and silicon begins non-uniformly.

本発明では反応の初期においてシリコン基板上に到達し
た数十A膜厚相当の高融点金属粒子の10%以上は0.
IKeV以上に加速されており、この加速されたイオン
がシリコン基板表面に衝突することによりシリコン基板
表面層を均一に混合し、シリコン基板表面内で均一に反
応が開始することになる。
In the present invention, 10% or more of the high melting point metal particles equivalent to a film thickness of several tens of amps that reach the silicon substrate in the early stage of the reaction are 0.
The accelerated ions collide with the surface of the silicon substrate, uniformly mixing the surface layer of the silicon substrate, and uniformly starting a reaction within the surface of the silicon substrate.

以上のように本発明によれば、均一で低抵抗な高融点金
属シリサイド膜をS i Of等の絶縁膜のパターンに
対して自己整合的に形成することができる。
As described above, according to the present invention, a uniform, low-resistance, high-melting point metal silicide film can be formed in a self-aligned manner with respect to a pattern of an insulating film such as SiOf.

(実施例) 第1図fan、 fb)は、本発明によってP型シリコ
ン基板1上にMoSi24を形成した工程を示す断面模
式図である。通常の酸洗浄を行った後、希釈弗酸処理に
より清浄表面とした5iO−絶縁M2(400A)パタ
ーンを有するP型シリコン基板1をイオン化蒸着装置内
で正方晶系Mo8iz形成温度の下限soo’c以上の
900℃に加熱して、第1図Calに示すように、前記
P型シリコン基板上にイオン化率20%、加速電圧1.
5 KVでMo3を40人の膜厚相当イオン化蒸着した
後、更に360 A の膜厚相当のMo3をイオン化せ
ずに蒸着するこボより、第1図(b)に示すように、蒸
着と同時に均一で比抵抗60μΩ・儂のMoSi*膜4
(約100OA)が露出Si表面にだけ自己整合的に形
成された。
(Example) FIG. 1 (fan, fb) is a schematic cross-sectional view showing the process of forming MoSi 24 on a P-type silicon substrate 1 according to the present invention. After normal acid cleaning, a P-type silicon substrate 1 having a 5iO-insulating M2 (400A) pattern with a clean surface treated with diluted hydrofluoric acid was heated to the lower limit of the tetragonal Mo8iz formation temperature in an ionization vapor deposition apparatus. The P-type silicon substrate is heated to 900° C. and the ionization rate is 20%, and the accelerating voltage is 1.
After ionizing Mo3 with a thickness of 40 people at 5 KV, Mo3 with a thickness of 360 A was further deposited without ionization, as shown in Figure 1(b). Uniform resistivity 60 μΩ・My MoSi* film 4
(approximately 100 OA) was formed only on the exposed Si surface in a self-aligned manner.

これに対し、従来の熱アニール法によって40OAのM
o金属膜3を常温の基板上に堆積させた後、電気炉によ
る窒素雰囲気中の20分間、900℃のアニールを行っ
た場合は、第2図のように不均一で比抵抗150μΩ・
儂のMo8iz膜4がSi0g絶縁膜2上にはみだして
形成された。
On the other hand, by conventional thermal annealing method, 40OA M
o When the metal film 3 is deposited on a substrate at room temperature and then annealed at 900°C for 20 minutes in a nitrogen atmosphere using an electric furnace, it becomes non-uniform and has a specific resistance of 150 μΩ as shown in Figure 2.
My Mo8iz film 4 was formed protruding over the Si0g insulating film 2.

他の高融点金属シリサイドについても本発明の方法によ
って、従来法に比して低抵抗で平滑かつ均一な高融点金
属シリサイド膜が形成できた。なお、上記実施例ではP
型シリコン基板を用いたがN型シリコン基板を用いても
かまわない。
With respect to other high melting point metal silicides, a smooth and uniform high melting point metal silicide film with lower resistance than the conventional method could be formed using the method of the present invention. In addition, in the above example, P
Although a type silicon substrate is used, an N type silicon substrate may also be used.

(発明の効果) 本発明によれば、均一で低抵抗な高融点金属シリサイド
膜を5ioz等の1d用絶縁膜のパターンに対して自己
整合的にm′R:rることができる。
(Effects of the Invention) According to the present invention, a uniform, low-resistance, high-melting point metal silicide film can be self-aligned to the pattern of a 1D insulating film of 5 ioZ or the like by m'R:r.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)、(1))は、本発明の方法にヨってM 
OS 12膜を形成する工程を示す断面模式図である。 第2図は、従来の熱アニール法によって得られたMoS
i2膜の断面模式図である。 第1図 (α) (b) 第2図 Mo 5i02紀縁瞑 oSi2 P型シリコン基オ反
Figures 1(a) and (1)) show that M
FIG. 3 is a schematic cross-sectional view showing a process of forming an OS 12 film. Figure 2 shows MoS obtained by conventional thermal annealing method.
FIG. 2 is a schematic cross-sectional view of an i2 film. Fig. 1 (α) (b) Fig. 2 Mo 5i02 Kienmei oSi2 P-type silicon base

Claims (1)

【特許請求の範囲】[Claims] Mo、W、V、Nb、Ta、Ti、Zr及びHfからな
る高融点金属シリコンとを反応させて高融点金属シリサ
イドを形成する方法において、少なくとも表面にシリコ
ン層を有した基板に前記高融点金属膜を堆積する場合に
、Mo及びWに対してはそれぞれ正方晶系MoSi_2
及びWSi_2が形成される温度、V、Nb及びTaに
対してはそれぞれ六方晶系VSi_2NbSi_2及び
TaSi_2が形成される温度、Ti、Zr及びHfに
対してはそれぞれ斜方晶系TiSi_2、ZrSi_2
及びHfSi_2が形成される温度に前記シリコン層を
有した基板を加熱せしめた状態で前記高融点金属の蒸着
を行う際に、初めの数十Å以下の膜形成に対して、蒸着
粒子の10%以上をイオン化し、且つ前記イオン化した
蒸着粒子を0.1KeV以上加速して蒸着し、その後所
望の膜厚までイオン化しない状態で蒸着を続け、蒸着と
同時にシリサイド化反応を生じせしめることを特徴とし
た高融点金属シリサイドの形成方法。
In a method of forming a high melting point metal silicide by reacting a high melting point metal silicon consisting of Mo, W, V, Nb, Ta, Ti, Zr and Hf, the high melting point metal is added to a substrate having a silicon layer on at least the surface thereof. When depositing films, tetragonal MoSi_2 is used for Mo and W, respectively.
and the temperature at which hexagonal system VSi_2NbSi_2 and TaSi_2 are formed for V, Nb and Ta, respectively, and the orthorhombic system TiSi_2, ZrSi_2 for Ti, Zr and Hf, respectively.
When the high melting point metal is vapor-deposited while the substrate with the silicon layer is heated to a temperature at which HfSi_2 is formed, 10% of the vapor-deposited particles are The method is characterized by ionizing the above particles, accelerating the ionized deposition particles by 0.1 KeV or more to deposit them, and then continuing the deposition in a non-ionized state until the desired film thickness is reached, causing a silicidation reaction to occur at the same time as the deposition. Method of forming high melting point metal silicide.
JP18011185A 1985-08-15 1985-08-15 Formation of high melting point metal silicide Pending JPS6240364A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18011185A JPS6240364A (en) 1985-08-15 1985-08-15 Formation of high melting point metal silicide

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18011185A JPS6240364A (en) 1985-08-15 1985-08-15 Formation of high melting point metal silicide

Publications (1)

Publication Number Publication Date
JPS6240364A true JPS6240364A (en) 1987-02-21

Family

ID=16077610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18011185A Pending JPS6240364A (en) 1985-08-15 1985-08-15 Formation of high melting point metal silicide

Country Status (1)

Country Link
JP (1) JPS6240364A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104561882A (en) * 2015-01-30 2015-04-29 中国钢研科技集团有限公司 High-temperature oxidation resistant coating on niobium alloy surface and preparation method of high-temperature oxidation resistant coating
CN104630722A (en) * 2015-01-27 2015-05-20 航天材料及工艺研究所 Method for preparing anti-oxidation coating on surface of tantalum alloy material

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104630722A (en) * 2015-01-27 2015-05-20 航天材料及工艺研究所 Method for preparing anti-oxidation coating on surface of tantalum alloy material
CN104561882A (en) * 2015-01-30 2015-04-29 中国钢研科技集团有限公司 High-temperature oxidation resistant coating on niobium alloy surface and preparation method of high-temperature oxidation resistant coating

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