JPH0950973A - Formation of silicide layer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make flocculation hardly occur in a narrow part so as to prevent the deterioration of the junction leakage characteristic of the narrow part by vitrifying a first silicide layer formed by causing a reaction between a metallic layer formed on a silicon layer and the silicon layer and forming a second silicide layer by recrystallizing the vitrified first silicon layer. SOLUTION: Firstly, a metallic layer 12 of titanium(Ti) is formed on a silicon layer 11. Then a first silicide layer 13 is formed by causing a reaction between the silicon in the layer 11 and the metal in the layer 12 through first-stage heat treatment. After forming the first silicide layer 13, the layer 13 is doped with silicon as an impurity by implanting silicon ions so that the layer 13 can be vitrified. Argon and nitrogen are also used as impurities for the ion implantation. Thereafter, a second silicide layer 14 is formed by recrytallizing the vitrified first silicide layer 13 through second-stage heat treatment.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a silicide layer, which is related to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art With the miniaturization of devices, the diffusion layers of transistors are becoming more and more shallow. Since the gate wiring width is shrinking, the depth of the diffusion layer must be shallow.
The short channel effect increases and the source / drain breakdown voltage deteriorates. For example, when the gate wiring width is 0.25 μm, the depth of the diffusion layer needs to be about 0.08 μm or less. The sheet resistance of the source / drain increases with the shallowing of the diffusion layer.
As a result, the response speed of the device deteriorates.
If the gate delay time is τpd, the operating frequency f ~ 1 / τ
Due to pd, improvement in operating frequency cannot be expected. This is a disadvantage for microprocessors, especially MPUs that require high-speed operation. Therefore, as a countermeasure for the above, salicide (SA) in which titanium silicide (TiSi ₂ ) with low resistance is selectively formed only on the source / drain is used.
LICIDE) process is receiving attention.

An example of a conventional MOSLSI process will be described with reference to FIG. As shown in (1) of FIG. 8, after forming the element isolation region 112 in the silicon substrate 111, a gate wiring (not shown) including the gate insulating film 113 and the gate electrode 114 is formed. Further, the gate electrode 114
The MOS transistor 110 is formed by forming the source / drain diffusion layers 115 and 116 on the silicon substrate 111 on both sides of. Note that sidewall insulating films 117 and 118 are formed on both sides of the gate electrode 114.

Subsequently, as shown in FIG. 8B, a source / drain diffusion layer 11 is formed by hydrofluoric acid (HF) treatment.
The native oxide film (not shown) on 5,116 is completely removed. Then, a titanium (Ti) film 121 (portion indicated by a chain double-dashed line) is formed to a thickness of 50 nm on the entire surface of the silicon substrate 111. Next, the first-stage heat treatment is performed in a nitrogen (N ₂ ) atmosphere at 600 ° C., and the _second- stage heat treatment is further performed in a nitrogen (N ₂ ) atmosphere at 800 ° C. to form the source / drain diffusion layers 115 and 116. By reacting silicon with titanium of the titanium film 121, low resistance titanium silicide (TiSi ₂ ) layers 122 and 123 are selectively formed. At this time, if the gate electrode 114 is made of polysilicon, a titanium silicide layer (not shown) is also formed on the gate electrode 114. After that, a wet treatment with ammonia-hydrogen peroxide mixture or the like is performed so that the element isolation region 112 and the sidewall insulating films 117 and 1 are formed.
Only the titanium film 121 on 18 is selectively etched and removed.

Subsequently, as shown in FIG. 8C, after forming an interlayer insulating film 131, a connection hole 132 is formed in the interlayer insulating film 131. Then, a blanket tungsten plug 133 is formed in the connection hole 132. Then, after forming an aluminum-based alloy film such as aluminum-silicon, it is patterned to form the wiring 134. The illustration and description of the barrier metal layer formed at the interface with the plug 133 and the adhesion layer formed on the lower surface of the wiring 134 are omitted.

When the MOS transistor 110 is formed by the above manufacturing method, the source / drain diffusion layers 115,
There is an advantage that the resistance of 116 is reduced by about one digit as compared with the structure in which the silicide layers 122 and 123 are not formed.

As another method, there is also proposed a method of forming a titanium film on a silicon substrate and then implanting ions of silicon or the like by setting the projection range at the interface between the silicon substrate and the titanium film. Has been done. This method is called ion-based inter-mixing.
Occurs at the above interface, the natural oxide film formed at the interface is destroyed, and the interfacial reaction between titanium and silicon easily proceeds. Due to such advantages, the finally formed titanium silicide layer becomes a low resistance titanium silicide layer even in the narrow region.

[0008]

However, with the miniaturization of elements, the diffusion layer is also miniaturized. Due to this effect, as shown in FIG. 9, even if an attempt is made to form the titanium silicide layers 122 and 123 on the source / drain diffusion layers 115 and 116 in the narrow portion of the MOS transistor 110, the titanium silicide cannot be aggregated to form a film. ,
There is a problem that the reduction of sheet resistance cannot be expected (IEEE
Symposium on VLSI Technical Papers (1992) I. Saka
i, H.Kawaguchi, T.Hirayama, LEG Johansson and K.Oka
be p.66-67).

For example, as a mechanism of the thin line effect of titanium silicide, there is a crystal change accompanying the formation of titanium silicide. Titanium silicide is generally C4
There are two types, the 9 crystal structure and the C54 crystal structure. Of these, the C54 crystal structure is said to be a low-resistance and stable silicide. Usually, in the salicide process, two stages of heat treatment are performed. The first stage heat treatment is 65
By performing heat treatment at a low temperature of about 0 ° C., titanium on silicon becomes titanium silicide having a C49 crystal structure. Next, unreacted titanium that does not become silicide on the silicon oxide is selectively removed. Then, a high temperature heat treatment at about 800 ° C. is performed to form titanium silicide having a C54 crystal structure having a grain size of several μm. In the case of forming by this process, in the narrow portion, the C49 crystal having a grain size of about 0.1 μm has a large grain size C in the second stage high temperature heat treatment.
It is said that the difficulty of phase transition to 54 crystal is the cause of the thin line effect.

Further, with the shallowing of the diffusion layer, silicide (or salicide) formed on the diffusion layer
It is necessary to thin the layers. However, if the thickness is reduced, it becomes difficult to stably form the titanium silicide layer.
That is, the titanium silicide layer formed in the thin film causes aggregation. Therefore, reduction of the sheet resistance of the silicide (or salicide) layer in the narrow portion cannot be expected.

The increase in the sheet resistance accompanying the thinning of the silicide (salicide) layer or the aggregation of the silicide (salicide) layer that causes the increase in sheet resistance is due to the removal of the natural oxide film on the silicon substrate before the titanium film is formed. Is insufficient. Or, because it is exposed to the atmosphere after pretreatment (usually hydrofluoric acid treatment) before forming the titanium film, oxygen is adsorbed on the silicon substrate to form a non-uniform natural oxide film. . Since the titanium film is formed in this state and the silicidation heat treatment is applied, the silicidation reaction proceeds nonuniformly. As a result, it is considered that the non-uniform silicide tends to be recrystallized and stabilized by the heat treatment after the formation of the silicide layer, so that the aggregation of the silicide is likely to occur.

As a pretreatment before forming the titanium film,
A so-called in-s of a sputtering apparatus for depositing titanium
By performing the pre-treatment in situ, it is possible to prevent the redeposition of the natural oxide film. As a method therefor, a method of performing pretreatment using an argon ion etching apparatus having parallel plate electrodes has been proposed. However, the above ion etching requires an accelerating voltage of at least about 1 kV for accelerating the argon ions in order to obtain sputtering enough to remove the natural oxide film. Therefore, since the surface of the silicon substrate is roughened by the ions that are incident with high ion energy, the silicide layer is nonuniformly formed in the silicidation reaction. Since such a silicide layer has a large film stress, the silicide layer is partially peeled off. In addition, during sputter etching,
To expose to the plasma of a parallel plate type plasma device,
There is also a problem that a thin gate oxide film is damaged by plasma damage and destroyed.

On the other hand, in the method of implanting ions at the interface between titanium and silicon, damage due to ion implantation is formed in the silicon substrate, which causes deterioration of junction leakage. In fact, by forming a titanium salicide layer by silicon ion implantation in a narrow area of 0.45 μm width,
The sheet resistance could be maintained as low as 3Ω / □ (Titanium silicide without silicon ion implantation
The sheet resistance was as high as 30 Ω / □ in the narrow region of 0.45 μm), but the junction leak was deteriorated by one digit or more. Therefore, it is desired to develop a thin silicide (salicide) that hardly causes aggregation even in a narrow portion and suppresses deterioration of junction leak characteristics.

[0014]

The present invention is a method for forming a silicide layer, which has been made to solve the above problems.
That is, in the first step, the metal layer formed on the silicon layer is reacted with the silicon layer to form the first silicide layer. Then, in a second step, the first silicide layer is made amorphous. Then, in the third step, the second silicide layer is formed by recrystallizing the amorphized first silicide layer. Amorphization of the first silicide layer is performed, for example, by implanting impurities into the first silicide layer by ion implantation. Further, for example, after forming a metal nitride film, a metal oxynitride film, or a metal boride film as an antioxidant film on the metal layer, the silicon layer and the metal layer are reacted to form the first silicide layer. Good.

In the method of forming a silicide layer, the first silicide layer obtained by reacting the silicon layer and the metal layer is made amorphous, and then the made amorphous first silicide layer is recrystallized. Since the second silicide layer is formed, the second
The silicide layer is composed of crystal grains having a large grain size (for example, several μm). Since the first silicide layer is made amorphous by implanting impurities into the first silicide layer by ion implantation, the first silicide layer can be easily made amorphous. Further, after forming the metal layer, an antioxidant film is formed on the metal layer, and then the silicon layer and the metal layer are reacted with each other to form the first silicide layer. Therefore, oxygen is formed on the outermost surface of the metal layer. Adhesion of impurities such as hindering silicidation is eliminated. Therefore, a silicide layer having a large grain size is likely to be formed during recrystallization of the amorphized first silicide layer.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 1A, in the first step, the metal layer 12 is formed on the silicon layer 11. The metal layer 12 is formed of titanium (Ti), for example. Alternatively, a silicide such as cobalt (Co), nickel (Ni), tungsten (W), molybdenum (Mo), platinum (Pt), zirconium (Zr), hafnium (Hf), gold (Au), or copper (Cu) is used. It is formed of a metal that can be formed. Then, a first stage heat treatment is performed to react the silicon of the silicon layer 11 with the metal of the metal layer 12 to form a first silicide layer 13 as shown in FIG. The heat treatment in the first stage is set under the condition that the silicon of the silicon layer 11 and the metal of the metal layer 12 cause a silicidation reaction.

Next, the second step shown in FIG. 1C is performed. In this step, the first silicide layer 13 is doped with silicon as an impurity by, for example, an ion implantation method. Thereby, the first silicide layer 13 is made amorphous. In this ion implantation, the implantation energy is adjusted so that silicon is implanted only in the first silicide layer 13. As the impurities used for the ion implantation, in addition to the above silicon, for example, argon (Ar), nitrogen (N),
The metal and arsenic (A
s) or antimony (Sb) can be used.

Thereafter, the third step shown in FIG. 1 (4) is performed. In this step, for example, a second stage heat treatment is performed,
The amorphized first silicide layer 13 is recrystallized to form a second silicide layer 14. The heat treatment in the second stage is set under conditions such that the first silicide layer 13 is recrystallized to form the second silicide layer 14 having a large grain size.

In the method of forming a silicide layer, in the first step, the unreacted metal layer 12 left by the reaction between the silicon layer 11 and the metal layer 12 after forming the first silicide layer 13 is removed, After that, the first silicide layer 13 may be amorphized in the second step.

In the first step, the metal layer 12 is formed on the silicon layer 11, and then an antioxidant film (not shown) is formed on the metal layer 12. As an example of this antioxidant film, a metal nitride film [for example, titanium nitride (TiN)]
Film, hafnium nitride (HfN) film, tungsten nitride (WN) film or zirconium nitride (ZrN) film], metal oxynitride film [eg titanium oxynitride film (TiON)] or metal boride film [eg titanium boride] (TiB)
Membrane]. After that, the silicon layer 11 and the metal layer 1
The first silicide layer 13 may be formed by reacting with 2. In this method, the unreacted metal layer 12 may be removed together with the antioxidant film after the first step and before the second step.

In the above method of forming a silicide layer, the first silicide layer 13 obtained by reacting the silicon layer 11 and the metal layer 12 is made amorphous, and then the first silicide layer 13 made amorphous is formed. Since the second silicide layer 14 is recrystallized to form the second silicide layer 14, the second silicide layer 14 has a large grain size. Therefore, it is possible to form a stable thin film silicide layer having a large grain size. Further, since the first silicide layer 13 is amorphized by implanting impurities into the first silicide layer 13 by ion implantation, the first silicide layer 13 is easily amorphized. At this time, by implanting ions only in the first silicide layer 13, damage to the silicon layer due to the ion implantation is suppressed, so that no junction leak occurs.

Next, an example in which the above embodiment is applied to a salicide process of a metal-oxide film-semiconductor (hereinafter referred to as MOS) transistor will be described with reference to the manufacturing process diagrams of the first embodiment shown in FIGS. explain.

As shown in (1) of FIG.
Depending on the transistor manufacturing process, the silicon substrate 2
1 to form an element isolation region 22, and then a gate insulating film 2
A gate electrode (including a gate wiring) 24 was formed through the layer 3. A so-called cap insulating film (not shown) was formed on the gate electrode 24. In addition, the gate electrode 24
A side wall insulating film 25 was formed on the side portion of. Further, by the ion implantation method, the source / drain diffusion layer 2
6, 27 were formed. In this way, the MOS transistor 20 was formed.

Next, for example, ICP (Induction Couple)
d Plasma) soft etching was performed to remove the natural oxide film (not shown) formed on the source / drain diffusion layers 26 and 27. As the ICP soft etching conditions, for example, argon (Ar) is used as an etching gas.
With an etching atmosphere pressure of 0.06 Pa, Vdc
Of 100 V and ICP power of 1.0 kW. Note that the gate insulating film 23 was not damaged by the argon plasma with the ICP power of the above level.

Subsequently, a titanium film 31 was formed on the entire surface by sputtering. The conditions for forming the titanium film 31 include, for example, a sputtering gas containing argon (A
The film formation temperature (substrate temperature) was set to 150 ° C., the pressure of the film formation atmosphere was 0.47 Pa, and the power was set to 1.0 kW. Then, a titanium film 31 having a thickness of 30 nm was formed.

Then, as shown in (2) of FIG. 2, as the first-stage heat treatment, for example, rapid thermal annealing (hereinafter referred to as RTA, RTA stands for Rapid Thermal Annealing).
Of the source / drain diffusion layers 26 and 27 and titanium of the titanium film 31 are silicide-reacted to form titanium silicide layers 32 and 33 (corresponding to the first silicide layer of FIG. 1). did. As the RTA conditions, for example, annealing is performed at 650 ° C. for 30 seconds in an atmosphere in which a nitrogen (N ₂ ) gas having a flow rate of 5 dm ³ / min is supplied. The RTA conditions are appropriately set to conditions that cause a silicidation reaction depending on the type of metal that reacts with silicon.

After that, as shown in FIG. 2C, silicon (Si ⁺ ) ions are implanted into the titanium silicide layers 32 and 33 by an ion implantation method so that the titanium silicide layers 32 and 33 are amorphous. Turned into As the ion implantation conditions, for example, the implantation energy is 20 keV and the dose is 5 × 1 so that the projected range Rp of the silicon ions is at the center of the film thickness of the titanium silicide layers 32 and 33.
It was set to 0 ¹⁵ pieces / cm ² . Furthermore, the unreacted titanium film 31 (the portion indicated by the chain double-dashed line) was selectively removed by wet etching in which it was immersed in ammonia-hydrogen peroxide mixture.

Subsequently, as shown in FIG. 2D, as a second-stage heat treatment, for example, RTA is performed to stabilize the amorphous titanium silicide layers (32, 33) with C54.
The crystalline titanium silicide layers 34 and 35 (the second titanium in FIG.
Corresponding to the silicide layer). As the RTA conditions, for example, annealing is performed at 800 ° C. for 30 seconds in an atmosphere in which a nitrogen (N ₂ ) gas having a flow rate of 5 dm ³ / min is supplied. The RTA condition is appropriately set to a condition that the amorphous silicide layer becomes a large-grain crystalline silicide layer depending on the constituent elements of the silicide.

Thereafter, as shown in (1) of FIG. 3, for example, chemical vapor deposition (hereinafter, referred to as CVD, CVD is Ch
An interlayer insulating film 41 made of silicon oxide was formed on the entire surface by an embodied vapor deposition method. The above C
The film forming conditions by the VD method are, for example, tetraethoxysilane (TEOS) with a reaction gas flow rate of 50 sccm.
And a film forming temperature of 720 ° C. and a film forming atmosphere pressure of 40
By setting to Pa, the interlayer insulating film 41 was formed to a thickness of 600 nm, for example.

After that, a resist film (not shown) is patterned by a lithography technique (for example, resist coating, exposure, development, baking, etc.), and a connection hole 42 is formed in the interlayer insulating film 41 by an etching technique. The above etching (eg dry etching)
For example, octafluorocyclobutane (C ₄ F ₈ ) was used as the etching gas, the RF power was set to 1.2 kW, and the etching atmosphere pressure was set to 2 Pa.

Next, as shown in FIG. 3B, a titanium film (not shown) as an adhesion layer and a titanium nitride film 43 as a barrier metal layer are formed inside each of the connection holes 42 by sputtering. Thereafter, the blanket tungsten plug 44 was formed by a usual process.
The sputtering conditions for the titanium film are as follows: Argon (A
r), power is 8 kW, film formation temperature is 150
℃, the pressure of the film forming atmosphere is set to 0.47 Pa, 10
A titanium film having a thickness of nm was formed. Further, as the sputtering conditions for the titanium nitride film 43, argon (Ar) having a flow rate of 40 sccm and nitrogen (N ₂ ) having a flow rate of 20 sccm are used as the sputtering gas, for example, power is 5 kW and pressure of the film forming atmosphere is 0. Setting to 47 Pa, a titanium film having a film thickness of 70 nm was formed.

The blanket tungsten plug 44
Was formed as follows. First, by the CVD method,
A tungsten film was formed. CV of the tungsten film
As the D condition, for example, the reaction gas has a flow rate of 2200 s.
ccm argon (Ar), flow rate 300 sccm nitrogen (N ₂ ), flow rate 500 sccm hydrogen (H ₂ ) and flow rate 75 sccm tungsten hexafluoride (W).
F ₆ ) was used to set a film forming temperature at 450 ° C. and a film forming atmosphere pressure at 10.64 kPa to form a tungsten film having a thickness of 400 nm. Then, the tungsten film was etched back. As the etch back conditions, for example, sulfur hexafluoride (SF ₆ ) having a flow rate of 50 sccm was used as the etching gas, the RF power was set to 150 W, and the etching atmosphere pressure was set to 1.33 Pa.

Then, a titanium film 45 serving as an adhesion layer and an aluminum-based metal film 46 serving as a main wiring material are formed on the entire surface of the blanket tungsten plug 44 and the interlayer insulating film 41 by, for example, sputtering. As the film forming conditions for the titanium film 45, for example, argon (Ar) having a flow rate of 100 sccm is used as the sputtering gas, and the pressure of the sputtering atmosphere is 0.4.
A film having a thickness of 30 nm was formed by setting 7 Pa, the substrate temperature at 150 ° C., and the power at 4 kW. As the film forming conditions for the aluminum-based metal film 46, for example, argon (Ar) with a flow rate of 50 sccm is used as the sputtering gas, the pressure of the sputtering atmosphere is 0.47 Pa, the substrate temperature is 150 ° C., and the power is 22.5 kW. Set to
A film was formed to a thickness of 0.5 μm.

After that, a resist pattern (not shown) is formed by a lithography technique, and then a portion indicated by a chain double-dashed line between the aluminum-based metal film 46 and the titanium film 45 is removed by dry etching to remove the aluminum-based metal. A wiring layer 47 was formed by the film 46 and the titanium film 45. The dry etching conditions include, for example,
Boron trichloride (BCl ₃ ) having a flow rate of 60 sccm and chlorine (Cl ₂ ) having a flow rate of 90 sccm were used as the etching gas, and the microwave power was set to 1.0 kW, the RF power was set to 50 W, and the etching atmosphere pressure was set to 16 mPa. .

In the above manufacturing method, when the cap insulating film is not formed on the gate electrode 24 and the polysilicon forming the gate electrode 24 is exposed,
A titanium silicide layer (not shown) is formed on the upper portion of the gate electrode 24 as well as the source / drain diffusion layers 26 and 27.

In the method of manufacturing the MOS transistor described above,
C49 crystal titanium silicide layer 3 by the first stage heat treatment
After forming 2, 33, the titanium silicide layer 32,
Titanium silicide layers 32 and 33 were made amorphous by ion-implanting silicon into 33, and then second-stage heat treatment was performed to recrystallize to form C54 crystal titanium silicide layers 34 and 35. Therefore, in the above manufacturing method,
Since the C49 crystal becomes amorphous, the phase transition to the C54 crystal easily occurs.

The silicon ion implantation conditions are set so that the projected range Rp of the silicon ions is the titanium silicide layers 32 and 3.
Since it was set to the center of the film thickness of 3,
Damage to the drain diffusion layers 26 and 27 due to ion implantation does not occur. Therefore, no junction leak occurs.

Next, an example in which the above embodiment is applied to the salicide process of a MOS transistor will be described with reference to the manufacturing process diagram of the second embodiment of FIG.

The second embodiment described here is a modification only to (2) to (4) in FIG. 2 of the first embodiment described with reference to FIG. Therefore, only the modified process will be described here. In the figure, the same components as those described in FIG. 2 are designated by the same reference numerals.

As shown in FIG. 4A, the source / drain diffusion layers 26 and 27 are formed by ICP soft etching after forming the MOS transistor 20 in the same manner as described in FIG. 2A. The natural oxide film (not shown) formed on each surface of was removed. The etching conditions are the same as those described above. Immediately after that, the titanium film 31 was formed on the entire surface by sputtering. The film forming conditions are the same as those described above.

Then, as shown in (2) of FIG. 4, as the first-stage heat treatment, for example, RTA is performed to perform the silicon of the source / drain diffusion layers 26 and 27 and the titanium film 31.
The titanium and the titanium are subjected to a silicidation reaction to form titanium silicide layers 32 and 33 of C49 crystal. This RTA condition is the same as the condition described in (2) of FIG. 2 above. Then, the unreacted titanium film 31 is immersed in ammonia-hydrogen peroxide mixture.
(A portion indicated by a chain double-dashed line) was selectively removed.

Thereafter, as shown in (3) of FIG. 4, silicon (Si ⁺ ) ions are implanted into the titanium silicide layers 32 and 33 by an ion implantation method to make the titanium silicide layers 32 and 33 amorphous. Turned into The ion implantation conditions are the same as those described in (3) of FIG.

Subsequently, as shown in FIG. 4D, as the second stage heat treatment, for example, RTA is performed to transform the amorphous titanium silicide layers 32 and 33 into stable C54 crystal titanium silicide layer 34. , 35. This RT
The condition A is the same as the condition described in (4) of FIG.

The subsequent steps are the same as those in the first embodiment.

Also in the manufacturing method of the second embodiment, when the gate electrode 24 is made of polysilicon, the upper layer portion of the gate electrode 24 is formed in the same manner as the source / drain diffusion layers 26 and 27. A titanium silicide layer (not shown) is formed.

Second Method of Manufacturing the MOS Transistor
Also in the example, as in the first example, the C49 crystal becomes amorphous, so that the phase transition to the C54 crystal easily occurs. Further, since the ion implantation conditions of silicon are set so that the projected range Rp of silicon ions is at the center of the film thickness of the titanium silicide layers 32 and 33, the source / drain diffusion layers 26 and 27 are not damaged by the ion implantation. Does not occur. Therefore, no junction leak occurs.

Next, an example in which the above embodiment is applied to the salicide process of a MOS transistor will be described with reference to the manufacturing process chart of the third embodiment of FIG.

The third embodiment described here is a modification only to (2) to (4) of FIG. 2 of the first embodiment described with reference to FIG. Therefore, only the modified process will be described here. In the figure, the same components as those described in FIG. 2 are designated by the same reference numerals.

As shown in FIG. 5A, after forming the MOS transistor 20 in the same manner as described in FIG. 2A, the source / drain diffusion layers 26 and 27 are formed by ICP soft etching. The natural oxide film (not shown) formed on each surface of was removed. The etching conditions are the same as those described above. Immediately after that, the titanium film 31 was formed on the entire surface by sputtering. The film forming conditions are the same as those described above. Further, a titanium nitride film 51 was formed on the titanium film 31 as an antioxidant film. The conditions for forming the titanium nitride film 51 are as follows:
For example, argon (Ar) with a flow rate of 40 sccm and nitrogen (N ₂ ) with a flow rate of 20 sccm are used as the sputtering gas, and the pressure of the sputtering atmosphere is 0.47 Pa,
The power was set to 5 kW and the titanium nitride film 51 was formed to a thickness of 20 nm.

Then, as shown in FIG. 5B, RTA is performed as the first-stage heat treatment, and the silicon of the source / drain diffusion layers 26 and 27 and the titanium film 31 are formed.
The titanium and the titanium are subjected to a silicidation reaction to form titanium silicide layers 32 and 33 of C49 crystal. This RTA condition is the same as the condition described in (2) of FIG. 2 above.

Then, the titanium nitride film 51 is removed by etching. Then, as shown in FIG. 5C, the titanium silicide layer 3 is formed by an ion implantation method.
Silicon (Si ⁺ ) ions are implanted into the layers 2 and 33 to make the titanium silicide layers 32 and 33 amorphous. The ion implantation conditions are the same as those described in (3) of FIG. Furthermore, the unreacted titanium film 31 (the portion indicated by the chain double-dashed line) was selectively removed by wet etching in which it was immersed in ammonia-hydrogen peroxide mixture. The titanium nitride film 51 may be removed after the ion implantation. In that case, the above-mentioned ion implantation conditions are the titanium nitride film 51.
The implantation energy is set so that the projected range Rp of the silicon ions is at the center of the film thickness of the titanium silicide layers 32 and 33 in consideration of the film thickness.

Then, as shown in FIG. 5D, for example, RTA is performed as a second-stage heat treatment to transform the amorphous titanium silicide layers 32 and 33 into stable C54 crystal titanium silicide layer 34. , 35. This RT
The condition A is the same as the condition described in (4) of FIG.

The subsequent steps are the same as in the first embodiment.

Also in the manufacturing method of the third embodiment, when the gate electrode 24 is made of polysilicon, the upper layer portion of the gate electrode 24 is formed in the same manner as the source / drain diffusion layers 26 and 27. A titanium silicide layer (not shown) is formed.

Third Method of Manufacturing MOS Transistor
Also in the example, as in the first example, the C49 crystal becomes amorphous, so that the phase transition to the C54 crystal easily occurs. Further, since the ion implantation conditions of silicon are set so that the projected range Rp of silicon ions is at the center of the film thickness of the titanium silicide layers 32 and 33, the source / drain diffusion layers 26 and 27 are not damaged by the ion implantation. Does not occur. Therefore, no junction leak occurs.

Next, an example in which the above embodiment is applied to the salicide process of a MOS transistor will be described with reference to the manufacturing process chart of the fourth embodiment of FIG.

The second embodiment described here is a modification of only (2) to (4) of FIG. 2 of the first embodiment described with reference to FIG. Therefore, only the modified process will be described here. In the figure, the same components as those described in FIG. 2 are designated by the same reference numerals.

As shown in FIG. 6A, first, the MOS transistor 20 is formed in the same manner as described in FIG. 2A, and then the source / drain diffusion layers 26 and 27 are formed by ICP soft etching. The natural oxide film (not shown) formed on each surface of was removed. The etching conditions are the same as those described above. Immediately after that, the titanium film 31 was formed on the entire surface by sputtering. The film forming conditions are the same as those described in the second embodiment. Further, a titanium nitride film 51 was formed on the titanium film 31 as an antioxidant film. The conditions for forming the titanium nitride film 51 are the same as those described in the third embodiment.

Then, as shown in FIG. 6B, RTA is performed as a first-stage heat treatment so that the silicon of the source / drain diffusion layers 26 and 27 and the titanium film 31 are formed.
The titanium and the titanium are subjected to a silicidation reaction to form titanium silicide layers 32 and 33 of C49 crystal. This RTA condition is the same as the condition described in (2) of FIG. 2 above.

Then, the titanium nitride film 5 is etched.
1 was removed, and the titanium film 31 that had not reacted was selectively removed by further immersing it in ammonia-hydrogen peroxide mixture. Subsequently, as shown in (3) of FIG. 6, silicon (Si ⁺ ) ions are implanted into the titanium silicide layers 32 and 33 by an ion implantation method to amorphize the titanium silicide layers 32 and 33. . The ion implantation conditions are the same as those described in (3) of FIG.

Subsequently, as shown in FIG. 6D, as the second stage heat treatment, for example, RTA is performed to convert the amorphous titanium silicide layers 32 and 33 into stable C54 crystal titanium silicide layer 34. , 35. This RT
The condition A is the same as the condition described in (4) of FIG.

The subsequent steps are the same as those in the first embodiment.

Also in the manufacturing method of the fourth embodiment, when the gate electrode 24 is formed of polysilicon, the upper layer portion of the gate electrode 24 is formed in the same manner as the source / drain diffusion layers 26 and 27. A titanium silicide layer (not shown) is formed.

Fourth Method of Manufacturing MOS Transistor
Also in the example, as in the first example, the C49 crystal becomes amorphous, so that the phase transition to the C54 crystal easily occurs. Further, since the ion implantation conditions of silicon are set so that the projected range Rp of silicon ions is at the center of the film thickness of the titanium silicide layers 32 and 33, the source / drain diffusion layers 26 and 27 are not damaged by the ion implantation. Does not occur. Therefore, no junction leak occurs.

Next, the sheet resistance of the titanium silicide layers 34 and 35 formed by the method of forming a silicide layer of the present invention will be described with reference to FIG. In the figure, the vertical axis represents the sheet resistance of the titanium silicide layers 34 and 35, and the horizontal axis represents the width of the source / drain diffusion layers 26 and 27 of the transistor.

As shown in the figure, the sheet resistance R of the titanium silicide layer formed by the method of forming a silicide layer according to the present invention.
(Indicated by a solid line) is almost constant regardless of the width of the source / drain diffusion layer. On the other hand, the sheet resistance R ′ of the titanium silicide layer formed by the conventional method shown as a comparative example.
The width of the source / drain formation layer is 1 μm (shown by the broken line).
It rises sharply below a certain level. As described above, it was found that the thin line effect does not occur in the titanium silicide layer of the present invention. Moreover, since the sheet resistance of the silicide layer does not increase, the response speed of the semiconductor device can be improved.

In the description of each of the above embodiments, the titanium silicide layer has been described as a representative, but transition metals other than titanium, for example, cobalt (Co), nickel (Ni), tungsten (W), molybdenum (Mo). , Platinum (P
The method of forming a silicide layer of the present invention can be similarly applied when forming a silicide of t), zirconium (Zr), hafnium (Hf), gold (Au), copper (Cu), or the like. .

In the method of forming the silicide layer described above, the metal film such as the titanium film is formed by sputtering or CVD.
Method or another film forming method may be used. Also, the third
Although the titanium nitride film 51 is formed in the fourth embodiment,
Other antioxidant films may be formed. Examples of other anti-oxidation films of the titanium nitride film 51 include metal nitride films [for example, hafnium nitride (HfN) film, tungsten nitride (WN) film or zirconium nitride (ZrN) film], metal oxynitride films [for example, , Titanium oxynitride film (TiON)] or metal boride film [eg titanium boride (TiB)]
Membrane]. Furthermore, the method of forming a silicide layer described above can be applied to a method of manufacturing a semiconductor device such as a bipolar transistor or a CCD as a device other than a MOS device.

[0070]

As described above, according to the present invention,
Since the first silicide layer is made amorphous and is recrystallized to form the second silicide layer, the second silicide layer can form a stable silicide layer with a large grain size. Therefore, the thin silicide layer can be stably formed in a narrow region, so that the resistance of the silicide layer can be reduced. Therefore, by forming the silicide layer of the semiconductor device according to the present invention, high integration, high frequency, low voltage, and low power consumption of the semiconductor device can be achieved.

[Brief description of drawings]

FIG. 1 is a process drawing of an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram (1) of a MOS transistor of the first embodiment.

FIG. 3 is a manufacturing process diagram (2) of the MOS transistor of the first embodiment.

FIG. 4 is a manufacturing process diagram of the MOS transistor of the second embodiment.

FIG. 5 is a manufacturing process diagram of a MOS transistor according to a third embodiment.

FIG. 6 is a manufacturing process diagram of a MOS transistor of a fourth embodiment.

FIG. 7 is a relationship diagram between the sheet resistance and the width of the source / drain diffusion layer.

FIG. 8 is a manufacturing process diagram of a conventional example.

FIG. 9 is an explanatory diagram of a problem.

[Explanation of symbols]

 11 silicon layer 12 metal layer 13 first silicide layer 14 second silicide layer

Claims (8)

[Claims] 1. A first silicide layer is formed by reacting a metal layer formed on a silicon layer with the silicon layer.
A second step of amorphizing the first silicide layer, and a second step of recrystallizing the amorphized first silicide layer.
And a third step of forming a silicide layer. 2. The method of forming a silicide layer according to claim 1, wherein in the second step, the first silicide layer is made amorphous by implanting impurities into the first silicide layer by ion implantation. A method for forming a characteristic silicide layer. 3. The method for forming a silicide layer according to claim 1, wherein the unreacted metal layer left by a reaction between the silicon layer and the metal layer is formed after the first step and before the second step. A method for forming a silicide layer, which comprises removing the silicide layer. 4. The method for forming a silicide layer according to claim 2, wherein the unreacted metal layer left by the reaction between the silicon layer and the metal layer is formed after the first step and before the second step. A method for forming a silicide layer, which comprises removing the silicide layer. 5. The method for forming a silicide layer according to claim 1, wherein in the first step, an antioxidation film is formed on a metal layer formed on a silicon layer, and then the silicon layer and the metal layer are separated from each other. A method of forming a silicide layer, which comprises reacting to form a first silicide layer. 6. The method for forming a silicide layer according to claim 2, wherein in the first step, an antioxidant film is formed on a metal layer formed on a silicon layer, and then the silicon layer and the metal layer are separated from each other. A method of forming a silicide layer, which comprises reacting to form a first silicide layer. 7. The method of forming a silicide layer according to claim 5, wherein the unreacted metal layer is removed together with the antioxidant film after the first step and before the second step. Method of forming silicide layer. 8. The method for forming a silicide layer according to claim 6, wherein the unreacted metal layer is removed together with the antioxidant film after the first step and before the second step. Method of forming silicide layer.