KR100270185B1 - Low temperature formation of low resistivity titanium silicide - Google Patents

Abstract

The low resistance titanium silicide and semiconductor device comprising the same according to the present invention can be formed by a titanium alloy comprising titanium and 1 to 20 atomic percent refractory metal, deposited in a layer on a silicon substrate. The substrate is then heated to a temperature sufficient to form substantially titanium silicide on C54. The titanium alloy may also include silicon, and the refractory metal may be Mo, W, Ta, Nb, V or Cr, more preferably Ta or Nb. The heating step used to form the low resistance titanium silicide is performed at a temperature below 900 ° C., preferably at about 600 ° C. to 700 ° C.

Description

Low resistance titanium silicide layer formation method and semiconductor device including same TECHNICAL FIELD

FIELD OF THE INVENTION The present invention relates to integrated circuit devices, and more particularly, to a method of forming a titanium silicide layer on a silicon layer in an integrated circuit device using a refractory metal to reduce the phase transformation temperature of the titanium silicide. .

Titanium silicides have become the most widely used silicides in the VLSI industry for self-aligned silicide applications because of their combination of low resistance, self-alignment, and relatively good thermal stability. Although TiSi ₂ has certain advantages over other silicides, the fact that it is a polymorphic material presents another problem in use. Specifically, in typical use, TiSi ₂ is an orthorhombic base-centered phase (known in the art as the C49 phase) having 12 atoms per unit cell and a resistance of about 60-90 micro-ohm-cm. Or as a more thermodynamically preferred an orthorhombic face-centered phase having 24 atoms per unit cell and a resistance of about 12-20 micro-ohm-centimeters. When using commonly used treatment steps to form titanium silicide, a less desirable, higher resistance C49 phase is formed first. A second high temperature annealing step is required to obtain the low resistance C54 phase. This second step is disadvantageous because it adversely affects silicides and other integrated circuit devices, especially those of smaller line-widths. For example, in some devices where more double doped polysilicon gate structures are used, the device's sensitivity to additional thermal cycles has been increased, as required in the second annealing step. In addition, peeling and breaking of silicon nitride is also associated with this second annealing step.

A series of processing steps that are commonly used to form titanium silicides include (1) pre-cleaning, (2) titanium deposition, (3) silicide formation at temperatures below about 700 ° C., (4) selective etching, and ( 5) phase transition annealing at temperatures above about 700 ° C. Converting the dominant C49 phase to C54 phase is phase transition annealing. The initial formation temperature is kept below 700 ° C. to minimize over-spacer bridging. The second transition annealing is carried out after any unreacted titanium is selectively removed and is usually carried out at a temperature of 50-200 ° C. above the forming temperature to complete control over sheet C54 to best control sheet resistance. To ensure the transition. However, as the line width and silicide film thickness of the device continue to decrease, it becomes more desirable to eliminate the need for a second annealing step as will be described in more detail later.

It is common for the C49 phase to be formed first because the surface energy of the C49 phase is lower than the surface energy of the C54 phase. That is, the higher surface energy on C54 results in a higher energy barrier to its formation. The second transition annealing step used in the above standard processing provides additional heat energy needed to overcome the nucleation barrier associated with the formation of new surfaces and grow the lattice structure on the newly formed C54. In VLSI applications, if phase transitions are inhibited or do not occur uniformly, degradation of circuit performance is observed. In some higher performance circuits, the RC delay associated with the bad phase transition is typically about 5-10 percent.

An important problem in the phase transition of C49-C54 is a phenomenon known as agglomeration. If the thermal energy used to achieve the phase transition is excessive, morphological degradation of titanium silicide, commonly called agglomeration, occurs. As the line width and silicide film thickness decrease, the heat energy required to phase transfer C49 to C54 increases, and the heat energy level at which the silicide film begins to agglomerate decreases. Thus, there is an ever-shirinking process window for performing such phase transitions, which results in more difficult process control and uniformity.

Thus, there is a need for an improved method of forming the C54 phase of titanium silicide, without the need for a second high temperature annealing step in commonly used conventional processing. Eliminating the second annealing step or reducing the temperature required to transfer the C49 phase to the desired C54 phase titanium silicide can eliminate the problems associated with high temperature treatment and the limitations resulting from the agglomeration of the silicide film during phase transition annealing.

1 to 3 are cross-sectional views illustrating C54 phase formation of titanium silicides in accordance with an aspect of the present invention.

4 is a graph of sheet resistance versus sputtered titanium thickness for several treatments with and without refractory metal in accordance with the present invention.

5 to 8 are in situ scanning resistance graphs showing sheet resistance of titanium silicide layers formed for some treatment cases with and without use of refractory metals formed by deposition or by implantation in accordance with the present invention. .

FIG. 9 is a bar graph of titanium silicide line resistance measured for Mo ion implanted and non-ion implanted according to the present invention. FIG.

10 and 11 are cross-sectional side views illustrating the formation of titanium silicide on C54 in accordance with an aspect of the present invention.

FIG. 12 is a graph showing normal sheet resistance versus temperature in forming titanium silicide from pure Ti, Ti (tantalum) alloys and Ti (niobium) alloys.

FIG. 13 is a graph showing the atomic percent of resistance versus refractory metal of a titanium silicide layer annealed at 900 ° C. FIG.

FIG. 14 is a graph showing the atomic percent of resistance versus refractory metal of a titanium silicide layer annealed at 700 ° C. FIG.

FIG. 15 is a graph showing atomic percentage of refractory metals versus formation temperature of C54 titanium silicide. FIG.

16 is a cross sectional view showing a portion of a semiconductor device with low resistance titanium silicide of the present invention.

Explanation of symbols for the main parts of the drawings

10 silicon substrate 12 upper surface

14: refractory metal 16: titanium layer

18,50: titanium silicide layer 30: titanium alloy layer

32: titanium 54 silicide layer 52: source on C54

54 drain 56 gate contact

59 gate 62 oxide spacer

By the method of the present invention, this need is met, the conventional limitations are overcome, and other advantages according to the principles of the present invention are realized. The present invention provides a method of forming a metal silicide over a silicon layer on a semiconductor wafer. The method includes forming a titanium silicide layer on a silicon substrate of a semiconductor device, the method comprising: (1) depositing a titanium alloy layer of 1 to 20 atomic percent refractory metal on a silicon substrate, (2 Heating the titanium alloy to a temperature sufficient to form a titanium silicide substantially on C54 from the titanium alloy. The temperature at this time may be less than about 700 ℃.

In one application of the method the titanium alloy may consist of 1 to 15 atomic percent refractory metal, which may consist of one or more of the group consisting of Ta, Nb, Mo, W, V and Cr. Titanium alloys may consist of titanium, silicon and refractory metals such as TiSi ₂ and refractory metals. The semiconductor substrate may be selected from monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium alloy, silicon on insulator (SOI) containing N-type dopant and SOI containing P-type dopant. The titanium alloy may be deposited onto the silicon substrate by physical vapor deposition or chemical vapor deposition.

Another aspect of the invention includes a semiconductor device having a titanium silicide layer on C54, the device comprising (1) a silicon layer and (2) a titanium silicide layer formed over the silicon layer, wherein the titanium silicide layer is substantially Titanium silicide on C54 and from 1 to 20 atomic percent refractory metal. Another aspect of the semiconductor device according to the invention is a silicon layer selected from the group consisting of monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium alloy, SOI containing N-type dopant and SOI containing P-type dopant. Include. The semiconductor device of the present invention may comprise a titanium silicide layer consisting of 10 to 200 nm thick comprising 1 to 15 atomic percent refractory metal.

According to one embodiment of the invention, after the refractory metal is disposed near the surface of the silicon layer and the titanium metal layer (hereinafter used to form titanium silicide) is deposited over the refractory metal, the wafer is sufficient to form titanium silicide. Heated to temperature.

In a second embodiment, the titanium metal layer may also be provided with silicon, for example as in known polycide treatments. If the titanium metal layer comprises silicon, the final titanium silicide is obtained by heating the wafer to a temperature sufficient to obtain the desired solid phase after the Ti-silicon alloy (which in some cases may be stoichiometric) is deposited. In addition to Si, the precursor metal layer is a B, C, N, O, Al, P, S, Zn, Ga, Ge, As, Se, Cd, In, Sn, Sb, Te, Hg, Tl in the periodic table. And other elements from groups IIB, IIIA, IVA, VA, and VIA, including Pb and Bi.

The refractory metal is preferably a metal capable of forming metal silicides, and the concentration of the refractory metal at the surface of the silicon layer is preferably greater than about 10 ¹⁷ atoms / cm 3. The refractory metal may be Mo, W, Ta, Nb, V or Cr. The silicon layer may be monocrystalline or polycrystalline, but is preferably polycrystalline. The heating step used to form the silicide is carried out at a temperature below about 700 ° C., more preferably at about 600-700 ° C.

There are several methods that can be used to place refractory metals. In general, these placement methods place refractory metal atoms on the surface or within a few angstroms of the surface, for example within about 2 GPa. The first method of placing refractory metals is by ion implantation in an amount of about 10 ¹² to 5 × 10 ¹⁴ atoms / cm 2, more preferably in an amount of about 10 ¹³ to 10 ¹⁴ atoms / cm 2. Preferred implantation energy is between about 15 and 90 KeV. According to another method, the refractory metal is disposed on the surface of the silicon layer by evaporating a so-called metal pellet. The refractory metal may also be disposed by sputtering or by exposing the surface of the silicon layer to a solution containing refractory metal ions. For example, this solution may be a dilute acid solution containing HCl or nitric acid. Under all of the above batch methods except ion implantation, the thickness of the refractory metal layer disposed on the silicon surface is preferably less than about 2.0 nm, more preferably about 0.01 to 1.5 nm.

Optionally, the wafer is annealed after the refractory metal placement step and before the precursor metal layer deposition step. Preferably, this annealing step is performed at a wafer temperature of at least about 900 ° C, more preferably between about 900 ° C and 1000 ° C. In one method, this annealing is performed using rapid thermal annealing (RTA) for at least about 5 seconds. Alternatively, a method of annealing in the furnace for at least about 10 minutes may be used.

In another method for the present invention, a titanium silicide layer is formed over a silicon layer on a semiconductor wafer. According to this method, a refractory metal is disposed near the surface of the silicon layer, and after the titanium layer is deposited on the refractory metal, the wafer is heated to a sufficient temperature to form a titanium silicide layer from at least a portion of the titanium layer. Preferably the titanium silicide layer formed during this heating step substantially represents the C54 phase of TiSi ₂ . Preferably, the titanium layer is deposited to a thickness of about 25-57.5 nm and the TiSi ₂ layer is formed at a temperature below about 700 ° C., more preferably at about 600-700 ° C. In addition, the refractory metal is preferably Mo, W, Ta, Nb, V or Cr, and is preferably disposed by ion implantation or metal deposition. Mo, Ta and Nb showed the best results even for W. Ion implantation is preferably performed at an implantation amount of about 10 ¹³ to 10 ¹⁴ atoms / cm 2. Preferably, the annealing step according to the selection described above is carried out.

In another embodiment according to the invention, depositing a titanium layer containing a small amount of refractory metal on a silicon layer and heating the wafer to a temperature sufficient to form titanium silicide on the semiconductor wafer. A metal silicide layer is formed over the silicon layer. The phase transition temperature of titanium silicide from C49 to C54 is lowered by the refractory metal present on the surface of the silicon layer. Preferably, titanium and refractory metal are deposited during the same deposition treatment, with the atomic percent of the refractory metal layer in the source being less than about 20 atomic percent, preferably between 1 and 15 atomic percent.

In a preferred method according to another embodiment of the invention, the titanium layer is deposited from a titanium source which also contains a small amount of refractory metal. The wafer is then heated to a temperature sufficient to substantially form a C54 phase of titanium silicide. Preferably, this temperature is less than about 700 ° C. and the atomic percentage of the refractory metal is less than about 20 atomic percent.

An advantage of the present invention is that the phase transition annealing step is eliminated. For example, for titanium silicide, the desired C54 phase is formed directly during the titanium silicide formation step. No second phase transition annealing is needed to transfer TiSi ₂ from C49 to C54. In addition, since the titanium silicide film is exposed to lower processing temperatures, agglomeration is essentially eliminated. As another advantage of the present invention, the ability to control the final microstructure of the C54 phase of the silicide film is improved, and the particle size of the C54 phase particles can be smaller than the critical dimension of the device being manufactured.

In one embodiment, a refractory metal is disposed near the surface of the silicon layer, and a titanium layer is deposited over the refractory metal and the silicon surface. The wafer is then heated to a temperature of about 600 to 700 ° C. for a time sufficient to form the C54 phase of titanium silicide.

More specifically, referring to FIG. 1, a silicon layer 10, which may be a single crystal silicon wafer 100 or polycrystalline silicon, is provided. Silicon layer 10 may be, for example, a polycrystalline N or P type line or a single crystal N or P type region. The refractory metal is disposed on or near the top surface 12 of the silicon layer 10 depending in part on how the metal is disposed. The refractory metal acts to lower the surface energy barrier for forming the C54 phase of TiSi ₂ , and therefore, the presence of the refractory metal on or near the surface is believed to promote the formation of the C54 phase. It is believed that a refractory metal-silicon alloy is formed in the vicinity of the upper surface 12. It is not clear whether this is a metal-silicon composite or a metal-silicon compound. In general, some of the disposed refractory metal should be present in the top surface 12 or in a few angstroms from the top surface. Of course, the exact placement of the refractory metal atoms depends on the placement method. However, each placement method described herein for the purpose of this application is considered to place refractory metal atoms in the vicinity of the silicon surface.

Referring now to FIG. 2, it is shown that the refractory metal 14 is near the surface of the silicon layer 10. First, it should be understood that FIG. 2 is for illustrative purposes only, and that the refractory metal 14 does not necessarily cover the entire top surface 12. Second, it should be noted that the distribution of the refractory metal 14 also varies with the placement method. For example, when the refractory metal 14 is disposed by ion implantation, most of the metal is located below the upper surface 12. On the other hand, if the metal is disposed by vapor deposition, most of the metal is disposed on the surface rather than below the upper surface 12. For both ion implantation and deposition, lowering the energy barrier on the C54 phase surface is considered to be the concentration of refractory metal in the vicinity of the upper surface 12. After the refractory metal 14 is disposed, the titanium layer 16 is deposited over the refractory metal 14 by so-called sputtering or vapor deposition. For example, thicknesses of 25 to 57.5 nm are used, and those skilled in the art will appreciate that thicknesses larger or smaller may also be used. The upper surface 12 is not explicitly shown in FIG. 2 because its position will vary depending on the refractory metal placement method used.

In addition to sputtering or vapor deposition, it is also possible to deposit titanium layer 16 over refractory metal 14 by chemical vapor deposition. In addition, when depositing by one of these methods, it is also possible to deposit a layer containing Ti and Si alloys rather than a pure titanium layer. Such alloys may be stoichiometric TiSi ₂ , but are not required to be, and Ti-Si alloys may be large or small in their silicon compounds. When depositing a Ti-Si alloy, the method according to the invention is substantially similar to that described herein. Those skilled in the art will understand any modifications necessary. Also, as used herein, the deposition of a titanium layer may alternatively refer to the deposition of a titanium-silicon alloy layer.

In FIG. 3, a TiSi ₂ film 18 was formed over the silicon layer 10 by heating the silicon layer 10 to a temperature between about 600 ° C. and 700 ° C. for a time sufficient to form a C54 phase of TiSi ₂ . This time is generally about 20 seconds for RTA to about 20 minutes for annealing in a conventional furnace. According to the method of the present invention, the formation of the TiSi ₂ film does not substantially pass through the C49 phase, but rather proceeds directly to the C54 phase due to the lowered surface energy barrier.

The optional annealing step is found to be advantageous for further promoting the formation of the C54 phase of TiSi, especially when forming silicides at low temperatures, ie below about 650 ° C. Annealing according to this selection is carried out after the placement of the refractory metal 14 and before the deposition of the Ti layer 16. In general, such annealing can be performed at a wafer temperature of at least about 900 ° C., more preferably at a wafer temperature of 900-1000 ° C., for at least about 5 seconds using RTA, and about 10-30 minutes using a conventional quartz furnace. Run for hours. Preferred annealing is performed at a temperature of about 900 ° C. for about 10 minutes in the furnace in an N ₂ environment. Annealing according to this choice is also believed to be able to promote the formation of a refractory metal-silicon alloy at the surface of the silicon layer, although not certain.

In general, the refractory metal according to the method of the present invention may be any metal capable of forming metal silicides. For this purpose, "refractory metals" are defined to include (but not limited to) Mo, V, W, Ta, Nb, or Cr, and Ta and Nb provide the most significant effect. The metals can be any of the placement methods disclosed herein, but ion implantation and deposition of Mo, Ta, and / or Nb is the preferred method.

Referring now to the silicided treatment described above in more detail, several methods may be used to dispose refractory metals. In general, these placement methods place refractory metal atoms on top surface 12 or in a few angstroms from the top surface. Refractory metal atoms closest to the silicon interface are the most active, but other, further atoms are not excluded from the sense used in the vicinity. For example, atoms located within about 2 Angstroms (ie about 0.2 nm) at the surface may be most active. The first method of placing refractory metals is ion implantation in an amount of about 10 ¹² to 5X10 ¹⁴ atoms / cm 2, and even more preferably ion implantation in an amount of about 10 ¹³ to 10 ¹⁴ atoms / cm 2. Preferred ion implantation energies for these cases are about 15 to 90 KeV.

One method of implanting refractory metals involves the use of an arc chamber of a commercially available ion implantation system. Since arc chambers are usually made of refractory metals (e.g., molybdenum, niobium, tantalum or tungsten) or otherwise lined with refractory metals, one method of ion implanting these metals is to employ the arc chamber as a source of metal to be implanted. Is achieved using. The type of metal to be implanted is selected by appropriately changing the arc chamber material and by adjusting the magnetic analyzer to select the desired atomic mass unit (AMU) of the metal type based on known isotopes of the desired type. For example, a suitable setting is 98 AMU for Mo and 184 AMU for W. Since W is also a conventional filament material in the ion source filament of the ion implantation tool, alternatively, W can be injected differently by adjusting the analyzer magnet to 184 AMU for a single ionized W or 92 AMU for a double ionized W. . The amount and energy selected for a particular metal type are limited by the capacity of the ion implantation system and the time taken to perform the implantation.

Referring to a particular Mo injection case, after the Mo arc chamber is installed in the injection system, 1 boron trifluorine source gas (BF ₃ ) is introduced into the arc chamber. The ionized BF ₃ acts to volatilize the molybdenum from the arc chamber to provide a suitable Mo ion (98Mo +) beam current of about 200 kW with an implantation energy of at least about 45 KeV. Since arc chambers are sometimes coated with other materials during use in other conventional applications, it is desirable to use clean chambers or new source chambers to obtain Mo ion beam currents.

When injecting Mo atoms under the above conditions (i.e., energy of 45 KeV), it is determined that the largest concentration of Mo atoms corresponding to a maximum Mo concentration of about 10 ¹⁹ atoms / cm 3 occurs at a depth of about 30 nm in the silicon layer. It became. However, as explained above, the concentration of Mo atoms of most interest is at the surface. When using the optional annealing step described above, SIMS data indicated that the concentration of Mo atoms at the surface was about 5 × 10 ¹⁸ atoms / cm 3. It is expected that the surface concentration of the refractory metal at the silicon interface may be preferably greater than about 10 ¹⁷ atoms / cm 3.

Alternatively, the refractory metal is disposed on the surface of the silicon layer by depositing so-called metal pellets. This may be done by e-beam deposition or by resistive heating (eg placing the pellets in a crucible that is heated by a large current). When using the vapor deposition method, it is important that the thickness of the refractory metal is not too large. For example, the thickness of the Mo layer disposed on the silicon layer is preferably less than about 2.0 nm. This is not an absolute maximum thickness, but it was observed that the silicide film peeled off when the thickness of the Mo layer increased to 2.0 nm or more. More preferably, a Mo thickness of about 0.01 to 1.5 nm is used. Preferred thicknesses for other metals may vary somewhat.

It is sometimes difficult to control the deposition rate when depositing a small thickness of refractory metal to form on a silicon layer. As a result, the shutter is positioned above the deposition metal source chamber to contain the refractory metal until ready for placement on silicon in one deposition method. Then, after the chamber is opened, it closes very quickly (called "flash" deposition) to provide a thin layer of refractory metal over the silicon layer. Other deposition methods can be used to better control the deposition rate.

As another method for the deposition of refractory metals, the refractory metal may instead be placed on a silicon layer by sputtering to a thickness similar to that described previously for the deposition method. Those skilled in the art will understand the modifications used by the sputtering method.

In addition to the above method, the refractory metal may be disposed on the silicon layer by exposing the surface of the silicon layer to a solution containing ions of the refractory metal. In a preferred manner, this solution is aqueous and may comprise dilute acid such as HCl or nitric acid.

For the TiSi ₂ method above, the wafer is optionally annealed after the refractory metal placement step and before the titanium layer deposition step. Preferably, this annealing step is performed at a wafer temperature of at least about 900 ° C, more preferably between about 900 ° C and 1000 ° C.

4 to 9 show experimental data for several TiSi ₂ films formed in accordance with the present invention. 4 is a graph of sheet resistance vs. sputtered titanium thickness of a titanium silicide layer for treatment with refractory metals and without treatment with refractory metals in accordance with the present invention. The data indicated as a standard film was formed without using refractory metals and without performing a second phase transition annealing. TiSi ₂ films corresponding to data points for W and data for Mo were formed by annealing at 600 ° C. for 30 minutes in an N ₂ atmosphere on (100) single crystal silicon according to the present invention. Optionally, RTA annealing at 1000 ° C. for 5 seconds was performed after injection of the refractory metal (performed for both W and Mo). Optional annealing is required when the TiSi ₂ film is formed at about 600 ° C., but is not required for a formation temperature of about 700 ° C. The sheet resistance of each film is represented by data points in the graph.

5 to 7 show in-situ the sheet resistance of the titanium silicide layer formed for the case of treatment with a refractory metal formed by vapor deposition according to the present invention and for treatment without a refractory metal. ) Scanning resistance graph. These measurements were made by continuously positioning the probe at four points in the furnace during the formation of the TiSi ₂ film. The refractory metals used in FIGS. 5-7 were disposed by the "flash" deposition method described above. 8 is an in-situ scanning resistance graph for a TiSi ₂ film using refractory metal formed by implantation rather than by deposition. Common conditions for FIGS. 5-8 include forming silicide films from about 57.5 nm thick Ti layers previously deposited over about 300 nm polysilicon layers. Each silicide film was formed by gradually increasing the temperature of about 15 ° C. per minute.

Referring now to FIG. 5, curve 30 shows the sheet resistance trend for a titanium silicide film formed without the use of refractory metals. Curve 30 shows a known expected increase in resistance due to mixing at point 32 and records the maximum resistance at about 500 ° C. Above about 500 ° C., its resistance drops as indicated by arrow 34. The TiSi ₂ film formed when the temperature moves from about 500 ° C. to 700 ° C. is substantially C49 phase. At about 700 ° C., the curve 30 flattens and enters the so-called “knee” at point 36, where the resistance is substantially constant with increasing temperature. This "knee" is the result of the silicide film not converting from C49 to C54 until higher temperatures are reached. In contrast to curve 30, curve 40 shows the resistance to the silicide film formed after disposing about 0.015 nm of Mo in accordance with the present invention. The operation is similar, only the " knee portion " previously observed for curve 30 substantially does not exist for curve 40 (see point 42). The absence of this knee portion means that the C54 phase of TiSi ₂ did not pass through the C49 phase but formed directly to a substantial extent during silicideation.

Curve 50 in FIG. 6 shows the sheet resistance trend for the silicide film formed when a Ta layer of about 0.015 nm is disposed by flash deposition in accordance with the present invention. As with the curve 40 of FIG. 5, no significant knee portion is observed during the formation of the C54 phase of TiSi ₂ . Curve 60 in FIG. 7 shows the sheet resistance versus temperature for a TiSi ₂ film formed using W of about 0.015 nm in accordance with the present invention. Curves 30 and 40 are shown relative to curve 60. Again, there is no significant knee portion for curve 60, and the C54 phase was formed at temperatures substantially below about 700 ° C.

8 is an in-situ scanning resistance graph showing the sheet resistance of a titanium silicide layer formed using an ion implanted refractory metal in accordance with the present invention. Curve 70 is for a control silicide film formed without refractory metal for comparison purposes, and curve 80 shows that Mo is ion implanted (with an amount of 10 ¹⁴ atoms / cm 2 and an injection energy of 45 KeV) before depositing Ti. For the TiSi ₂ film formed. After ion implantation of Mo, an annealing step was performed at 900 ° C. for 10 minutes before depositing Ti. As with the conventional curve 30 described above, the curve 70 represents the knee portion at point 72, but not the curve 80. The absence of the knee portion in curve 80 indicates that the C54 phase of TiSi ₂ was formed at a temperature substantially below about 700 ° C.

FIG. 9 is a bar graph of titanium silicide line resistance measured for Mo and without implants in accordance with the present invention.

In addition to the data shown in Figures 4-9 above, there is further evidence that the C49 phase is virtually omitted in the silicideation according to the present invention. Optical micrographs on the C54 of the titanium silicide layer formed according to the present invention showed much smaller particle sizes than in the conventional case without using refractory metals. This supports the fact that the nucleation energy barrier on C54 was significantly reduced by the method of the present invention. This fact is most important in VLSI circuits where the line width is smaller than the particle size of the C54 phase formed when using conventional methods.

While the method according to the invention described above is clearly robust, there are some caveats in using it. First, heating cycles above 700 ° C. for extended periods of time should be avoided to avoid possible silicide instability problems when using the present invention. Second, if the thickness of the refractory metal layer is too large, cracking of the silicide may result.

Another advantage of the present invention is that it does not form an amorphous silicon layer on the top surface of the silicon layer. Specifically, any amorphous silicon that may be present by an optional annealing step is removed when using ion implantation to place refractory metals. This optional annealing is not necessary in other placement methods to prevent amorphous silicon. The presence of amorphous silicon is associated with junction leakage failures and should be avoided.

In another embodiment of the present invention, the method includes depositing a titanium alloy layer containing a refractory metal over a silicon layer and heating the wafer to a temperature sufficient to substantially form titanium silicide on C54 from the titanium alloy layer. The method can form a metal silicide layer on a silicon layer on a semiconductor wafer, where the phase transition temperature of the titanium alloy is lowered by the presence of the refractory metal. Preferably the temperature at which the C54 phase is formed is less than about 700 ° C.

1 and 10, a titanium alloy layer 30 may be deposited on the surface of the silicon substrate 10. The silicon substrate 10 may be directly over other electronic devices or may form part of such devices, but aspects of these semiconductor devices have not been shown to more clearly depict and explain aspects in accordance with the present invention. The term "electronic components" as used herein is intended to include both passive and active electronic components. The titanium alloy layer may comprise titanium and a refractory metal of up to 20 atom sets, such as Ta, Nb, Mo, W, V, Cr or a combination thereof. Ta and Nb are preferred refractory metals. In addition to the refractory metals, Si may also be included in the titanium alloy layer. Those skilled in the art will appreciate that embodiments in which silicon is added into a titanium alloy layer may prohibit the use of self-aligned silicide treatment techniques. In addition to the refractory metal, the titanium alloy layer may also comprise other elements from the IIIA, IVA, VA and VIA groups, including B, C, N, O, Al, P, In, Sb and As in the periodic table. ⅦA elements, such as F, should be avoided and such elements, if present, should be present at levels sufficiently below the atomic percentage of the refractory metal.

The titanium alloy layer can be disposed by any of several techniques known in the art. Titanium and refractory metals can be deposited from different sources or titanium sources that also contain small amounts of refractory metal such that the atomic percent of the refractory metal layer in the resulting layer is less than 20 atomic percent, preferably 1 to 15 atomic percent. have. Titanium alloys may be deposited on silicon substrates by physical vapor deposition (PVD) treatment of sputtering. For example, a suitable sputtering target of titanium alloy is provided to have the desired atomic percent refractory metal when the film is deposited on a silicon substrate. Alternatively, PVD treatment of deposition can be used to place the titanium alloy, in which case titanium and refractory metal are deposited in appropriate proportions from two different sources to obtain the desired atomic percent refractory metal. The treatments described above, as well as any of the other processes known in the art for depositing titanium or metal silicides, can be used to dispose a titanium alloy layer over a silicon substrate. The titanium alloy layer may be disposed 10 to 200 nm thick, preferably 10 to 60 nm thick.

Referring to FIGS. 10 and 11, the titanium alloy layer 30 may then be heated to a temperature sufficient to form a titanium silicide layer 32 on substantially C54. The phrase “substantially C54 phase” as used herein means a titanium silicide layer comprising at least 50 weight percent of the C54 phase in which the C54 phase has dominant resistance properties. As will be described in more detail herein below, an advantage of the present invention is that the phase transition annealing step can be eliminated by avoiding the need for a second phase "conversion annealing" as the C54 phase is formed virtually directly during the titanium silicide formation step. Is there. Moreover, the presence of refractory metals in titanium silicide substantially increases the damage temperature by heat, ie the temperature at which undesirable transitions such as agglomeration may occur. Increasing the thermal damage temperature has the advantage of creating a larger treatment window.

As shown in FIG. 12, the in-situ scanning resistance plot shows that the formation temperature of the titanium silicide containing the refractory metal was reduced compared to the pure titanium silicide formation temperature. This figure also shows an increase in thermal stability when refractory metals are used. The titanium layers referenced in FIG. 12 were each heated to a temperature of 1050 ° C. (15 ° C. increase per minute) in He atmosphere.

FIG. 13 shows the resistance as a function of the atomic percent of refractory metal present in the titanium alloy used to form titanium silicide. The titanium alloy was annealed up to 900 ° C. (15 ° C. increase per minute) in He atmosphere. The “C49 TiSi ₂ ” and “C54 TiSi ₂ ” regions surrounded by dotted lines in the figure indicate standard resistance ranges for C49 and C54 phase TiSi ₂ formed from pure TiSi ₂ . This figure shows that the annealed titanium alloy of the present invention having 1 to 20 atomic percent refractory metal has a much lower resistance than TiSi _{2 on} C49. However, titanium alloys formed with Mo exhibit reduced resistance at concentrations below about 5 atomic percent. 14 also shows the resistance as a function of the atomic percentage of the refractory metal present in the titanium alloy used to form the titanium silicide. However, in FIG. 14, annealing was performed on a titanium alloy layer of 30 to 50 nm at 700 ° C. (maintained at 35 ° C./S for 60 seconds) in an N ₂ atmosphere. 13 and 14 show that titanium silicides formed from titanium alloys containing Ta, Nb, Mo, W and V, respectively, exhibit much lower resistance than titanium silicides on C49. 15 also shows the C54 formation temperature as a function of the atomic percentage of refractory metal added to the titanium alloy. 14 and 15 show that the annealed titanium alloy of the present invention has a resistance comparable to that of TiSi ₂ on C54 formed from pure TiSi ₂ and achieves low resistance at much lower annealing temperatures.

The treatment according to the invention can be easily integrated into current semiconductor fabrication techniques using a titanium silicide layer formed from pure titanium. For example, referring to FIG. 16, a CMOS using a titanium silicide layer 50 according to the present invention, a drain contact 54 and a gate contact 56 as a source 52 for an N-MOSFET and a P-MOSFET. Transistors are shown. However, the titanium silicides of the present invention may also be used with fabrication processing techniques for many other electronic components.

Titanium alloys, including titanium and refractory metals, may be deposited over devices comprising polysilicon layer 58, and may be highly doped in source 52 and drain 54 regions like pure titanium in current self-aligned silicide applications. It may be deposited on silicon. After deposition, the titanium alloy may first be heated in a “form annealing” process to form titanium silicide. Since titanium silicide on C54 can be formed from a titanium alloy at a much lower temperature than other silicides, the formation annealing process may actually form the titanium silicide on C54 phase layer. Thus, in many cases the need for conversion annealing can be completely eliminated when using titanium alloys as the titanium silicide on C54 phase is substantially formed by the first cold annealing. However, depending on the formation annealing temperature and the geometry of the device, some applications may still require conversion annealing.

The titanium silicide may then be selectively etched according to current processing techniques to remove unreacted portions of the titanium alloy layer, whether C49 phase, C54 phase, or a mixture of the two. This treatment is typically “salicide” because regions of the titanium alloy that are not located on the silicon substrate may be “self aligned” by etching to selectively etch the metal against the silicide without reacting to form silicide. Or self-aligned silicide treatment. After etching, titanium silicide on C49 or titanium silicide with mixed phases on C49 and C54 may be subjected to a second annealing, ie, a “conversion annealing” that transfers the silicide to the desired substantially C54 phase titanium silicide. Even in this case, however, even where conversion annealing is necessary or desirable, conversion annealing can be performed at significantly lower temperatures, thus maintaining the available heat burden. After formation of the low resistance titanium silicide layer of the present invention, the electronic components and desired interconnects can be completed using well known semiconductor fabrication techniques.

In the case of pure titanium silicide, the forming annealing forms titanium silicide on C49. This formation annealing is necessarily carried out at low temperatures to avoid the formation of silicides on unwanted areas of the device, which is a common problem referred to as bridging, and therefore cannot form a C54 phase from pure TiSi ₂ . For example, in the device of FIG. 16 subject to the temperature needed to form titanium silicide on C54 from pure titanium prior to selective etching, silicide may be formed over oxide spacers 62 in the unwanted portion of the titanium layer. The formation of the silicide on the spacer 62 electrically connects the gate 59 and the region of the source 52 or drain 54 to short the device. Therefore, conventional silicide treatment techniques have to etch unwanted portions of titanium using a second high temperature annealing, i.e., conversion annealing, and then convert the C49 phase titanium silicide to the desired low resistance C54 phase. Therefore, it is particularly important that the low resistance titanium silicide layer, which is substantially C54 phase, is formed by heating the device using a titanium alloy with a single formation annealing or with conversion annealing at temperatures much lower than 900 ° C. As described above, forming the C54 phase from the titanium alloy is advantageous in that it reduces the movement of the dopant material forming the predefined doped regions 58 and 60 of the individual electronic components.

While the invention has been described in detail above, it is intended that the invention not be limited to the particular form disclosed herein, but include modifications and equivalents as may be within the spirit and scope of the invention as defined by the appended claims. It is intended.

An advantage of the present invention is that the phase transition annealing step is eliminated. For example, for titanium silicide, the desired C54 phase is formed directly during the titanium silicide formation step. No second phase transition annealing is needed to transfer TiSi ₂ from C49 to C54. In addition, since the titanium silicide film is exposed to lower processing temperatures, agglomeration is essentially eliminated. As another advantage of the present invention, the ability to control the final microstructure of the C54 phase of the silicide film is improved, and the particle size of the C54 phase particles can be smaller than the critical dimension of the device being manufactured.

Claims (21)

A method of forming a titanium silicide layer on a silicon substrate of a semiconductor device, the method comprising: ① placing a titanium alloy layer comprising 1 to 20 atomic percent refractory metal on the silicon substrate; ② heating the titanium alloy to a temperature sufficient to form a titanium silicide on substantially C54 phase; Titanium silicide layer formation method. The method of claim 1, Wherein said temperature is less than about 700 ° C. The method of claim 1, And the substrate is heated to a temperature sufficient to completely transition the titanium alloy layer to titanium silicide on C54. The method of claim 1, And wherein said refractory metal comprises at least one element from the group consisting of Ta, Nb, W, V and Cr. The method of claim 2, Wherein said titanium alloy comprises 1 to 15 atomic percent refractory metal. The method of claim 5, Wherein said refractory metal comprises a refractory metal selected from the group consisting of Ta and Nb. The method of claim 2, Wherein said titanium alloy comprises titanium, silicon, and a refractory metal. The method of claim 1, And the titanium alloy layer is disposed on the silicon substrate in a thickness of 10 to 60 nm. The method of claim 1, Wherein said silicon substrate is selected from the group consisting of monocrystalline silicon, polycrystalline silicon, amorphous silicon, and silicon germanium alloy. The method of claim 1, Wherein said silicon substrate is selected from the group consisting of a silicon on insulator (SOI) containing an N-type dopant and a SOI containing a P-type dopant. The method of claim 1, And the titanium alloy is deposited on the silicon substrate by physical vapor deposition. The method of claim 1, And the titanium alloy is deposited on the silicon substrate by chemical vapor deposition. The method of claim 1, Wherein said titanium alloy comprises from 1 to about 5 atomic percent Mo. A method of forming a titanium silicide layer in a semiconductor device, the method comprising: ① depositing a 10-200 nm thick titanium alloy layer over the semiconductor device—the titanium alloy comprises 1 to 15 atomic percent refractory metal and the semiconductor device comprises a plurality of electronic devices having exposed silicon surfaces -Wow, (B) heating the titanium alloy layer to a temperature sufficient to substantially form a C54 phase titanium silicide in the titanium alloy layer on the silicon surface, wherein the temperature is less than about 700 ° C .; ③ etching the unreacted portion of the titanium alloy layer Titanium silicide layer forming method comprising a. A method of forming a titanium silicide layer in a semiconductor device, the method comprising: ① depositing a 10-200 nm thick titanium alloy layer over the semiconductor device—the titanium alloy comprises 1 to 15 atomic percent refractory metal, the semiconductor device comprising a plurality of electronic devices having an exposed silicon surface Hamm (B) heating the titanium alloy layer to a degree sufficient for titanium silicide to form in the titanium alloy on the silicon surface; (3) etching the unreacted portion of the titanium alloy; ④ heating the titanium silicide to a temperature sufficient to substantially form titanium silicide on C54 phase, wherein the temperature is less than about 700 ° C. Titanium silicide layer forming method comprising a. A semiconductor device having a titanium silicide layer, ① with silicon layer, A titanium silicide layer on the silicon layer, the titanium silicide layer substantially comprising titanium silicide on C54 and a second refractory metal of 1 to 20 atomic percent, wherein the thickness of the titanium silicide layer is 10-200 nm. Semiconductor device comprising a. The method of claim 16, Wherein said silicon layer is selected from the group consisting of monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium alloy, SOI containing an N-type dopant, and SOI containing a P-type dopant. The method of claim 16, And the second refractory metal is selected from the group consisting of at least one of Ta, Nb, W, V or Cr. The method of claim 16, Wherein said titanium silicide layer comprises 1 to 15 atomic percent of a second refractory metal. The method of claim 17, And the second refractory metal is selected from the group consisting of Ta and Nb. The method of claim 16, The second refractory metal includes Mo, Wherein said titanium silicide layer comprises 1 to 5 atomic percent Mo.

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