TW418464B - Low temperature formation of low resistivity titanium silicide - Google Patents

Abstract

Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900 DEG C, and more preferably between about 600-700 DEG C.

Description

Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives A7 B7 V. Description of the Invention (1) Related applications have not been made before and after this application is part of the US Patent Application Serial No. 08 / 145,921. The invention relates to integrated circuit devices, and more particularly, to a method for forming a silicon silicide layer on the integrated circuit device and covering the silicon layer, in which the phase transition temperature of titanium silicide has been used. Pyrophoric metal is reduced by beta. The previous technology of titanium silicide has become the most widely used silicide in the VLSI industry for self-aligned silicide applications because of its low resistivity, automatic alignment capability, and relatively good performance. Combined properties of thermal stability. Although TiSi2 has some advantages over other silicides, in fact, it is a polymorphic material that presents other problems when used. To be clear, in typical use, TiSi2 has 12 orthorhombic bottom core phases (referred to as the C49 phase in this industry) with a unit cell of 12 elements and an electrical resistivity of about 60-90 microohm-cm. Or, there is a more thermodynamically favorable oblique aspect cardiac phase (called C54 phase) with 24 atoms per unit cell and a resistivity of about 19-70 microohm-cm. When using generally accepted processing conditions to form titanium silicide, the less desirable higher resistivity C49 phase is formed first. A second high temperature tempering step is required in order to obtain a lower resistivity of 054 phase. This second step is disadvantageous because it may have an adverse effect on silicide and other integrated circuit components, especially at smaller line widths. For example, the increasing use of dual-doped polysilicon gate structures in some devices has increased their sensitivity to additional thermal cycling, as required by the second tempering step. Nitrided sand peeling and paper size are in accordance with Chinese National Standard (CNS) A4 specification (2〗 0X297 mm) (Please read the note on the back < 11 ^ before filling out this page) Ministry of Agriculture and Customs Central Standard Printed by the bureau ’s consumer cooperative, 8 in "A7 ___ B7 _____ ~ ---- '· ,, _____ ______ _____ _ V. Description of the invention (2) Cracking has also been accompanied by a second tempering step. Generally accepted The combination of processing conditions used to form titanium silicide includes: (1) pre-cleaning, (2) titanium deposition, (3) silicide formation at temperatures below about 70 ° C, selective etching, and (5 ) Phase transformation and tempering at temperatures greater than about 700 ° C. This phase transformation and tempering system transforms the main C49 phase into the C54 phase. The initial formation temperature system is maintained below 700 ° C to reduce the bridging effect of the interstitial material above. To the minimum. The second transformation tempering is performed after any unreacted titanium has been selectively removed 'and is usually performed at a temperature above 50-200 ° C' to ensure complete conversion to C54. Phase to obtain the most controlled sheet resistance. However, when the device line width and silicide film When the degree continues to gradually decrease, it does become more desirable to dispense with the need for this second tempering step, as discussed further below. The generally accepted situation is that the C49 meeting will first form because it has A lower surface energy than the C54 phase. In other words, the higher surface energy of the C54 phase will cause a higher energy barrier to its formation. The second transformation tempering step used in the standard method described above is provided to overcome novel formation The surface is accompanied by a nucleation barrier and the additional thermal energy necessary to grow a newly formed C54 phase crystal structure. In VLSI applications, 'if the phase transition is suppressed or fails to occur uniformly, the circuit performance is found to be Degradation. In some higher-performance batteries, the RC delay with bad phase transition is typically about 51%. An important limitation on the C49 to C54 phase transition is a type called cohesion. Phenomenon. If the heat energy used to obtain this phase transition is too high, it will cause morphological degradation of sanded titanium. It is often referred to as cohesion. When the line width and sandy substance are used, this paper scale is applicable to China. Ladder standard (CNS > Λ4 specification (2 丨 0X297 mm) (please read the notes on the back ^^ before filling out this page) 砀 1. Order printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economy 4 \ & 464 A7 ______B7 V. Description of the invention (3) When the thickness of the film is reduced, the thermal energy required to achieve the C49 to C54 phase transition will increase, and the thermal energy level at which the silicide film starts to cohes will decrease. Therefore, 'About this phase transition, There is a shrinking processing window that makes program control and uniformity more difficult to achieve. Therefore 'an improved method is still needed to form the C54 phase of titanium silicide' without the need for Two high temperature tempering steps. Eliminating this second tempering step, or reducing the temperature necessary to transform the C49 phase of titanium silicide to the desired C54 phase, will reduce the problems associated with high temperature processing 'and the cohesion of the silicide film during phase transition tempering Limitations due to role. Summary of the Invention According to the principle of the present invention, a method for forming a metal silicide layer overlying a silicon layer on a semiconductor wafer is used to meet this demand, overcome the limitations of the prior art, and achieve other benefits. The method includes forming a titanium silicide layer on a silicon substrate of a semiconductor device, which includes: depositing a titanium alloy layer on the silicon substrate, wherein the titanium alloy contains 1 to 20 atomic percent of a refractory metal; and (2) heating the titanium alloy. A temperature sufficient to substantially form a C54 phase titanium silicide from the titanium alloy. This temperature may be lower than about 700 ° C »In one application of the above method, the titanium alloy may include 1 to 15 atomic percent of a refractory metal, and the refractory metal may include one or more including Ta,: 1 ^ ,: \ 1〇, 沢, ¥, and 0. This titanium alloy may include titanium, silicon, and a refractory metal; one example is TiSi2 and a refractory metal. The semiconductor substrate may be selected from monocrystalline silicon, polycrystalline silicon, amorphous silicon, and silicon-germanium alloys containing N-type doping. Insulating epitaxial silicon with insulating agent and Insulating epitaxial with P · type dopant -6 · Lai Thorn (CNS) (210X297 mm) for this paper ~ I --------- 0 ^- (Please read the precautions on the back before filling this page) Order_ 3¾¾: Visit 418464 A7 B7 V. Description of the invention (4) Silicon "This titanium alloy can be deposited on the silicon substrate by physical vapor deposition or chemical vapor deposition. Top >> Another aspect of the present invention is a semiconductor device including a C54 phase titanium silicide layer, including: (1) a silicon layer; and (2) a layer of titanium silicide on the silicon layer, wherein the layer of titanium silicide It contains substantially C54 phase titanium silicide and 1 to 20 atomic percent of refractory metal. Another aspect of the semiconductor device of the present invention includes a silicon layer selected from the group consisting of monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium alloy, insulating epitaxial silicon with N-type dopants, and P-type doping. Insulating Silicon on the Surface of the Agent "The semiconductor device of the present invention may include a titanium silicide layer containing 1 to 15 atomic percent of a refractory metal and having a thickness between 10 and 200 nm. Brief description of the attached circle 1-3 is a cross-sectional view illustrating the formation of the C54 phase of titanium silicide according to one aspect of the present invention. Fig. 4 is a graph of the resistance of the titanium silicide sheet flakes against the thickness of the sputtered titanium in accordance with the present invention with respect to several treatments with and without the use of refractory metals. Figures 5-8 are in-situ scanning resistance charts illustrating the sheet resistance of the titanium silicide layer formed in accordance with the present invention with respect to several treatments with and without the use of vaporized or implanted pyrometal.囷 9 is a histogram of measured resistance of titanium silicide lines with and without Mo ion implants according to the present invention. "Figures 10 and 11 are cross-sectional side views illustrating the formation of C54 phase titanium silicide according to one aspect of the present invention. . Figure 12 depicts the formation of silicified paper from pure Ti, Ti (button) alloy, and Ti (niobium) alloy. The paper uses the Chinese National Standard (CIVS) specification (210X297 mm). 0 ut ml {Please read the note on the back first (F-item, please fill out this page again.) Staff Consumer Cooperatives of the Central Bureau of the Ministry of Economic Affairs of the People's Republic of China printed T-^-^ .------ Order ------- J --- 1 ------ -Printed by the Consumer Cooperative of the Central Sample Rate Bureau of the Ministry of Economic Affairs

/ Π846 A A7 ______ B7 " --------- V. Explanation of the invention (5) Qin Zhi's normalized sheet resistance vs. temperature chart β 圏 13 is a graph describing the resistivity of the titanium silicide layer tempered at 900 ° C against fire resistance Graph of metal atomic percentage.圏 14 is a graph of the resistivity of the titanium silicide layer tempered at 70 ° C against the atomic percentage of refractory metal. 囷 15 is a graph describing the formation temperature of C54 titanium silicide vs. atomic percentage of refractory metal. A cross-sectional side view of a part of a semiconductor device with a coefficient of titanium silicide. DESCRIPTION OF THE INVENTION According to one aspect of the present invention, a refractory metal is arranged on the surface adjacent to the silicon layer, and a titanium metal layer (to be used later to form Titanium silicide) is deposited to cover the refractory metal, and the wafer is heated to a temperature sufficient to form a silicified beverage. In a second embodiment, the titanium metal layer may also be doped with silicon, such as in known polysilicides. The situation in the method ° When the drinking metal layer is broken, the final titanium silicide is after depositing Ti · silicon alloy (which may be stoichiometric in some cases), and by heating the wafer to a temperature sufficient to obtain the desired solid phase, Obtained. In addition to Si, the precursor metal layer may be doped with other elements from the πβ, melons '^' ▽ and VIII groups of the periodic table, including 3, €,; ^, 〇, meaning,?, S, Zn, Ga, G e, As, Se, Cd, In, Sn, Sb, Te, Hg, Tl, Pb, and Bi. The refractory metal is preferably a metal capable of forming a metal silicide, and the concentration of the refractory metal on the surface of the broken layer is preferred. More than about 1017 atoms / cubic centimeter-8- This paper size is applicable to the Central Solid State Standard (CNS) Α4 size (210X297 mm) ^ 1- n ^^ 1-1 ^ 1 ^^ 1 I ί Please read the back first Please pay attention to the item (please fill in this page) Order V}-418464 A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (β. This refractory metal can be 1 ^ 〇, double, 13, 1 ^) , ¥, or (: 1 '. The silicon layer may be monocrystalline or polycrystalline, but is preferably polycrystalline. The heating step used to form the silicide is at a temperature below about 700 ° C, and more The best line is between about 600-700eC. There are several research ways to configure the refractory metal that can be used. Generally, 'the configuration method is to place refractory metal atoms on the surface within or within several angstroms, for example Within about 2 Angstroms. The first research approach to deploy refractory metals is by ion implantation, using about 1012 to 5xl014 atoms / cm2. Dose, and more preferably a dose of about 1013 to 1014 atoms per square centimeter. The preferred implantation energy is about 15 to 90 KeV. In another research approach, 'refractory metals are obtained by, for example, evaporation of metal pellets. It is disposed on the surface of the silicon layer. The refractory metal may also be disposed by sputtering or by exposing the surface of the silicon layer to a solution containing refractory metal ions. For example, the solution may be a dilute acid solution containing HC1 or nitric acid. In all of the above research methods, except for the implantation method, the thickness of the refractory metal layer disposed on the silicon surface is preferably less than about 2.0 nm, and more preferably about 0.01 to 1.5 nm. Temper the wafer as appropriate after the step of disposing the refractory metal and before the step of depositing the precursor metal layer. This tempering step is preferably performed at a wafer temperature of at least about 900 ° C, and more preferably between about 900 and 1000 ° C. In one approach, this tempering was performed using rapid thermal tempering (RTA) for at least about 5 seconds. Alternatively, tempering in the middle can be used for at least about 10 minutes. In another research approach of the present invention, a titanium silicide layer is formed to cover the silicon layer on the semiconductor wafer. According to this research approach, the refractory metal system is arranged close to the surface of the silicon layer, and a titanium layer is deposited to cover the refractory metal. The 9-sheet paper size is in accordance with the Chinese National Standard (CNS) A4 size (210X297 mm) nn * ni— I — ^ M. I (please read the precautions on the reverse side before filling out this page), 1T-418464 No. 86115438 Patent Application Chinese Manual Correction Page (September 89) A7 Xiu Fen I really: V. Description of the invention (B7ψψ ^ Amendment: The Ministry of Economic Affairs of the Ministry of Economic Affairs and the Central Bureau of Commerce, which are being referred to by the Central Government Bureau %%, i. The printed wafers of the consumer cooperative are heated to a temperature sufficient to form at least part of the silicide layer from the titanium layer. The titanium silicide layer formed during the step is preferably a C54 phase that is substantially π TiSi2. The titanium layer is preferably deposited to a thickness of about 25_57 5 nm, and the TiSis layer is at a temperature lower than about 70 (rc). And more preferably formed under about 600-700. And 'refractory metal is preferably 1 ^ 〇, Shi, 1 ^, Can, 乂 or C r' iL is preferably by ion implantation or metal Evaporation to configure. M0, Ta & Nb have been found to give the best As a result, even if it is relative to. The implantation is preferably performed at an implantation dose of about 103 to 1014 atoms / cm 2. It is preferable to perform the optional tempering step described above. In an alternative embodiment according to the present invention, the metal silicide is a method including a step of depositing a titanium layer on the silicon layer to cover the layer on the silicon layer on the semiconductor wafer. Formation, in which the titanium layer contains a small amount of refractory metal, and the wafer is heated to a temperature sufficient to form silicic acid. The phase transition temperature of titanium silicide from C49 to C54 is reduced because the refractory metal is present on the surface of the silicon layer. Titanium It is preferably deposited during the same deposition process as the refractory metal, and the atomic percentage of the refractory metal layer in the source is less than about 20 atomic%. It is preferably between 1 and 15 atomic%. According to alternative embodiments In a preferred research approach, the convergence layer is deposited from a titanium source that also contains a small amount of refractory metal. Then, the wafer is heated to a temperature sufficient to form a fragmented C54 phase on the substrate. This temperature is better Below about 700 ° C and the atomic percentage of the refractory metal is below about 20 atomic percent. The advantage of the present invention is to eliminate the phase transition tempering step. For example, regarding the C 5 4 phase system required by Shi Xihua Qin ' Substantially directly during the titanium silicide formation step-10- This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) (please read the notes on the back before filling this page) Bureau employee consumer cooperatives printed A7 B7 5. The invention description (8) was formed. No second phase transition tempering is needed to change TiSi2 from C49 to C54 phase. Moreover, the cohesion is basically eliminated because the titanium silicide film is exposed to a lower processing temperature. Other advantages of the present invention are the improved ability to control the microstructure of the C54 phase of the final silicide film, and the small grain size of the C54 phase grains can be lower than the critical size of the device being manufactured. In a specific embodiment, the refractory metal is disposed adjacent to the surface of the silicon layer, and the titanium layer is deposited on the surface of the refractory metal and the silicon. The wafer is then heated to a temperature of about 600 to 700 eC for a period of time sufficient to form the C54 phase of the silicified prostitute. More specifically, referring to FIG. 1, a silicon layer 10 is provided, which may be a single crystal silicon wafer (100) or polycrystalline silicon. The silicon layer 10 may be, for example, a polycrystalline N or P-type line or a monocrystalline N or P-type region. The refractory metal is arranged on or near the top surface 12 of the silicon layer 10, depending in part on the way the metal is arranged. The Xianxin refractory metal is used to reduce the surface energy barrier of the C54 phase forming TiSi2. Therefore, the presence of refractory metal on or near the surface will promote the formation of ^^ phase. The Xianxin refractory metal-silicon alloy is formed near the top surface 12. It is not known whether it is a metal-dream complex or a metal hard compound. In general, a portion of the configured refractory metal should be on or within a few angstroms of the top surface. Of course, the correct configuration of the refractory metal will depend on the configuration method. However, for the purpose of this application, each of the arrangements described herein refers to the placement of refractory metal atoms next to the silicon surface. Now referring to the circle 2 'fortune fire metal 14 series, the surface immediately adjacent to the broken layer 10 is shown. First, it should be understood that FIG. 2 is for illustrative purposes only, and refractory metal 14 may not necessarily cover all top surfaces 12. Secondly, it should be noted that the distribution of refractory metal 14 -11-This paper size is in accordance with China National Standard (CNS) A4 size (210X297 mm) (Please read the precautions on the back before filling in this page}

-l1T 4184 6 4 Α7 Β7 V. Description of the invention (9) will also change according to the configuration method < • For example, if the refractory metal 14 is configured by ion implantation, most of the metal will be lower than the top surface 12. On the other hand, if this metal is configured by evaporation, most of the metal will be placed on the top surface 12 instead of β below it. Ion implantation and evaporation are used as two research approaches. , Is the refractory metal concentration next to the top surface 12. After the refractory metal 14 is configured, the titanium layer 16 is then deposited on the refractory metal 14 by, for example, sputtering or evaporation. For example, a thickness of 25 to 57.5 nm is used, but those skilled in the art will understand that larger and smaller Thickness can also be used. The top surface 12 is not explicitly shown in Fig. 2, as its position will vary depending on the configuration of the refractory metal used. In addition to sputtering or evaporation, the titanium layer 16 may be deposited on the refractory metal 14 by chemical vapor deposition. Furthermore, when deposited by one of these methods, an alloy layer containing Ti and Si may be deposited instead of the basic titanium layer. This alloy may be stoichiometric TiSh, but this is not required, and the Ti_a alloy may be rich or depleted in its silicon composition. When depositing a Ti-Si alloy, the method according to the present invention is substantially similar to that described herein. Those skilled in the art will understand any needed corrections. As used in this article, the deposition of a titanium layer may alternatively refer to the deposition of a 鈇 · broken alloy layer. Β Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ---- 1--i — (Please read the Note: Please fill in this page again.) In Figure 3, the TiSi2 film 18 has been formed on the silicon layer 10 by heating the dream layer 10 to about 600 and 70 (temperature between TC, which is enough to form the Ti54 C54 phase). Period. This period usually ranges from about 20 seconds to RTA to about 20 minutes of tempering in the conventional finish. According to the method of the present invention, the 5% thin film formed does not substantially pass the C49 phase, but mainly Directly reach phase C54. This is due to the reduced surface energy barrier. -12 This paper size is applicable to China Standards Standard (CNS) 8-4 (2) 0297 mm A7 B7 August 8 418464 No. 86U5438 Revised page of the Chinese specification of the patent application (September 89) 5. Description of the invention (10) It has been found that an optional tempering step is beneficial to further promote the formation of the c54 phase, especially when compared with At low temperatures, such as when sand formation occurs below about c. It is performed after the hot metal 14 is configured and before the Ti layer 16 is deposited. In general, this tempering is performed at a wafer temperature of at least about 900 C, and more preferably 900-1000 t: When using RTA, it lasts for at least about 5 seconds, and when using a conventional quartz furnace, it is usually about 10-30 knife clocks. The preferred tempering is in a ladle, in a% environment, at about 900 ° ; > The temperature lasted about 10 minutes. Generally speaking, this selection of tempering can further promote the formation of refractory metal-silicon alloy on the surface of the silicon layer, but this is not certain. Generally, $, according to the method of the present invention The refractory metal may be any metal which is sufficient to form a metal silicide. For the purpose of this application, "refractory metal" is intended to include (non-limiting) the following preferred metals: M0, v, W, Ta, Nb or Cr, Ta and Nb provide the most significant effect. It is believed that the above metals will usually work in any of the configurations disclosed in this article, but the ion implantation and evaporation of Mo, Ta and / or Nb is Better research approach. Now discuss the above silicification method in more detail. There are several research approaches. It is used to configure the refractory metal that can be used. Generally speaking, these configuration methods place the refractory metal atoms on the top surface or within several angstroms. The refractory metal atoms closest to the silicon interface are the most Active, but other distant atoms are not excluded from the immediate meaning used herein. For example, atoms within about 2 angstroms (meaning about 0.2 nanometers) of this surface may be most ear-active. The first research approach to deploy refractory metals was by ion implantation, using a dose of about 10 12 to 5 X 1 0 1 4 atoms / cm 2, and this paper size is applicable to China 圉Standard (CNS) A4 (210X297 mm) — mV m · ftn l ^ i (Please read the notes on the back before filling out this page] Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, 418464 A7 B7 ____ V. Description of the invention (n) More preferably, a dose of about 1313 to ίο 14 atoms / cm². The preferred implantation energy for these cases is about 15 to 卯 KeV. One method of implanting refractory metal involves using an arc chamber using a commercially available ion implantation system. Since arc chambers are usually made of or lined with refractory metals (such as molybdenum, niobium, tantalum, or tungsten), one method of implanting these metals is to use the arc chamber as a metal to be implanted. Source. The metal species to be implanted is selected by appropriately changing the material of the arc chamber, and by adjusting the magnetic analyzer to select the atomic mass unit (AMU) of the desired metal species, using the known isotope of the desired species as basis. For example, set 値 to 98 AMU for Mo or 184 for W as appropriate. Since W is also a commonly used filament material in ion source filaments of implantation tools, W can alternatively be adjusted to 184 AMU for individual ionization w or to dual ionization W by adjusting the analyzer magnet. 92 AMU for implantation. The dose and energy chosen for a particular metal species will be limited by the ability of the ion implantation system and the time spent on implantation. Du Yinzhuang, Consumer Co-operation of the Central Bureau of Standards, Ministry of Economic Affairs (please read the note ^^ on the back before filling out this page) For the specific case of Mo implants, the Mo arc chamber is installed in the implant system. Boron trifluoride source gas Zhao (BF3) was introduced into the arc chamber. Xianxin ionized BF3 is used to volatilize molybdenum from the arc chamber to provide a suitable Mo ion (98Mo +) beam current of about 200 mA and implant energy It is at least about 45 KeV. Since the arc chamber is sometimes coated with other materials in other conventional applications during use, it is preferable to use a clean or new source chamber to obtain the Mo ion beam current. When When Mo atoms are implanted under the above conditions (meaning 45 KeV energy), the maximum concentration of Mo atoms has been determined to occur in the silicon layer to a depth of about 30 nanometers. -14 Good paper standards are applicable to China National Standards (CNS > A4 specification (210X297 mm) 418464 ΓΓ: Description of the invention (12) Α7 Β7 degrees' equivalent to the peak Mo concentration of about 9 atoms / cubic centimeter β But, as discussed above, the most The river 0 atomic concentration of interest is at this surface. When using the above-mentioned optional tempering step, the SIMS data has shown that the concentration of Mo atoms at the surface is about 5 × 1018 atoms / cm³. It is expected that the surface concentration of refractory metals at the wonderful interface will exceed about 1017 atoms / Cubic centimeters may be desired. In another research approach, refractory metals are placed on the surface of the silicon layer by, for example, evaporation of metal pellets. This can be done by e-beam evaporation or by resistance heating (for example, 'will The pellets are placed in a crucible that has been heated by a large current). When evaporation is used, it is important that the thickness of the refractory metal is not too large. For example, the thickness of the Mo layer configured on the silicon layer is preferably less than about 20 nanometers. This is not an absolute maximum thickness, but when the thickness of the Mo layer increases above 20 nanometers, peeling of the silicide film has been found. More preferably, a Mo thickness of about 0.01 to 1.5 nanometers is used The thickness of other metals can be changed slightly. When such a small thickness of refractory metal is evaporated onto the silicon layer, it is sometimes difficult to control the evaporation rate β. Therefore, in one evaporation research approach, the shutter is set In the evaporation metal source chamber to contain refractory metal until it is ready to be placed on the silicon sludge. Then, the shutter is opened and closed fairly quickly (the so-called " emergency " evaporation) to provide a thin refractory metal layer on the silicon layer β can use other evaporation ways to better control the evaporation rate. The following is an alternative way to evaporate the refractory metal. The refractory metal can be placed on the silicon layer by sputtering instead of the method described above for evaporation. To a certain thickness. The correction of the sputtering method used is familiar -15- This paper size is not applicable to the National Solid State Standards (CNS) M specification (210 > < 297) and ——¾- c Read the note $ on the back and fill out this page)-Order the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs and print the Consumer Cooperative Work of the Central Prototype Bureau of the Ministry of Economics and Du Dudian 418464 A7 B7 V. Invention Description (13) clear. In addition to the above, the refractory metal can be arranged on the silicon substrate by exposing the surface of the cutting layer to a solution containing refractory metal ions. In a preferred research approach, the solution is aqueous and can contain dilute acid. , Such as HC1 or _ acid. As far as the above research methods are concerned, the wafer is tempered after the step of arranging refractory metal and before the step of depositing titanium layer, as the case may be. This tempering step is preferably performed at a wafer temperature of at least about 90 ° C, and more preferably between about 900 ° C and 1000 ° C. Figure 4-9 presents experimental data on several TiSi2 films formed according to the present invention. Β Figure 4 shows the resistance of the titanium silicide layer to the sputtered titanium according to the present invention with respect to the treatment of several kinds of TiSi2 films with and without the use of refractory metals. Thickness chart. This data shows that standard films are formed when refractory metal is not used and when a second phase transition tempering is not used. The TiSi2 film corresponding to the data points of W and the data of Mo was formed according to the present invention in n2 on (100) single crystal silicon by tempering at 600 eC for 30 minutes. After the refractory metal (using both w and Mo) is implanted ', use the optional RTA of 5 seconds and 1000X for tempering. When TiSi2 film is formed at about 600eC, this optional tempering is necessary, but it is not necessary for the formation temperature of about 700 ° C. The sheet resistance of each film is shown by the data points in the table. Figures 5-7 are in-situ scanning resistance diagrams illustrating the sheet resistance of a titanium silicide layer formed in accordance with the present invention regarding the treatment of several types of refractory metals with and without evaporation. These measurements are performed during the formation of the TiSi2 film by continuously placing a four-point probe in the furnace. The refractory metal shown in Figure 5-7 is applicable to the Chinese papers (CNS) A4 regulations (210X297 mm) at the X degree of the clothing paper. (谙 Please read the $ on the back and fill in this page). Order printing of A7 B7 in the Central Standard Bureau of the Ministry of Economic Affairs and Consumer Cooperatives Fifth, the description of the invention (14) is configured by the "emergency" evaporation method described above. Figure 8 is an in-situ scanning resistance table for TiSi2 thin films, which uses implanted rather than evaporated refractory metals. The general conditions for 囷 5-8 include forming a silicide film from a 57.5 nm-thick Ti layer previously deposited on a polycrystalline silicon layer of about 300 nm. Each silicide film is formed at about 15 ° C per minute by slowly increasing the temperature. Turning now to Figure 5, curve 30 shows the sheet resistance behavior of the titanium silicide film formed without the use of refractory metal. Curve 30 shows a known and expected increase in resistance, which is due to the mixing near point 32, where curve 30 forms a resistance peak 値 at about 500 Ό. Above about 500X, its resistance decreases as shown by arrow 34. When the temperature moves from about 50 ° C to about 700 ° C, the TiSi2 film formed is substantially in the C49 phase. "At about 700 ° C, the curve 30 flattens at point 36 to become the so-called" knee ". In which, the resistance system remains substantially unchanged with increasing temperature. This "knee" is converted from the C49 phase to the C54 phase due to the silicide film rupture until it reaches an even higher temperature. In contrast to curve 30, the curve Series 40 illustrates the resistance of the silicide film formed after the configuration of about 0 015 nm Mo according to the present invention. The behavior is similar, but it is noted that the " lap " found in curve 30 above does not substantially Exist in curve 40 (see point 42) »The absence of this knee indicates that the phase 54 of Ding Zhan ^ was formed directly to a large extent during the silicidation without passing through the C49 phase. In Figure 6 Curve 50 shows the sheet resistance behavior of the silicide film formed. Among them, about 0.015 nm Ta is configured according to the present invention by rapid evaporation. As for the curve 40 in FIG. 5, during the formation of the TiSi2t C54 phase, no Significant knees. In Figure 7, curve 60 says According to the present invention, -17- this paper size is applicable to China Customs Service Standard (CNS) A4 specification (2 丨 〇χ297 public shame) (please read the notes on the back before filling this page) 袈 · Order 418464 • '«' -.rS- 418464 • '«' -.rS- Printed by A7 B7, Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 5. Description of the invention (15) The sheet resistance versus temperature of a TiSi2 film formed with about 0.015 nm W. The curve 30 shown is compared with the 40 series and the curve 60. Again, for the curve 60, there is no significant knee, and the C54 series is formed substantially at a temperature below about 700. Circle 8 is an in-situ scanning resistance chart Explains the sheet resistance of the titanium silicide layer formed by the implantation of refractory metal according to the present invention. Curve 70 is a control silicide film formed without refractory metal for comparison purposes, and curve 80 is before deposition Ti In which Mo has been implanted (at a dose of 1014 atoms / cm2 and an implantation energy of 45KeV) of a TiSi2 film. After Mo implantation, the tempering step is performed at 900eC before depositing Ti. 10 minutes. As used above Line 30, curve 70 at point 72_ shows the knees, but curve 80 does not. The knees of curve 80 do not exist, indicating that the TiSi2i C54 phase is formed substantially at a temperature below about 700 °. Min 9 Histogram of measured resistance of titanium silicide lines with and without Mo ion implants according to the present invention. In addition to the data presented in Figures 4-9 above, there is further evidence that the C49 phase is essentially By the present invention, the silicidation is bypassed. Optical micrographs of the C54 phase of the titanium silicide layer formed according to the present invention have shown that the grain size is significantly smaller than the conventional case where no refractory metal is used. This proves that the nucleation energy barrier of the C54 phase is significantly reduced by the method of the present invention. This becomes the most important in VLSI circuits where the line width is smaller than the C54 phase grain size that would be formed if the conventional approach is used. Although the above-mentioned method according to the present invention is believed to be quite powerful, there are some precautions for its use. First of all, when using the present invention to prevent the possible -18-this paper size uses the Chinese household rate (CNS > Λ4 size (210X297 mm) ί1 ^ ------ ir viv. T (please first Please read the notes on the back of the reading and fill in this X) 41846 4 A7 B7 V. Description of the invention (16) When the problem of the instability of the magical compound, the heating cycle should be avoided for more than 7000 hours and last a long time. If the thickness is too large, it may cause delamination of fragmented materials. Another advantage of the present invention is that it does not generate an amorphous silicon layer on the top surface of the silicon layer. Specifically, when an ion implantation method is used In the configuration of refractory metal, 'optional tempering step will remove any amorphous silicon that may exist. In other ways, it is not necessary to perform optional tempering to avoid the crystalline dream. It is generally expected to avoid amorphous silicon. Exist, because it will be damaged by junction leakage6 In an alternative embodiment of the present invention, metal silicide may be formed in a layer overlying a silicon layer on a semiconductor wafer by a method including: Deposition of a titanium alloy containing refractory metal On the silicon layer, the wafer is heated to a temperature sufficient to substantially form the C54 phase titanium silicide from the titanium alloy layer, wherein the phase transition temperature of the titanium alloy is reduced due to the presence of refractory metal. The temperature used to form the C54 phase is lower than The best line is less than about 700. (: >> With reference to FIGS. 1 and 10, the Chin alloy layer 30 may be deposited on the surface of the wonderful substrate 10. The silicon substrate 10 may itself cover other electronic components, or may itself Contains-some of these components' However, these aspects of the semiconductor device have not been shown to more clearly show and explain aspects of the invention. The term " electronic component " as used herein is intended It includes both passive electronic components and active electronic devices. The titanium alloy layer may include titanium and refractory metals up to 20 atomic percent, examples of which are Ta 'Nb, Mo, W, V, Cr, or a combination thereof. Ta and Nb are relatively In addition to refractory metal, "Silicon refractory metal" can also be incorporated into the titanium alloy layer. Those skilled in the art will understand that the silicon is added to the titanium alloy layer. Λ4 specifications (2 丨 0X297 mm) please First «read the back note

I Printed by the Central Standards Bureau of the Ministry of Economic Affairs, printed by WC Industrial Consumer Cooperative, 418464 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, printed by the Consumer Consumer Cooperative of A7 B7 V. The embodiment of the invention description (17) can suppress the automatic alignment of silicide processing technology. Use β In addition to refractory metal, the titanium alloy layer can also be doped with other elements from the 11th, ^, 乂, and \ / 1 groups of the periodic table, including 8, 0:,: ^, 〇, ^ \ 1 , P, In, Sb, and As. Elements of the VIIA group, such as F, are avoided, but if present, they should be present at a content far lower than the original percentage of refractory metal. The β-Cin alloy layer can be configured by any of several techniques known in this technology. Titanium The refractory metal can be deposited from a different source of titanium, or a titanium source that also contains a small amount of refractory metal, so that the atomic percentage of the refractory metal layer in the formed layer is less than 20 atomic%, preferably 1- 15 atomic percent. Titanium alloys can be deposited on dream substrates by sputtering by physical vapor deposition (PVD). For example, an alloy target for radioactivity is prepared so that when a thin film is deposited on a silicon substrate, it has a desired atomic percentage of metal to fire. Alternatively, the vapor-deposited PVD method can be used to configure the salvage alloy, in which titanium and refractory metals are deposited from two different sources at an appropriate rate to achieve the desired percentage of refractory metal atoms. Regardless of any of the above methods, and other methods known in the art for depositing titanium or metal oxides, a titanium alloy layer can be disposed on a silicon substrate. The gypsum alloy layer may be configured to have a thickness of 10 to 200 nm, preferably 10 to 60 nm. Referring to Figures 10 and 11, the titanium alloy layer 30 can then be heated to a temperature sufficient to form a layer that is substantially C54-phase crystalline 32. The phrase "essentially C54 phase" as used herein means a titanium silicide layer in which the resistance characteristic is dominated by the C54 phase and contains at least 50% by weight of the C54 phase β as described in more detail below Discussant, the advantage of the present invention is that the phase transformation tempering step can be -20 ---- c · ^ ------ ΐτ (谙 first read the notes on the back and then fill out this page) {{PMC 'i / -Hftw Λ 必 —' · * yz < 418Αβ ^ Α7 ___ B7 V. Explanation of the invention (18) is exempted, because the C54 phase can be formed directly directly during the titanium silicide formation step, so avoid The second phase is the need to transform and temper. Furthermore, since refractory metals are present in titanium silicide, thermal degradation temperatures, such as unwanted cohesion temperatures, may increase substantially. Increasing the thermal degradation temperature has the benefit of establishing a larger processing window. As shown in Fig. 12, the in-situ scanning resistance circle indicates that, with respect to the formation temperature of pure titanium silicide, titanium silicide having a refractory metal therein has a reduced formation temperature. This figure also shows that when using refractory metal, thermal stability increases. The titanium layers referred to in FIG. 12 are each tempered in a He atmosphere to a temperature of 1050 eC (15 ° C / minute).囷 13 shows the resistivity as a function of the atomic percentage of refractory metal present in the titanium alloy used to form the titanium silicide. This titanium alloy is tempered to 900eC (15 ° C / min) in He atmosphere. The area surrounded by a dashed line and titled "C49 TiSi / and" C54 TiSi2 "indicates the standard resistivity range of the C49 phase and C54 phase TiSi2 formed by pure 1 through 2. This line is It shows that the tempered titanium alloy with 1-20 atomic percent refractory metal in the present invention has a resistance much lower than that of C49 phase TiSi2. However, the titanium alloy formed with Mo has a concentration of less than about 5 Printed by the cooperative -------- ί} Table __ '(please read the note on the back before filling out this page) The atomic% shows the reduced resistivity. In addition, Figure 14 also shows the resistivity As a function of the atomic percentage of refractory metal present in the titanium alloy used to form the titanium silicide. However, in Figure 14, the tempering is on a 30-50 nm titanium alloy layer in N2 atmosphere at 700 ° C (35 ° C / sec, hold for 60 seconds). Figures 13 and 14 show titanium silicides formed from titanium alloys doped with Ta, Nb, Mo, W and V, each showing a resistance much lower than that of C49. Titanium. Figure 15 further shows the temperature at which C54 is formed as added to the titanium alloy. National Standards (CNS) A4 grid (210X297 mm) 418464 Consumption cooperation between employees of the Central Bureau of Standards, Ministry of Economic Affairs, Du printed A7 B7 V. Description of the invention (19) A function of the atomic percentage of refractory metals. Figures 14 and 15 both show this The tempered titanium alloy of the invention has a resistance equivalent to that of the C54 phase TiSi2 made of pure TiSi2, and it achieves such low resistance under relatively low temperature tempering. The method of the present invention can be easily integrated into the present In the semiconductor manufacturing technology using a silicon silicide layer made of pure titanium, for example, referring to FIG. 16, it shows a CMOS transistor using the titanium silicide layer 50 of the present invention as the source 52, the drain 54 and the gate 56 on N-MOSFET and P-MOSFET devices. However, the titanium silicide of the present invention can be used with many other electronic component manufacturing processing techniques. A titanium alloy containing titanium and refractory metals can be deposited on the device, including polycrystalline silicon The layer 58 and the highly mixed debris in the regions of the source 52 and the electrode 54 are like the pure titanium used in the current self-aligned silicide application. After deposition, the titanium alloy can be first " formed and tempered "; It can be heated at low temperature to form titanium silicide. Because C54 phase titanium silicide can be made from alloy at a significantly lower temperature than other silicides, its forming and tempering can form a dream layer of titanium which is essentially C54 phase. Therefore, in many cases, when a titanium alloy is used, the need for transformation and tempering can be completely eliminated, because the C54 phase titanium silicide can be essentially formed at the first low temperature tempering. However, depending on the forming tempering temperature and device Depending on the geometry, 'transform backfire' may still be necessary in some applications. This fragmentation—whether it is the C49 phase, the C54 phase, or a mixture of the two—can then be selectively etched to remove unreacted portions of the titanium alloy layer in accordance with current processing techniques. This procedure is commonly referred to as " auto-aligned silicide " or auto-aligned silicide procedure, because the titanium alloy region that is not positioned on the silicon substrate will not react to form silicide, and can be etched " Automatic alignment ", this etching system is -22- Thai paper size applicable to China National Standards (CNS) A4 specifications (2) 0X297 mm) (谙 read the note on the back ^. Before filling this page) -11 A7 B7

41846A V. Description of the invention (20) Selectively etch metal with respect to silicide. After etching, the C49 phase titanium silicide or titanium silicide with a mixture of C49 and C54 phases can be subjected to a second tempering "conversion tempering", which converts the silicide into the desired substantially C54 phase silicide. However, Even in cases where transformation and tempering are necessary or desired, the transformation and tempering can be performed at a relatively low temperature, so the available thermal budget is saved. After the low resistivity titanium silicide layer of the present invention is formed, Electronic components and desired interconnections can be completed using conventional semiconductor manufacturing technologies. Β Using pure titanium silicide, the forming and tempering system forms C49 phase titanium silicide. The forming and tempering must be completed at low temperature. It cannot form the C54 phase from pure TiSi2. To avoid the formation of silicide on undesired device areas, which is often referred to as a bridging problem. For example, in the device of FIG. 16, before selectively etching the undesired portion of the titanium layer, the device is accepted as The temperature necessary to form the C54 phase titanium silicide from pure titanium may cause silicide to form on the oxide interstitial 62. The silicide is formed on the interstitial 62 and will electrically connect the gate 59 to the source Area 52 or Sink 54 thus short-circuiting the device. Therefore, the current silicide processing technology must use a second high temperature tempering, which means transforming the tempering to silicify the C49 phase after etching the unreacted portion of titanium Titanium is transformed into the desired low-resistivity C54 phase. Therefore, it is particularly important that the low-resistivity titanium silicide layer, essentially the C54 phase, can be tempered in a single forming or transformed into a tempering device through a device with a titanium alloy. , Formed by heating at a temperature significantly below 900eC. As noted above, the formation of the C54 phase from titanium alloys has the advantage that it will cause less latent migration of dopant materials, including the pre-definition of individual electronic components The doped regions 58 and 60. Although the present invention has been described in detail above, it is not intended to be limited to this -23- this paper size uses the Chinese National Standard (CNS) A4 specification (210 X 297 mm) < Please read the notes on the reverse side before filling out this page) Ai. Order the consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs 418A64 A7 B7 V. Description of Invention (21) The specific form proposed in the text is intended to imply These alternatives and equivalents that can reasonably be included within the spirit and scope of the present invention are as defined by the patent application park attached to the article. Printed by the Consumer Consumption Cooperative of the Central Bureau of the Ministry of Economic Affairs- 24 < Please read the notes on the back before filling out this page)

The standard of this paper is Chinese National Standard (CNS) 8-4 gauge (2! 〇 × 297 mm)

Claims (1)

4Γ84β4 Α8 Β8 C8 m Printed by the Central Laboratories Bureau of the Ministry of Economic Affairs and Consumer Cooperatives to apply for patents 1. A method for forming a titanium silicide layer on a silicon substrate of a semiconductor device, comprising: disposing a titanium alloy layer on the silicon substrate Wherein the titanium alloy contains 1 to 20 atomic percent of a refractory metal; and a temperature at which the titanium alloy is heated sufficiently to substantially form a C54 phase titanium silicide 02. The method according to item 1 of the scope of patent application, wherein the temperature is low At about 700 eC 03. The method according to item 1 of the patent application group, wherein the substrate is heated to a temperature sufficient to completely transform the titanium alloy layer into a C54 phase titanium silicide. 4. The method according to item 1 of the scope of patent application, wherein the refractory metal comprises one or more elements selected from the group consisting of Ta, Nb, W, V, and Cr. 5. The method according to item 2 of the patent application scope, wherein the titanium alloy contains a refractory metal of 1 to IS atomic percentage. 6. The method according to item 5 of the Patent Application Group, wherein the refractory metal comprises a refractory metal selected from the group consisting of Ta and Nb. 7. The method according to item 2 of the scope of patent application, wherein the titanium alloy comprises titanium, silicon, and a refractory metal. 8. The method according to item 1 of the scope of patent application, wherein the titanium alloy layer is configured to be 10 to 60 nanometers thicker than the silicon substrate. 9. The method according to item 1 of the scope of the patent application, wherein the silicon substrate is selected from the group consisting of single crystal sand, polycrystalline debris, amorphous and hard alloy. 10. The method according to item 1 of the scope of patent application, wherein the silicon substrate is selected from the group consisting of insulating epitaxial silicon containing an N-type dopant, and --------- --2 ^ -__ This paper ruler uses two standard (CNS) A4 sizes (210X297mm) (please read the note on the back and read 3 ^ this page) Order the central ladder of the Ministry of Economic Affairs Ag B8 C8 D8 printed by the Bureau of Industrial and Commercial Cooperatives VI. Patent application scope Insulation external fragmentation 0 11. The method according to item i of the patent application park, wherein the titanium alloy is deposited on the silicon substrate by physical vapor deposition . 12. The method according to item 1 of the scope of the patent application, wherein the titanium alloy is deposited on the silicon substrate by chemical vapor deposition β 13. The method according to item 1 of the scope of the patent application, wherein the samarium alloy contains j to about 5 atomic percent of Mo. 14. A method for forming a titanium silicide layer in a semiconductor device, comprising: depositing a layer of 10 to 200 nm titanium alloy on the semiconductor device, wherein the beverage alloy contains 1 to 15 atomic percent of refractory metal, and the semiconductor device is Incorporating multiple electronic components with exposed silicon surfaces; heating the Cin alloy layer to a temperature sufficient to substantially form the C54 phase dreaming in the rhenium alloy layer covering the silicon surface, the temperature being below about 700 ° C And etching the unreacted portion of the titanium alloy layer. 15. A method of forming a titanium silicide layer in a semiconducting device, comprising: depositing a layer of 10 to 200 nanometer titanium alloy on a semiconductor device, wherein the alloy contains 1 to 15 atomic percent of a refractory metal, and the The semiconductor device incorporates a plurality of electronic components having an exposed silicon surface; heating the titanium alloy layer sufficiently to form titanium silicide in a hafnium alloy covering the silicon surface; etching unreacted portions of the titanium alloy; and heating the Titanium silicide is a temperature sufficient to substantially form the C54 phase silicide, which is below about 700 ° C. _-9R -_______ This paper size is applicable to China National Grey Kneading (CNS) A4 specification (210X297 ^ cent) (Please read the notes on the back before filling in this fW • HI-I k Order 4Α8464 Central Kneading Bureau of the Ministry of Economic Affairs A8, B8, C8, D8 π printed by the Industrial and Commercial Cooperative, patent application range 16, a semiconductor device with a titanium silicide layer, which includes:-a rare layer; and a layer of titanium silicide on the silicon layer, wherein the titanium silicide layer contains substantially • Upper C54 phase titanium silicide and refractory metal from 1 to 20 atomic percent. 17_ The semiconductor device according to item 16 of the scope of patent application, wherein the broken layer is selected from the group consisting of single crystal dream, polycrystalline dream, amorphous dream, wonderful W-alloy, Insulation hardening with N—type dopant and Insulating epitaxial silicon with N—type dopant. 18. The semiconductor device according to item 16 of the patent application, wherein the refractory metal is selected from one or more of the following Element Ta, Nb, W, V, or 0. 19. The semiconductor device according to item 16 of the scope of the patent application, wherein the myopic layer contains 1 to 15 atomic percent of the refractory metal. 20. According to the scope of the scope of patent application The semiconductor device according to item 17, wherein the refractory metal is selected from Ta and Nb. 21. The semiconductor device according to item 1 of the patent application scope, wherein the magic layer comprises 1 to 5 atomic percent of Mo. 22. According to the patent application The semiconductor device in the range of item 16 * wherein the magic drum layer has a thickness between 10 and 200 nanometers. -27- This paper size is applicable to 81 Chinese standards (CNS) A4 (210X297 mm) {please refer to Fujian Read the note $ on the back and fill in this I)