JP2586407B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a shallow junction diffusion layer having a low melting point by providing a refractory metal silicide film on the surface.

[0002]

2. Description of the Related Art As a typical example of a CMOS type semiconductor device having the above-described impurity diffusion layer, further miniaturization is being promoted for higher performance and higher integration. At this time, a shallow junction of about 0.1 μm or less is indispensable as an impurity diffusion layer used as a source / drain region of a MOS field effect transistor. Also, when the junction depth becomes shallow, the resistance of the impurity diffusion layer increases, which hinders the realization of a semiconductor device having high speed. Therefore, a salicide technique of forming a refractory metal silicide film in a self-alignment manner on an impurity diffusion layer or a gate electrode made of polycrystalline silicon is used. Conventionally, as a method of forming a junction on a semiconductor silicon substrate, a method has been used in which an impurity serving as a dopant is selectively introduced into a surface portion of the semiconductor silicon substrate by ion implantation, and annealing is performed by an electric furnace or a lamp annealing apparatus. . However, when impurities are introduced into a semiconductor silicon substrate by ion implantation, channeling occurs and the impurities penetrate deeply, and there is a problem that the junction cannot be made shallow. In order to solve this problem, as shown in FIG. 4, a method of ion-implanting impurities is shifted from the low-index crystal axis direction of the P-type semiconductor silicon substrate 1, for example, the [100] axis direction (first conventional example). 5)
As shown in FIG. 1, before the ion implantation of impurities, ions that do not affect the electrical characteristics of the semiconductor, for example, ions of silicon or germanium are implanted into the source / drain formation region on the P-type semiconductor silicon substrate 1 in advance. A technique of forming amorphous layers 9-1 and 9-2 near the surface (second conventional example) has been proposed. Further, Japanese Patent Laid-Open No. 3-1
No. 1731 discloses that the amorphous layer 6 is formed deeply in the P-type silicon substrate 1 by increasing the ion implantation energy of silicon to thereby form the amorphous layer 9-.
The crystal defects generated when 1,9-2 are recrystallized are
A method is described in which a transistor is formed in a region deeper than a depletion layer extending from a source / drain region of a field effect transistor to obtain good current-voltage characteristics.

On the other hand, a conventional salicide structure LDDMO
Manufacturing method of S-type field effect transistor (third conventional example)
As shown in FIG. 6A, according to a normal semiconductor manufacturing process,
Well 2, field oxide film 3, gate oxide film 4, gate electrode 5 made of polysilicon, low-concentration impurity implantation layer 6
After forming -1, 6-2, as shown in FIG.
A silicon oxide film 7 is deposited, and as shown in FIG.
The insulating spacer 8 is formed using anisotropic etching, ion implantation is performed, and heat treatment is performed to form the high concentration impurity diffusion layers 15-1 and 15-2 (at this time, the low concentration impurity implantation layer 6-1). , 6-2 are activated to form low concentration impurity diffusion layers 14-1 and 14-2), and as shown in FIG. The silicon oxide film is removed, and a titanium film 11 as a high melting point metal is deposited on the entire surface by a sputtering method. Thereafter, a first heat treatment is performed at 650 ° C. for about 30 seconds in a nitrogen atmosphere to cause a silicide reaction. As a result, FIG.
As shown in (b), the C49 phase TiSi ₂ film 12-
1, 12-2 and 12-3 are formed. Then, surplus T
An i-etch, a second heat treatment at 800 ° C. for about 10 seconds is performed, and as shown in FIG. 7C, the C54 phase TiSi ₂ films 13-1, 13-2, and 13-3, which are low-resistance phases, are formed. Form. Thereafter, according to a conventional process, an interlayer insulating film (not shown) is formed, a contact hole is opened, a contact hole is opened, and a metal wiring, a protective film and the like are formed.

[0004]

In the conventional method of forming an impurity diffusion layer having a shallow junction, which is a method of ion-implanting an impurity off a low-index crystal axis, channeling can be sufficiently suppressed. Immediately after the ion implantation, impurities have already penetrated to a deep region in the P-type semiconductor silicon substrate 1, and it is difficult to form a shallow junction of 0.1 μm or less. On the other hand, in the method in which the amorphous layers 9-1 and 9-2 are previously formed by implanting silicon ions near the surface of the P-type semiconductor silicon substrate 1, channeling due to ion implantation can be suppressed, and The impurity distribution can be limited to a shallow region. However, during the subsequent annealing heat treatment for activating the impurities, the impurities diffuse to the deep region of the P-type semiconductor silicon substrate 1 and it is difficult to form a shallow junction. This is because of the Journal of Electronic Materials
(Tronic Materials), Vol. 19, No. 1, 1990, pp. 67-88. That is, the amorphous layers 9-1 and 9-2 formed by the implantation of silicon ions during the annealing heat treatment.
Is recrystallized, and the presence of point defects at that time accelerates the diffusion of impurities.

SUMMARY OF THE INVENTION It is an object of the present invention to suppress an impurity ion-implanted into an amorphous layer from being accelerated and diffused during annealing heat treatment, and to provide a shallow junction impurity diffusion layer having a low resistance by a high melting point metal silicide film. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can form a semiconductor device.

[0006]

According to a method of manufacturing a semiconductor device of the present invention, an amorphous layer is formed by implanting Group IV element ions into a surface portion of a semiconductor silicon substrate, and the surface portion of the amorphous layer is formed. To form an impurity-implanted layer, deposit a high-melting metal film on the impurity-implanted layer, and perform a first heat treatment at a temperature of at most 500 ° C. at which the amorphous layer is not recrystallized. The refractory metal film is silicided, and the reaction product formed on the surface of the refractory metal film during the first heat treatment and the refractory metal film remaining unreacted are removed, and the temperature exceeds 500 ° C. Forming an impurity diffusion layer by performing a second heat treatment at a temperature to recrystallize the amorphous layer, activate the impurity implantation layer, and perform a phase transition of the refractory metal silicide. It is.

The source of a MOS type field effect transistor
To form an impurity diffusion layer as a drain region, a gate electrode for selectively covering the surface of a semiconductor silicon substrate via a gate insulating film is formed, and an insulating spacer is formed on a side surface of the gate electrode. A crystalline layer may be formed.

As the refractory metal, titanium, tungsten, zirconium or hafnium can be used.

When the refractory metal is titanium, the titanium silicide after the phase transition is mainly composed of TiSi ₂ having a crystal structure of C54.

Of the Group IV elements, silicon or germanium, especially silicon, is preferred.

[0011]

Since silicon atoms are consumed in the first heat treatment, diffusion of interstitial silicon-impurity atoms or vacancy-impurity atoms in the second heat treatment is reduced.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings.

First, as shown in FIG. 1A, an N-type well 2 is formed on the surface of a P-type semiconductor silicon substrate 1, and a field oxide film 3 is selectively formed to partition an element formation region. Then, a gate oxide film 4 having a thickness of 10 nm is formed on the surface of the element formation region, and a polysilicon film is deposited and patterned to form a gate electrode 5. Next, boron ions are implanted under the conditions of an implantation energy of 20 keV and an implantation amount of 3 × 10 ¹³ cm ⁻² to form low-concentration impurity implantation layers 6-1 and 6-2.

Next, as shown in FIG.
A silicon oxide film 7 having a thickness of 0 nm is deposited by a CVD method, and an insulating spacer 8 is formed by anisotropic etching as shown in FIG. Next, using the gate electrode 5, the insulating spacer 8 and the field oxide film 2 as a mask, silicon ions are implanted under the conditions of an implantation energy of 70 keV and an implantation amount of 2 × 10 ¹⁵ cm ⁻² , and from the surface of the P-type semiconductor silicon substrate 1 Amorphous layer 9A over a depth of 200 nm
-1, 9A-2 are formed. By the silicon ion implantation, the silicon atoms themselves constituting the P-type semiconductor silicon substrate 1 are repelled, and the amorphous layers 9A-1 and 9A are removed.
-2 is an aggregate containing vacancies and excess interstitial silicon. Next, as shown in FIG. 1D, similarly to the above, using the gate electrode 5 and the like as a mask, an element formation region is implanted with boron fluoride as a P-type impurity at an implantation energy of 20 ke.
V, ion implantation (average range: 20 nm) under the condition of an implantation amount of 3 × 10 ¹⁵ cm ⁻² , and a high-concentration impurity implanted layer 10A-1,
Form 10A-2. Next, as shown in FIG. 2A, a titanium film 11 is deposited on the entire surface as a high melting point metal film to a thickness of about 20 nm by a sputtering method. Thereafter, a first heat treatment is performed at a temperature and a time at which the amorphous layer is not recrystallized by a lamp annealing method in a nitrogen atmosphere, that is, at a temperature of 500 ° C. or less, for example, at 450 ° C. for about 30 seconds, and a titanium silicide film 16-1, 16-2 and 16-3 are formed. Since the temperature of the silicide is low, these titanium silicide film TiSi _x, can be expressed (x <2), and. At this stage, diffusion of boron fluoride hardly occurs. Next, the titanium silicide films 16-1, 16
The reaction products such as unreacted Ti and titanium nitride formed by the first heat treatment existing on -2, 16-3 are removed by using an ammonia hydrogen peroxide solution, and the lamp is annealed in a nitrogen atmosphere by a lamp annealing method. Second in about 10 seconds at around 850 ° C
2C, the titanium silicide films 13A-1, 13A-2, and 13A-3 become high-concentration impurity diffusion layers 15A-1, 15A-1 as shown in FIG.
15A-2 and on the gate electrode 5. By performing this heat treatment, the titanium silicide film formed by the first heat treatment undergoes a phase transition to a low-resistance C54 phase titanium silicide (TiSi ₂ ) having a sheet resistance of 3Ω / □. At the same time, the amorphous layer is recrystallized, and the ion-implanted boron is also activated (the low-concentration impurity implantation layers and the high-concentration impurity implantation layers become low-concentration impurity diffusion layers and high-concentration impurity diffusion layers, respectively). .

Thereafter, according to a normal process,
A not-shown interlayer insulating film is formed, a contact hole is opened, a metal wiring is formed, a protective film is formed, and a MOS is formed.
The fabrication of the field effect transistor is completed.

FIG. 3 is a diagram showing a comparison between the distribution of boron after the heat treatment for activating boron according to the present embodiment and that of the conventional example. In the conventional example described with reference to FIGS.
As shown in the profile b, boron diffuses to a deep region in the P-type semiconductor silicon substrate 1, and the junction formed has a depth of about 0.2 μm.
As shown in FIG. 7, in this embodiment, the depth can be reduced to 0.1 μm or less.

Although the reason why such an impurity diffusion layer having a shallow junction can be formed by this embodiment cannot be explained sufficiently, it can be understood to some extent by considering the following. Let's assume that the amorphous layer is replaced with a crystalline layer. When titanium silicide is formed by the first heat treatment, vacancies are generated in the P-type semiconductor silicon substrate 1 by the movement of silicon, which is a diffusion species of the titanium silicide reaction, into the titanium film 11, and the amorphous silicon becomes amorphous. Layer 10A-1,
Excess interstitial silicon in 10A-2 is consumed.

It is a common theory that the diffusion of boron and BF ₂ ^{+ in} a silicon crystal can be explained by an interstitial silicon-impurity pair diffusion model, so that the accelerated diffusion of impurity diffusion during the second heat treatment is suppressed. Is done. In the present embodiment, even if it is estimated that a phenomenon similar to this occurs, it cannot be said that it is an error.

Although the case where amorphous is formed by using Si as a group IV element has been described, other elements such as Ge and C,
In particular, Ge can be used. This is because lattice silicon is repelled when amorphous by ion implantation, and interstitial silicon is generated. In addition, there is almost no possibility that the high-melting point metal such as titanium and Ge react with each other to form an alloy in the first and second heat treatments.

Although the case where titanium is used as the high melting point metal has been described, silicon, tungsten, zirconium, hafnium, or the like may be used as a diffusion species during the silicide reaction.

Further, the case where the P-type impurity diffusion layer is formed has been described. However, the present invention is also applicable to the case where the N-type impurity diffusion layer is formed. It is considered that about 50% of the diffusion of P and As in a silicon crystal is caused by a vacancy-impurity atom pair, and it is considered that the vacancy decreases during the first heat treatment.

[0022]

As described above, according to the present invention, the interstitial silicon in the amorphous layer formed by the implantation of Group IV element ions can be consumed by the silicide reaction at a low temperature. Accelerated diffusion of impurities serving as a dopant ion-implanted into the crystalline layer can be suppressed. As a result, a shallow junction impurity diffusion layer having a low resistance can be formed by a silicide film indispensable for a miniaturized MOS type field effect transistor and the like, which has an effect of contributing to high integration of a semiconductor device.

[0023]

[Brief description of the drawings]

FIGS. 1A to 1D illustrate an embodiment of the present invention.
FIG.

FIGS. 2A to 2C are cross-sectional views in the order of steps, which are separated from FIGS.

FIG. 3 is a graph showing a profile of an impurity diffusion layer according to an embodiment of the present invention in comparison with a conventional example.

FIG. 4 is a cross-sectional view for explaining a first conventional example.

FIG. 5 is a sectional view for explaining a second conventional example.

6 (a) to 6 (c) are cross-sectional views in the order of steps for explaining a third conventional example.

FIGS. 7A to 7C are cross-sectional views in the order of steps, which are separated and shown in FIGS.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type semiconductor silicon substrate 2 N-type well 3 Field oxide film 4 Gate oxide film 5 Gate electrode 6-1 and 6-2 Low-concentration impurity injection layer 7 Silicon oxide film 8 Insulating spacer 9-1, 9-2, 9A -1,9A-2 Amorphous layer 10-1,10-2,10A-1,10A-2 High concentration impurity injection layer 11 Titanium film 12-1,12-2,12-3 TiSi ₂ film 13-1 , 13-2, 13-3 TiSi ₂ film 13A-1, 13A- _2, 13A-3 Titanium silicide film 14-1, 14-2, 14A-1, 14A-2 Low concentration impurity diffusion layer 15-1, 15 −2,15A-1,15A-2 High concentration impurity diffusion layer

Claims (5)

(57) [Claims] 1. An amorphous layer is formed by implanting Group IV element ions into a surface portion of a semiconductor silicon substrate, and an impurity implanted layer is formed by implanting impurity ions into a surface portion of the amorphous layer. A high melting point metal film is deposited on the impurity-implanted layer, and a first heat treatment is performed at a temperature of at most 500 ° C. at which the amorphous layer is not recrystallized to silicify the high melting point metal film. Sometimes, the reaction product formed on the surface of the refractory metal film and the unreacted refractory metal film are removed, and a second heat treatment is performed at a temperature exceeding 500 ° C. to form the amorphous layer. A step of forming an impurity diffusion layer by recrystallizing, activating the impurity implantation layer, and performing a phase transition of the refractory metal silicide. 2. A method according to claim 1, further comprising forming a gate electrode for selectively covering a surface of the semiconductor silicon substrate via a gate insulating film, forming an insulating spacer on a side surface of the gate electrode, and then forming an amorphous layer. Item 2. A method for manufacturing a semiconductor device according to Item 1. 3. The method according to claim 1, wherein the refractory metal is titanium, tungsten, zirconium or hafnium. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the high melting point metal is titanium, and the titanium silicide after the phase transition is mainly composed of TiSi ₂ having a crystal structure of C54. 5. The method of claim 1, wherein the Group IV element is silicon.
5. The method for manufacturing a semiconductor device according to 2, 3, or 4.