JPS6239922A - Digital demodulation system - Google Patents

Abstract

PURPOSE:To improve the 2nd equalization capability limit by applying logic operation to a control signal of each tap at an imaginary part in a transversal equalizer among a quadrant discrimination output, a position discrimination output and an area discrimination output. CONSTITUTION:A 64QAM wave input signal enters a transversal filter 3 comprising a delay circuit and a weight circuit, a control signal from weight control circuits 2R, 2L is received to reject an inter-code interference of the input signal and an output signal without inter-code interference is obtained at the output of a demodulator 4. A real part weight control circuit 2R receives quadrant discrimination signals D1p, D1q and error signals Ep, Eq as the input to output weight control signals R+ or -1, R+ or -2. An imaginary part weight control circuit 2I receives quadrant discrimination signals D1p, D1q, a position discrimination signal S1, and an area discrimination signal S2 and error signals Ep, Eq to send weight control signals I+ or -1, I+ or -2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention aims to improve the equalization capability of a multidigital demodulation system including a demodulator and a transversal equalizer.

[Prior art and problems to be solved by the invention] Various microwave digital transmission systems have already been put into practical use, and the development and practical use of multilevel digital modulation systems, starting with the 16 QAM system, is progressing recently. . Although such a multi-level digital modulation wave system is capable of highly efficient information transmission, it is extremely susceptible to various distortions in the transmission system, and countermeasures against fading in the propagation path become serious. As a countermeasure against this problem, a transformer equalizer is known to be an effective means, and is now commonly used in high-efficiency transmission systems, but its equalization characteristics have the following disadvantages.

That is, the first equalization ability limit value when the transmission distortion (code amount interference) goes from a small state to a high level, and the transversal equalizer goes from a state where the transmission distortion is large and the transversal equalizer is inoperable, to an operating state when the amount of distortion is reduced. Although it is desirable that the second equalization ability limit values are equal after going through the process of returning to , the second equalization ability limit values are very small under the current characteristics. This indicates that the transversal equalizer is not fully demonstrating the equalization ability that it should have.

[Means for solving problems]

The present invention eliminates the above drawbacks and provides a digital demodulation system including a transversal equalizer and demodulator that improves the second equalization capability limit value.

Its feature is that it includes a demodulator and a transformer equalizer, and after demodulating the digital modulated wave to obtain a demodulated signal, it performs multi-level discrimination and reproduces multiple columns of data output including the main data signal. In the digital demodulation system, quadrant discriminating means performs binary discrimination on the demodulated signal to obtain a quadrant discrimination output; and binary discrimination means performs binary discrimination on a phase shift signal obtained by shifting the phase of the demodulated signal by one Fujian to obtain a position discrimination output. and position determination means to obtain.

region discriminating means for performing multi-value discrimination on the phase shift signal or performing a logical operation on the data output to obtain a region discriminating output; and means for obtaining the determination output by performing a logical operation between the determination output, the position determination output, and the area determination output.

〔Example〕

The present invention will be described in detail below using two drawings.

FIG. 1(,) is an embodiment of a digital demodulation system applied to a 64-value quadrature amplitude modulated wave (hereinafter abbreviated as 64 QAM wave) according to the present invention, and FIG. This is an example. In the figure, 1 is an IF band transversal equalizer r, 2B is a real part weighting control circuit,
2□ is an imaginary part weighting control circuit, 3 is a transversal filter, 4 is a demodulator, 5 is an identification section, and 6 is a quadrature detector (Q
AMDET), 7, 8 are variable resistance attenuators, 9-1
4 is A/l) converter (A/i) C0NV).

15 and 1.6 are AGC circuits (AGC), and 17 is a subtracter.

18 is an adder, 19 to 23 are EX-OR circuits, 24 is A
ND circuit, 25 is a NAND circuit, 26 is a D type frizzo flop, 27 is a selection circuit, and 28 is an OR circuit.

29 is a logic circuit for carrier synchronization, and 30 is an asynchronous detection circuit (
DET), 31 is a low pass filter (LPF),
32 is a voltage controlled oscillator (VCO), and 33 is a ROM.

The operation will be explained below.

64 The input signal of the QAM wave enters the transversal filter 3 composed of a delay circuit and a weight pair circuit, where it receives control signals from the 2 weighting control circuits 2Rl and 2I, and removes the code amount interference that the input signal has. As a result, an output signal free from code amount interference is obtained at the output of the demodulator 4.

The real part weighting control circuit 2R receives the quadrant discrimination signal D1p T Dlq T error signal Ep and E as input, and outputs a weighted control signal R1+R±2, which is conventionally used. It consists of a circuit.

The imaginary part weighting control circuit 2 is a feature of the present invention.2 In this embodiment, the quadrant discrimination signals D1p, D1
9. Position determination signal S4. Area discrimination signal S2. error signal E
, E, and the weight becomes ■±1+'lO.
q Send control signals. Details will be described later.

The output of the IF band transversal equalizer 1 enters the demodulator 4, is multiplied by a reference carrier wave ('CARR) in the quadrature detector 6, and is converted into demodulated signals P and Q. The variable resistance attenuators 7 and 8 are controlled by control signals so that the input levels of the Φ converters 9 and 10 are optimized. The control signal is obtained by AGC circuit 15,16. A
/b converter 9.10 consists of 4 pits, and its output is from MSB to 3 pits, namely Dlp-D3p and Dlp.
,~D3. .

is the main data signal, D4p(E,), D4. (E9) is sent out as an error signal.

Next, the second
This will be explained using the diagram (,).

FIG. 2 (,) is a signal arrangement diagram of 64 QAM waves.

The P and Q axes represent quadrant discrimination axes.

The imaginary part weighted control signal is created from the phase rotation error information of each signal point, and gives phase rotation to each signal point.
This is basically the same phase error signal that is also used as a control signal for carrier synchronization circuits.

Further, the position determination signal S1 here is equivalent to a phase error signal in a carrier synchronization circuit.

(However, S is a signal before correlation with quadrant discrimination signals D1 and D19, and 1p is a signal before correlation with D and D
The Iq calculation is performed by the imaginary part weight pair control circuit 2□. )
Wire converters 11-14. Subtractor 17. Adder 18, E
The circuit composed of X-OR circuits 19 to 21 is a well-known digital Costas-type phase-locked circuit for PSK waves, and for example, the A184.5 r circuit that was announced at the 1978 IEICE General Conference. 4 PSK demodulator using baseband processing type carrier synchronization circuit" is also described.

That is, subtractor 17. Adder 18 receives demodulated signal P.

The phase of Q is shifted by 1 Fujian, and the position discrimination signal S1 is obtained by performing an EX-OR operation on each Ll in an EX-OR circuit 20. Furthermore.

If the output of the EX-OR circuit 20 and the output of the EX-OR circuit 19 are subjected to EX-OR operation by the EX-OR circuit 21, E
The output of the X-OR circuit 21 is 4. This becomes a phase error signal for PSK waves.

Here, the phase error signal obtained from the EX-OR circuit 21 is a signal that can be regarded as equivalent to 4 PSK waves in FIG.
It is obtained from signal points on the 1st axis rQ1st axis. At that time, it is unrelated to the amplitude value of each signal point.

Even if it moves on the Pl and Q1 axes, erroneous phase error information is not created, but correct phase error information is obtained only when it moves away from the r Pl + Q1 axis.

This means: When the input signal is subject to in-phase interference and quadrature interference at the same time, in the conventional CD I-Lance Parsal equalizer, the imaginary part control signal and the real part control signal interact with each other and go through a process of sequential convergence, which reduces the convergence speed. When the signal is slow and there is a large amount of interference, it may not be possible to converge.9 However, the imaginary part control signal according to the present invention can converge independently without being affected by common-mode interference and input level fluctuations, so the convergence speed can be reduced. This has the effect of increasing the speed and increasing the amount of interference that makes convergence impossible.

Next, the area discrimination signal S2 signal will be explained. 'The intervention force signal is a 64 QAM wave, and there are many signal points in addition to the signal points on the + Pl r Q1 axis, and these signal points are far from the Pl and Q1 axes), and correct phase error information can be extracted from these. Otherwise, you will receive jitter.

Therefore, a configuration is adopted in which a region is provided near the Plr QH axis and the output of the EX-OR circuit 21 is used only when a signal point falls within this region. The threshold level of the L2 output of the Φ converter 13.44 is set to ±t in FIG. When , it becomes II Q II.

Therefore, the area discrimination signal S2 becomes t+171 when each signal point enters the area a1.

The area discrimination signal S2 is sent to the imaginary part weight pair control circuit 2. Since the 1 phase error signal inputted to the Pl r Q1 axis is output from a signal point near the Pl r Q1 axis, a control signal with less jitter components can be created. The smaller the set value of the threshold level ±t, the less the jitter component will be. However, if the two-position discrimination signal s1 is used as the phase error signal for the carrier synchronization circuit, the pull-in phase will be as shown in Figure 2 (a). Instead of the state shown, a so-called pseudo-entrainment phenomenon occurs that stabilizes at a position with a certain phase rotation from this state, so in the end, the value of t becomes P,
.

It can be said that it is desirable to set it to the maximum value that does not include other signal points on the Q1 axis. The area discrimination signal S2 can be created by a method other than the method shown in FIG. 1 (,).

FIG. 1(b) shows another embodiment of the area discrimination circuit.

Fig. 2 ω) When a signal point enters area a2, ROM
All you have to do is write in the ROM so that the output of the A/1) converter 11 and 12 is sent to the output of the A/1) converter 11 and 12.

Output of the converters 9 and 10 4. Since it is the same as D and 9, it is used as the input of the EX-OR circuit 19.
', 10 output glue, ,Dl, may be used.

FIG. 3 shows an embodiment of the imaginary part weight pair control circuit 2□, in which quadrant discrimination signals D1p, D1 . and the error signal E, , E.

and a conventionally used imaginary part weight pair control circuit 2,'' which sends weighted control signals of ■±l, ■±, , , , , , 11 in response to quadrant discrimination signals D1, D19, and position discrimination. Signal S1. Receiving area discrimination signal S2, ■±2', ■
±1'.

An imaginary part weight pair control circuit 2□' according to the present invention which sends a weight control signal of r, o/, and an imaginary part weight pair control circuit 2
It consists of a selection circuit 57 for selecting either the output of □' or the output of 2'. Imaginary part weight pair control circuit 2
□' are delay circuits 34 to 44, EX-OR circuit 45
50, an AND circuit 51, and D-type flip-flops 52-56. next.

The operation of the imaginary part weight pair control circuit 21' according to the present invention will be explained.

The output of the EX-OR circuit 45 is a quadrant discrimination signal.

The delay circuits 34 to 38 delay the signal by one time slot. Position determination signal S1. The area discrimination signal s2 is delayed by three time slots corresponding to the center tag, and the signal 1EX-OR circuit 46 of E3 and D1 to D5 is
By performing an EX-OR operation with .about.50, the phase error signal of each tap can be obtained. The outputs of the EX-OR circuits 46 to 50 receive information from all signal points and include jitter components, so the outputs of the EX-OR circuits 46 to 50 are read by the D-type flip-flops 52 to 56 as 520UT signals. If this is done, the phase error signal can be extracted only from the signal points that fall within the area a in FIG. 2(a), and the jitter component can be reduced.

Here, the weighted control and control signals which are the outputs of the D-type flip-flops 52 to 56, ■±1', ■Sat, /, ■,
/ has the advantage of not depending on the input level, but since the phase error signal is detected from a part of the input modulated wave signal, it is different from the imaginary number of the conventional configuration, which detects it from all signal points. Weighted control signal engineering by section weight vs. control circuit 2T''
1. ■±2'', ■Jitter increases slightly compared to o'.

Therefore, when the two-wire digital demodulation system is in a transition period,
That is, transversal equalizer], , AGC circuit]
, 5 , 16 , Weighted control signal ■±1', ■±2', ■o' only when the carrier synchronization circuit is not operating normally
During normal operation, that is, when a normal signal is input to the input terminal of the A/1 converter 9, 100, the selection circuit 57 selects the conventional weighted control signals (1/2), (2) ±2', (2). ′
It is better to use , and this becomes more effective as the number of multivalues increases. However, this selection circuit 57 is not an essential element of the present invention.

The selection circuit 57 in FIG.
Weighted control signal ■± by circuit 2□' according to the present invention in /
2', ■±1', and the control signal C0
NT is a signal indicating that this digital demodulation system is in a stable operating state, as shown in FIG. 1(a).

A stable operating state is indicated when the alarm signal ALM in the AGC circuits 15, 1.6 and the asynchronous detection circuit 30 disappears. The configuration of the carrier synchronization circuit in FIG. The output of the 2 selection circuit 27 is completely the same as the output of the selection circuit 57 including the switching function. Therefore, when the phase error signal according to the present invention is used in a carrier synchronization circuit, the phase error signal according to the present invention is shown in FIG.
) or the output I of the selection circuit 57 in FIG. is input to the voltage controlled oscillator 32 via the low-pass filter 31, a carrier-locked loop is formed. The above-mentioned asynchronous detection circuit 30 has a loop that is non-□
C13) A means for detecting a change in loop impedance is well known to detect a synchronized state. still,
The operation of the carrier wave synchronization logic circuit 29 is as follows.

For example, one of the two inventors published JP-A-57-131151.
This is detailed in the ``carrier regeneration circuit'' proposed in the publication, so it will be omitted here.

FIG. 4(a) is a specific example of the AGC circuit 15.16, and the fourth
Figure (b) is an explanatory diagram of the operation, and 58 is a logic circuit (LOG).
IC), 59 is a flip-flop, and 60 is a detection circuit (DET). The output S of the logic circuit 58 is shown in FIG.
When the signal point enters the region C8 in b), the attenuator 7,
8 control signals. Here, when the AGC circuit is not operating normally, that is, when the signal point enters only either area C or C1, the free rough 0f 0
The output of the 7'59 becomes DC level. In addition, during normal operation, the data signal is at a higher mark rate. Therefore, the configuration is such that the detection circuit 60 detects the difference between the two and sends out an alarm signal ALM in the event of an abnormality.

Returning to the explanation in Figure 3, there are 8 weighted control signals ■±2'.

■±/, r, and 7 hold true regardless of the input level.

Weighted control signal ±2", ■±1//, ■: depends on the input level, so when switching between the two, please refer to Figure 1 (
a) It is essential to check whether the AGC circuit in K is operating normally, and therefore the 1 selection circuit 5
7 control signal C0NTK AGC circuit], 5, -
1.6 alarm signal ALM is used. Furthermore, the selection circuit 57
In addition to the above, information from the bit error rate characteristics can also be used for the control signal C0NT.

! 5 is an embodiment using a baseband transversal equalizer, 61 is a baseband transversal equalizer, 62 is a transversal filter, 6
3 is a real part weighting control circuit.

64 is an imaginary part weighting control circuit. The feature of this embodiment is the operation of the imaginary part weighting control circuit 64, and the other features are the conventional circuit or those explained in FIG.

FIG. 6 shows a specific example of the imaginary part weighting control circuit 64.
4" is a conventionally used imaginary part weighting control circuit,
65-82 are delay circuits, 83-94 are EX-OR circuits,
95 is an AND circuit, 96 to 105 are D type flip-flop circuits, and 1-06 and 1.07 are selection circuits. The difference from FIG. 3 is that the control signal is P.

This is the only part where the Q channel is created independently.

The present invention can be explained using 64QA using FIG. 1(a) and FIG.
I have explained the case where it is applied to the M system.

The present invention is not limited to (4QAM (4P)
It is applicable to a multilevel quadrature amplitude modulation system of SK) or higher.

It is only necessary to change the storage capacity of 33. Furthermore, although the transversal equalizer with 5 taps has been described in FIG.

〔Effect of the invention〕

As described above, according to the present invention, even if there is common-mode interference distortion in the transmission system, it is possible to realize an imaginary part control circuit that independently converges without being affected by it. A digital demodulation system that can improve the equalization capability limit value can be provided.

[Brief explanation of drawings]

FIG. 1(a) is an embodiment of the digital demodulation system applied to 64 QAM waves according to the present invention, FIG. 1(b) is another embodiment of the area determination circuit, and FIG.
M-wave signal arrangement, FIG. 2(b) is an explanatory diagram of the operation of FIG. 1(b). Figure 3 shows an example of the imaginary part control circuit, and Figure 4 (,) shows the AG
A specific example of the C circuit, FIG. 4(b) is an explanatory diagram of the operation of FIG. 4(a), FIG. 5 is an example using a baseband transversal equalizer, and FIG. 6 is an imaginary part weight. This is a specific example of an attached control circuit. 1 is an IF band transversal equalizer, 2R, 63 is a real part weighting control circuit, 2,164 is an imaginary part weighting control circuit, 3 is a transversal filter, 4 is a demodulator, 5 is an identification section, 6 is a Quadrature detector, 7-8 are variable resistance attenuators, 9-
14 is a converter, 15 and 16 are AGC circuits, 17 is a subtracter, and 18 is an adder. 19-23. 45-50. 83-94 are EX-OR circuits, 24. , 51, 95 are AND circuits, 25 is NA
NDAND circuit, 52 to 56, 96 to 105 are D type flip-flops, 27, 57, 106 to 107 are selection circuits, 28 is an OR circuit, 29 is a logic circuit for carrier synchronization, 30 is an asynchronous detection circuit, 31 is a low frequency 32 is a voltage controlled oscillator, 33 is a ROM. 34-44. 65-82 are delay circuits, 58 is a logic circuit +
59 is a flip-flop, and 60 is a detection circuit. 61 is a baseband transversal equalizer.

Claims (1)

[Claims] 1. A digital demodulation system that includes a demodulator and a transversal equalizer, demodulates a digital modulated wave to obtain a demodulated signal, performs multi-level discrimination, and reproduces multiple columns of data output including a main data signal, quadrant discriminating means for binary discriminating the demodulated signal to obtain a quadrant discriminating output; and position discriminating means for binary discriminating the phase shift signal obtained by shifting the phase of the demodulated signal by π/4 radians to obtain a position discriminating output. means and
region discriminating means for performing multi-value discrimination on the phase shift signal or performing a logical operation on the data output to obtain a region discriminating output; 1. A digital demodulation system, comprising: a discrimination output, a means for performing a logical operation between the position discrimination output and the area discrimination output.