JPS6239067A - Manufacture of thin film semiconductor device - Google Patents
Manufacture of thin film semiconductor deviceInfo
- Publication number
- JPS6239067A JPS6239067A JP17812485A JP17812485A JPS6239067A JP S6239067 A JPS6239067 A JP S6239067A JP 17812485 A JP17812485 A JP 17812485A JP 17812485 A JP17812485 A JP 17812485A JP S6239067 A JPS6239067 A JP S6239067A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor film
- impurity
- source
- annealing
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000010409 thin film Substances 0.000 title claims description 3
- 238000000137 annealing Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 33
- 238000000151 deposition Methods 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 2
- 239000012535 impurity Substances 0.000 abstract description 9
- 239000011521 glass Substances 0.000 abstract description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 2
- 239000003513 alkali Substances 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract 4
- 239000013078 crystal Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 15
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 238000001953 recrystallisation Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BZUDVELGTZDOIG-UHFFFAOYSA-N 2-ethyl-n,n-bis(2-ethylhexyl)hexan-1-amine Chemical compound CCCCC(CC)CN(CC(CC)CCCC)CC(CC)CCCC BZUDVELGTZDOIG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、絶縁基板上に薄膜トランジスタ（ＴＦ’ｒ
）を製作した際に、より高速で電気的特性のすぐれた動
作をする製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a thin film transistor (TF'r) on an insulating substrate.
), which operates at higher speed and with excellent electrical characteristics.
この発明は、絶縁基板上にＴＦＴＱ製作する方法におい
て、ソースとドレイン部分の不純物添加の半導体痕ヲビ
ーム了ニールすることにより、ソースとドレインでの抵
抗を減少させ、コンタクト金改善したものである。This invention is a method for manufacturing TFTQ on an insulating substrate, by beam-annealing the semiconductor traces of impurity doping in the source and drain portions, thereby reducing the resistance at the source and drain and improving the contact gold.
従来、第２図に示すように、絶縁基板上にＴＦＴｉ製作
する際に、ソース及びドレイン部分の不純物添加の半導
体ａｔビーム了ニールしなかつも〔発明が解決しようと
する問題点〕
ＴＩＦＴのソースとドレイン部分の抵抗が高く。Conventionally, when manufacturing TFTi on an insulating substrate, as shown in FIG. The resistance of the drain part is high.
コンタクトが不十分であるため、ＴＸＰＴの特性が良く
ならないという欠点があった。There was a drawback that the characteristics of TXPT were not improved due to insufficient contact.
ＴＰＴのソースとドレイン部分の不純物添加の半導体膜
を下の半導体膜が溶融しない程度にビームアニールする
ことで、ソースとドレイン部分の抵抗を減少させ、コン
タクトを改善する。By beam annealing the impurity-doped semiconductor film in the source and drain portions of the TPT to an extent that the underlying semiconductor film does not melt, the resistance of the source and drain portions is reduced and contact is improved.
第１図Ｃｂ）に示すように不純物添加の半導体装置全半
導体膜２が溶融しない程度にビームアニールすることで
、不純物添加の半導体膜３の不純物が活性化し、不純物
が半導体膜８中にやや拡散することで、比抵抗が低下し
、コンタクトが良くなる〔実施例〕
以下図面によって本発明の詳細な説明する。第１図（ハ
））Ｆｓ、、絶縁基板１上に半導体膜２を堆積し。As shown in FIG. 1Cb), by beam annealing to an extent that the entire semiconductor film 2 of the impurity-doped semiconductor device is not melted, the impurities in the doped semiconductor film 3 are activated and the impurities are slightly diffused into the semiconductor film 8. By doing so, the specific resistance is reduced and the contact is improved. [Example] The present invention will be explained in detail below with reference to the drawings. FIG. 1(c)) Fs. A semiconductor film 2 is deposited on an insulating substrate 1.
ビームアニールにより再結晶化する工程である。This is a process of recrystallization by beam annealing.
絶縁基板１の例としては２石英や凛アルカリガラスやガ
ラスの表面に絶縁物？コートしてガラスからの不純物の
拡散全防止したものなどがある。次に半導体膜２の例は
多数おるが、ここではブラダ−ｒ ＣＶ Ｄ 法１ｆＣ
Ｌる了モルブアスシリコンＣａ−日ｉ）Ｋついて説明す
る。堆積温度は室温から約８００℃の間で行い、ｌ原料
ガスはおもにシラン（Ｂｉ Ｈ＆） ヤ’） Ｓ’７７
（ｓＳｓ Ｈｓ ） ’Ｊ：便用する。An example of an insulating substrate 1 is an insulating material on the surface of 2 quartz, Rin-alkali glass, or glass. There are products that are coated to completely prevent impurities from diffusing from the glass. Next, there are many examples of the semiconductor film 2, but here, the bladder r CV D method 1fC
Let's explain about Molbuas Silicon Ca-day i)K. The deposition temperature was between room temperature and about 800°C, and the raw material gas was mainly silane (Bi H&) S'77.
(sSs Hs) 'J: To use.
また膜厚に、０．０５μ雷から０．５μ餌の間に設定す
る。次に半導体膜２のビームアニール方法について１明
する。アニール方法には、レーザや電子ビームまたはラ
ンプやヒータなどを用いる方法があるが、ここでは了ル
ゴｙレーザに使用してα−５７６ア二−ルする方法につ
いて説明する。Also, the film thickness is set between 0.05μ and 0.5μ. Next, a method of beam annealing the semiconductor film 2 will be briefly explained. Annealing methods include methods using lasers, electron beams, lamps, heaters, etc., but here a method for α-576 annealing using a laser beam will be described.
一般にプラズマｃｖｐ法で堆積したα−８ぜには、水素
ガスが金言れているため、このガス全除去スルアニール
（プレアニールンヲ行うことで後述の再結晶子ニール後
の結晶性が良くなる。ブレ丁ニール方法はα−８１中の
水素ガスが約５００℃以上で除去できることが知られて
おり、この温度まで上昇できるアニール方法であればど
の方法でも可能である。例えば真空または不活性ガス雰
囲気中で、ａ−Ｂ ｉが溶融しない程度のエネルギー密
度でアルゴンレーザビームを走査させて行うことができ
る。丁ニール条件の一例としてに、パワー１２７．ビー
ム径３４０μ岳、走査速度５ＩＭ／ｓｅｅがある。次に
再結晶アニールについて説明する。In general, α-8 deposited by the plasma CVP method requires hydrogen gas, so performing a pre-anneal to completely remove this gas improves the crystallinity after recrystallization annealing described later. It is known that the hydrogen gas in α-81 can be removed at a temperature of about 500°C or higher, and any annealing method that can raise the temperature to this temperature is possible.For example, in a vacuum or an inert gas atmosphere, This can be done by scanning an argon laser beam with an energy density that does not melt a-Bi. An example of the following conditions is a power of 127, a beam diameter of 340μ, and a scanning speed of 5IM/see.Next, Recrystallization annealing will be explained.
前記のプレアニールと同様に、真空または不活性ガス雰
囲気中でアルゴンレーザを用いて、α−Ｂ（が溶融する
パワー密度で行う。アニール条件の一例としては、パワ
ー１３Ｗ、ビーム径１３０μｍ、走査速度５０ｃｍ／ｓ
ｅａがある。Similar to the pre-annealing described above, it is performed using an argon laser in a vacuum or an inert gas atmosphere at a power density that melts α-B. An example of the annealing conditions is a power of 13 W, a beam diameter of 130 μm, and a scanning speed of 50 cm. /s
There is ea.
第１図の）ｔｊｌ、−半導体膜２上に不純物添ｍｃｔ半
導体膜８を堆積し、パターニングした優、不純物添加の
半導体膜３を半導体膜２が溶融しない程度のエネルギー
密度でビームアニールする工程である。不純物添加の半
導体１８の例としては、ＰチャネルＴＦＴｉ製作する場
合にはＰ童の不純物を添刀口してア＋とする。Ｎチャネ
ルＴＰＴの場合には、Ｘ型の不純物を添加してＮ＋とす
る。ここでは前述したプラズマｃｖＤ法により、Ｎ十〇
−ｓ４を堆積する場合全説明する。堆積温度は室温から
約３００℃の間で原料ガス１ｊｊ３ｉＨ，に０．１チか
ら１チのホスフィン（”ｓ）ｅ添加して、０．０２μ常
から０゜１μ情の間で堆積する。ｔたｒ十〇−ｇ４の場
合には、ｓｅｍ、にジボラン（Ｂ＊ Ｈｓ ）ｋ添加し
て堆積する。次にフォトリソ技術により不純物添刀口の
半導体［３ｉＴＦＴのソースとドレイン部分のみ残し、
他ｔエツチングして除去する。次の工程は、不紳物添の
口の半導体膜３ｔ−ビームアニールして、比抵抗を下げ
、コンタクトを改善する工程である。アニール条件例と
しテハ０丁ルアルゴンザを用いて、前述のプレレーザア
ニールと同一条件で行うことができる。In the process of depositing an impurity-doped MCT semiconductor film 8 on the semiconductor film 2 (FIG. 1) and patterning it, the impurity-doped semiconductor film 3 is beam annealed at an energy density that does not melt the semiconductor film 2. be. As an example of the impurity-doped semiconductor 18, when manufacturing a P-channel TFTi, a P-type impurity is added to form A+. In the case of an N-channel TPT, an X-type impurity is added to make it N+. Here, the entire case of depositing N10-s4 by the plasma CVD method described above will be explained. The deposition temperature is between room temperature and about 300° C., and 0.1 to 1 t of phosphine (s)e is added to the raw material gas, and the deposition is carried out at a thickness of 0.02 μ to 0.1 μ. In the case of r10-g4, diborane (B*Hs) is added to SEM and deposited.Next, the impurity-doped semiconductor [3i, leaving only the source and drain portions of the TFT, is deposited using photolithography.
Remove by etching. The next step is to perform t-beam annealing on the semiconductor film 3 with an additive to lower the resistivity and improve the contact. As an example of the annealing conditions, the annealing can be performed under the same conditions as the pre-laser annealing described above, using a TEHA 0-tonal laser gonza.
第１図（Ｃ）は、前記半導体膜２上にゲート絶Ｒ膜４を
形成し、さらにゲート電極５．ドレイン電極、ソース電
極７を形成する工程を示す図面である。ゲート絶Ｒ膜４
の例は、酸化ケイ素（８ｉ０ｚ］や窒化ケイ素（ｓｉＮ
２）などがある、ここではｓｕｍ、の堆積方法について
説明する。プラズマＯＶＤ法金用いて、原料ガスには、
おもにｓ６Ｈ，とＮＨ′、’ｉ使って０．２ｐｍ、から
０．Ｓｔｔｍ間で堆積する。ゲート絶縁層４の膜厚や膜
質は。In FIG. 1C, a gate isolation film 4 is formed on the semiconductor film 2, and a gate electrode 5. 7 is a drawing showing a process of forming a drain electrode and a source electrode 7. FIG. Gate isolation R film 4
Examples include silicon oxide (8i0z) and silicon nitride (siN).
2), etc. Here, the deposition method of sum will be explained. Using the plasma OVD method, the raw material gas is:
Mainly s6H, and NH', 'i using 0.2pm, to 0. Deposited between Sttm. What is the thickness and quality of the gate insulating layer 4?
ＴＦ’Ｔ設計値や特性によって変えることができる。次
にソースとドレイン部分のコンタクトホールと７オトリ
ソ技術で形成した後に、ゲート電極５、ドレイン電極６
．ソース電極７ｔ−形成する工程について説明する。堆
積方法の例としては、各種スパッタ法や蒸着法などがあ
り、材料にもＡｔ−５４，Ｍ（、−ｓｓ、ｗ−ｓ４など
の金属シリサイドがある。−例には、マグネトロンスパ
ッタ法でＡｚ−ｓ＜金０．４μｍから１μｍの間で堆積
する方法がある。It can be changed depending on the TF'T design value and characteristics. Next, after forming contact holes for the source and drain portions 7 using otolithography, a gate electrode 5 and a drain electrode 6 are formed.
．． The process of forming the source electrode 7t will be explained. Examples of deposition methods include various sputtering methods and vapor deposition methods, and materials include metal silicides such as At-54, M(, -ss, and w-s4). -s<gold There is a method of depositing between 0.4 μm and 1 μm.
この発明は、前述の例で説明したように、ＴＦＴ製作時
に、ドレインとソース部分の不純物添加の半導体膜３ｔ
−ビームアニールすることにより。As explained in the above example, the present invention is advantageous in that when manufacturing a TFT, the semiconductor film 3t is doped with impurities in the drain and source portions.
- By beam annealing.
第２図に示した従来のＴＰＴに比べ、比抵抗が低下し、
コンタクトが改善されるため、ＴＰＴの特性が良くなる
という効果がある。Compared to the conventional TPT shown in Figure 2, the specific resistance is lower,
Since the contact is improved, there is an effect that the characteristics of TPT are improved.
第１図（ω〜（Ｃ）は本発明のＴＦ’Ｉ’の製造工程順
の断面図、第２図は従来のＴＰＴの断面図であ７１゜１
、。絶縁基板、 ２．。半導体膜
８、、不純物添加の半導体膜
３１ 、。ビームアニールしない不純物添加の半導体膜
４゜、絶縁膜 ６゜、ゲートＩＥ極６０．ドレイ
ン電極 ７．、ソース電極 」牡出願人 セイコー電子
工業株式会社
代理人 弁理士 最 上 務
ＴＰＴの類造工程啼−■図
第１図Fig. 1 (ω to (C) is a cross-sectional view of the manufacturing process of TF'I' of the present invention, and Fig. 2 is a cross-sectional view of a conventional TPT.
,. Insulating substrate, 2. . Semiconductor film 8, impurity-doped semiconductor film 31. Impurity-doped semiconductor film without beam annealing: 4°, insulating film: 6°, gate IE electrode: 60°. Drain electrode 7. , Source Electrode” Applicant: Seiko Electronic Industries Co., Ltd., Patent Attorney, Mutsumi Mogami TPT Manufacturing Process – ■Figure 1
Claims (1)
前記半導体膜を結晶化する工程と、前記半導体膜上に不
純物添加の半導体膜を堆積し、ソースとドレイン領域を
パターニング後、前記不純物添加の半導体膜をビームア
ニールする工程と、前記半導体膜上にゲート絶縁膜を形
成し、前記不純物添加の半導体膜と前記ゲート絶縁膜上
にソース電極とドレイン電極及びゲート電極を形成する
工程とから成る薄膜半導体装置の製造方法。A step of depositing a semiconductor film on an insulating substrate and crystallizing the semiconductor film by beam annealing, depositing an impurity-doped semiconductor film on the semiconductor film, patterning source and drain regions, and then depositing the impurity-doped semiconductor film on the semiconductor film. A thin film semiconductor device comprising the steps of beam annealing the semiconductor film, forming a gate insulating film on the semiconductor film, and forming a source electrode, a drain electrode, and a gate electrode on the impurity-doped semiconductor film and the gate insulating film. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17812485A JPS6239067A (en) | 1985-08-13 | 1985-08-13 | Manufacture of thin film semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17812485A JPS6239067A (en) | 1985-08-13 | 1985-08-13 | Manufacture of thin film semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6239067A true JPS6239067A (en) | 1987-02-20 |
Family
ID=16043069
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17812485A Pending JPS6239067A (en) | 1985-08-13 | 1985-08-13 | Manufacture of thin film semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6239067A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6352883B1 (en) | 1991-02-22 | 2002-03-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6458200B1 (en) | 1990-06-01 | 2002-10-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for fabricating thin-film transistor |
-
1985
- 1985-08-13 JP JP17812485A patent/JPS6239067A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6458200B1 (en) | 1990-06-01 | 2002-10-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for fabricating thin-film transistor |
| US6740547B2 (en) | 1990-06-01 | 2004-05-25 | Semiconductor Energy Laboratory Co., Ltd. | Method for fabricating thin-film transistor |
| US7018874B2 (en) | 1990-06-01 | 2006-03-28 | Semiconductor Energy Laboratory Co., Ltd. | Method for fabricating thin-film transistor |
| US6352883B1 (en) | 1991-02-22 | 2002-03-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6717180B2 (en) | 1991-02-22 | 2004-04-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
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