JPS6238339Y2 - - Google Patents

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Publication number
JPS6238339Y2
JPS6238339Y2 JP4608279U JP4608279U JPS6238339Y2 JP S6238339 Y2 JPS6238339 Y2 JP S6238339Y2 JP 4608279 U JP4608279 U JP 4608279U JP 4608279 U JP4608279 U JP 4608279U JP S6238339 Y2 JPS6238339 Y2 JP S6238339Y2
Authority
JP
Japan
Prior art keywords
resonator
subtracter
adder
semiconductor
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP4608279U
Other languages
Japanese (ja)
Other versions
JPS55146722U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4608279U priority Critical patent/JPS6238339Y2/ja
Publication of JPS55146722U publication Critical patent/JPS55146722U/ja
Application granted granted Critical
Publication of JPS6238339Y2 publication Critical patent/JPS6238339Y2/ja
Expired legal-status Critical Current

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  • Networks Using Active Elements (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Description

【考案の詳細な説明】 本考案はイコライザ回路装置に関するもので、
特性の改善を図ることを目的とするものである。
[Detailed description of the invention] This invention relates to an equalizer circuit device.
The purpose is to improve the characteristics.

たとえばこの種のイコライザ回路装置として、
第1図のように差動増幅器1、共振子2(21,
22〜2n)、利得調整抵抗3(31,32,〜
3n)、抵抗4,5で形成した場合、すなわち共
振子2の入力インピーダンス特性を増幅器1で直
接合成するようにした場合、利得調整抵抗3によ
る最大,最小値での特性は満足するものが得られ
る。しかし中間から最少変化位置での特性が悪
く、多周波ポイントのグラフイツクイコライザで
は全帯域のレベルコントローラと化してしまう傾
向にある。その原因は抵抗4,5に対して共振子
2の入力インピーダンスの与える利得の最大増減
値を利得調整抵抗3の合成値が制限する形にな
り、したがつて共振子2のインピーダンスに対し
て利得調整抵抗3の抵抗値を大きくしなければな
らない。したがつて抵抗3は共振子2に対し直列
に入る関係で特性を悪化させている。
For example, as this type of equalizer circuit device,
As shown in Fig. 1, a differential amplifier 1, a resonator 2 (21,
22~2n), gain adjustment resistor 3 (31, 32, ~
3n), when the resistors 4 and 5 are formed, that is, when the input impedance characteristics of the resonator 2 are directly synthesized by the amplifier 1, the characteristics at the maximum and minimum values obtained by the gain adjustment resistor 3 are obtained. It will be done. However, the characteristics from the middle to the minimum change position are poor, and a graphic equalizer with multiple frequency points tends to become a level controller for the entire band. The reason for this is that the combined value of the gain adjustment resistor 3 limits the maximum gain increase/decrease given by the input impedance of the resonator 2 with respect to the resistors 4 and 5. The resistance value of the adjustment resistor 3 must be increased. Therefore, the resistor 3 is placed in series with the resonator 2, which deteriorates the characteristics.

また第2図に示すように入出力間に減算器6,
加算器7を設け、さらに第1図の利得調整抵抗
3,共振子2に相当する利得調整抵抗8,共振子
9でもつて形成した場合、減算器6の出力とゲイ
ン調整用抵抗8との間に共振子9すなわちイコラ
イザ部を設ける関係上、使用する共振子9として
はLCRの共振回路または同調増幅回路を使用し
なければならない。LCRの共振回路は構成的に
外部から影響を受けやすいと共に低い周波数に使
用するLに問題がある。また同調増幅回路は回路
構成が複雑であり構成素子も多くなる欠点があ
る。
In addition, as shown in Fig. 2, a subtractor 6,
When the adder 7 is provided, and the gain adjustment resistor 3 shown in FIG. Since a resonator 9, that is, an equalizer section is provided in the resonator 9, an LCR resonant circuit or a tuned amplifier circuit must be used as the resonator 9. The LCR resonant circuit is structurally susceptible to external influences, and there is a problem with L used at low frequencies. Further, the tuned amplifier circuit has a disadvantage that the circuit configuration is complicated and the number of constituent elements is large.

さらに第3図イ,ロのようにオペアンプを用い
た半導体共振子を使用したくても同共振子の共振
インピーダンスZonは半導体共振回路の入力イン
ピーダンス(入力端子とアース間)で作用するた
めに使用することができない。
Furthermore, even if you want to use a semiconductor resonator using an operational amplifier as shown in Figure 3 A and B, the resonant impedance Zon of the resonator is used to act as the input impedance (between the input terminal and ground) of the semiconductor resonant circuit. Can not do it.

本考案はこのような欠点を除去したもので、以
下第4図の一実施例により説明する。ここで6,
7,8,81,82は第2図の場合と同じであ
る。異なるのは101,102として半導体共振
子を使用し、半導体共振子用電源11の中点Nを
半導体共振子10の共通ラインとして減算器6の
出力回路に接続し、同共振子10を電源11を含
めフローテイング状態にしている点である。すな
わち共振子10の電源を減算器6,加算器7とは
別の電源とし、入力端子と共通ライン間の入力イ
ンピーダンスが共振特性をもつ半導体共振子を使
用できるようにしている。
The present invention has been made to eliminate such drawbacks, and will be described below with reference to an embodiment shown in FIG.
7, 8, 81, and 82 are the same as those in Fig. 2. The difference is that semiconductor resonators are used as 101 and 102, the midpoint N of the semiconductor resonator power supply 11 is connected to the output circuit of the subtractor 6 as a common line for the semiconductor resonator 10, and the resonator 10, including the power supply 11, is in a floating state. In other words, the power supply for the resonator 10 is a separate power supply from the subtractor 6 and adder 7, and a semiconductor resonator with a resonance characteristic in the input impedance between the input terminal and the common line can be used.

したがつて利得調整抵抗8の抵抗値を共振子イ
ンピーダンスに影響をおよぼさないように小さく
できるためにグラフイツクなイコライザ特性が得
られる。
Therefore, the resistance value of the gain adjustment resistor 8 can be made small so as not to affect the resonator impedance, so that graphic equalizer characteristics can be obtained.

上記実施例より明らかなように本考案によれば
半導体共振回路を用いることができ、任意のイコ
ライザ特性に設定することができる。
As is clear from the above embodiments, according to the present invention, a semiconductor resonant circuit can be used and any equalizer characteristics can be set.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図はそれぞれ従来のイコライ
ザ回路装置の結線図、第3図イ,ロは半導体共振
回路の結線図、第4図は本考案の一実施例による
イコライザ回路装置の結線図である。 6……減算器、7……加算器、8……利得調整
抵抗、10……半導体共振子、11……電源。
1 and 2 are connection diagrams of conventional equalizer circuit devices, FIG. 3 A and B are connection diagrams of semiconductor resonant circuits, and FIG. 4 is a connection diagram of an equalizer circuit device according to an embodiment of the present invention. be. 6...Subtractor, 7...Adder, 8...Gain adjustment resistor, 10...Semiconductor resonator, 11...Power source.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入出力端子間に減算器と加算器とを直列接続
し、上記減算器と加算器の両入力端子間に利得調
整用抵抗を設けると共に入力を上記抵抗に、共通
ラインを上記減算器の出力側に接続した半導体共
振回路を設け、かつ上記減算器および加算器の電
源とは異なる半導体共振回路の専用電源の中点を
上記共通ラインに接続したことを特徴とするイコ
ライザ回路装置。
A subtracter and an adder are connected in series between the input and output terminals, a gain adjustment resistor is provided between the input terminals of the subtracter and the adder, the input is connected to the resistor, and the common line is connected to the output side of the subtracter. An equalizer circuit device comprising: a semiconductor resonant circuit connected to the subtracter and the adder; and a midpoint of a dedicated power source for the semiconductor resonant circuit, which is different from the power sources for the subtracter and the adder, connected to the common line.
JP4608279U 1979-04-06 1979-04-06 Expired JPS6238339Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4608279U JPS6238339Y2 (en) 1979-04-06 1979-04-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4608279U JPS6238339Y2 (en) 1979-04-06 1979-04-06

Publications (2)

Publication Number Publication Date
JPS55146722U JPS55146722U (en) 1980-10-22
JPS6238339Y2 true JPS6238339Y2 (en) 1987-09-30

Family

ID=28925546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4608279U Expired JPS6238339Y2 (en) 1979-04-06 1979-04-06

Country Status (1)

Country Link
JP (1) JPS6238339Y2 (en)

Also Published As

Publication number Publication date
JPS55146722U (en) 1980-10-22

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