JPS6237952A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6237952A
JPS6237952A JP17716385A JP17716385A JPS6237952A JP S6237952 A JPS6237952 A JP S6237952A JP 17716385 A JP17716385 A JP 17716385A JP 17716385 A JP17716385 A JP 17716385A JP S6237952 A JPS6237952 A JP S6237952A
Authority
JP
Japan
Prior art keywords
terminals
package
terminal
bit
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17716385A
Other languages
Japanese (ja)
Inventor
Shutaro Nanbu
修太郎 南部
Tadashi Tanida
谷田　忠
Kaoru Muramatsu
村松　薫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP17716385A priority Critical patent/JPS6237952A/en
Publication of JPS6237952A publication Critical patent/JPS6237952A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To improve high frequency characteristics, by using a circular or elliptical package, in which five or more terminals are arranged in a radial pattern. CONSTITUTION:A lead 5 is provided between a terminal 1 and a terminal 2. A lead 6 is provided between a terminal 3 and a terminal 4. In this package, the length from a chip fixing part 31 to terminals 32-36, which are to be wire- bonded, becomes almost equal to the length from the end of a plastic sealing part to the end of the lead. The length becomes considerably small, as 1-1.5mm. Therefore, high frequency characteristics can be improved.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、高周波ＩＣに適した小形の低コストのパッケ
ージを有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device having a small, low-cost package suitable for high-frequency ICs.

従来の技術 近年の半導体の進歩に伴い、半導体を封入する２、、−
７ パッケージにおいても、技術進歩がめざましい。Conventional technology With recent advances in semiconductors, semiconductors are encapsulated2, -
7. Technological progress in packaging is also remarkable.

特に、半導体の場合低コストが要求されるため、安価な
、プラスチック、パッケージが多用されている。In particular, in the case of semiconductors, low cost is required, so cheap plastics and packages are often used.

このようなプラスチック、パッケージの製作工程を概説
する。捷ず、コムと称する連続した複数個のパッケージ
に対応する導体パターン上に、チップをダイスボンドし
、チップ上の電極パッドとパッケージのリード端子とな
る導体パターン間に金属細線をワイヤボンドする。しか
る後、プラスチック（樹脂）を圧入してチップ周辺をお
おう。We will outline the manufacturing process for such plastics and packages. The chip is die-bonded onto a conductor pattern corresponding to a plurality of consecutive packages called a comb without being separated, and a thin metal wire is wire-bonded between the electrode pad on the chip and the conductor pattern which will become the lead terminal of the package. After that, plastic (resin) is press-fitted to cover the area around the chip.

プラスチック硬化後コムの不要な導体パターンを切り離
し、端子に、半田ｄｉｐや折り曲げなどの加工を施して
、完成する。After the plastic hardens, the unnecessary conductor patterns of the comb are cut off, and the terminals are processed by solder dipping, bending, etc. to complete the process.

このような、プラスチックパッケージの形状には、様々
なものがあるが、端子板によって、はぼ形状が決ってい
る。第４図ａ、ｂに示すような長方形の両側、あるいは
片側に端子のでだもの、第４図ｃ、ｄに示すように円あ
るいはだ円のプラスチックから、放射状に端子が設けら
れたものに犬３・、−１ 別できる。乙の端子数は下は２本からかなりの多数の端
子数を有するもの捷であるが、Ｃの形状のものけ、４本
以下のものしかない。これは、４本以上の端子数になる
と、乙の形状の方が実装」−使すやすいだめと思われる
。There are various shapes of such plastic packages, but the dovetail shape is determined by the terminal board. A rectangular body with terminals on both sides or one side as shown in Figures 4a and b, or a circle or oval shaped plastic with terminals radially provided as shown in Figures 4c and d. 3., -1 Can be distinguished. The number of terminals for Otsu varies from 2 to a considerably large number of terminals, but for C-shaped monoke, there are only 4 or less terminals. This is because when the number of terminals exceeds 4, the shape shown in Figure B is considered easier to implement.

発明が解決しようとする問題点 近年の半導体技術の進歩に伴い、動作速度、動作周波数
は急速に高速化、高周波化されつつある。Problems to be Solved by the Invention With recent advances in semiconductor technology, operating speeds and operating frequencies are rapidly increasing.

デバイスの動作周波数の高周波化に伴い、それを封止す
るパッケージの高周波数化に対しても、大きな要請があ
る。個別半導体（１つのＦＥＴとかトランジスタなど）
を封止するパッケージに関しては、かなりの高周数帯の
もの丑で、すでにセラミックを使ったものが商品化され
ている。第１図Ｃに示したプラスチック封止のものも、
２〜３ＧＨｚ　　付近まで使用可能なものが、すでに商
品化されている。As the operating frequency of devices becomes higher, there is also a great demand for higher frequency packages that seal the devices. Discrete semiconductor (such as a single FET or transistor)
As for the package that seals it, it has a fairly high frequency band, and one that uses ceramic has already been commercialized. The plastic-sealed one shown in Figure 1C also
Products that can be used up to around 2 to 3 GHz have already been commercialized.

しかし、複数個の半導体素子や抵抗、コンデンサなどを
集積化した。ＩＣは、捷だデバイス自身の動作周波数が
せいぜい１００ＭＨ２程度であることもあって、それ以
上の高周波ＩＣを封入するパック−７に関しては、従来
あ捷り考慮がはられれていなかった。However, multiple semiconductor elements, resistors, capacitors, etc. were integrated. Since the operating frequency of the IC device itself is approximately 100 MH2 at most, no consideration has been taken into consideration regarding the packaging 7 that encapsulates a higher frequency IC.

個別半導体用のパッケージとＩＣ用のパッケージとの相
違点は、単にリード端子（ピン）数ノ大小にある。ＩＣ
用パッケージでは、通常５端子以上の端子が必要である
。The difference between individual semiconductor packages and IC packages is simply the number of lead terminals (pins). IC
Typically, five or more terminals are required for the package.

従って、ＩＣ用のパッケージｄ：、通常図１（ｉｌｃ示
すような形状のものになるが、この場合、チップの端か
ら、パッケージの端のリード端までの長、さが、どうし
ても長くなるリードがでてくる。Therefore, IC package d: usually has a shape as shown in Figure 1 (ilc), but in this case, the length from the end of the chip to the end of the lead at the end of the package is inevitably long. It comes out.

１００ＭＨ２以下の低周波数では、その波長に比べて端
子の長さは、無視できる程短いため、あ捷り問題となら
ないが、それ以」二の高周波では、インダクタンスとし
て働いたり、あるいは、リードの浮遊容量が問題に々っ
たりする。丑だ、チップに到る捷でのり一部の長さが、
端子によって異なることも、位相差を問題とするデバイ
スの場合には問題となる。At low frequencies of 100 MH2 or less, the length of the terminal is negligibly short compared to the wavelength, so there is no problem with fraying, but at higher frequencies, it acts as an inductance or causes stray leads. Capacity is often a problem. It's a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a piece
Differences between terminals also pose a problem in devices where phase differences are an issue.

問題点を解決するための手段 ５、＜； 本発明では、上記の問題点を解決するために、５本以上
の端子を、放射状に配置したことを特徴とする円型又は
楕円型のパッケージを有する半導体装置を提供するもの
である。Means for Solving Problems 5 <; In order to solve the above problems, the present invention provides a circular or elliptical package characterized in that five or more terminals are arranged radially. The present invention provides a semiconductor device having the following.

作用 ＩＣチップの電極パッドと各パッケージ端子との間のリ
ード長が短かく、一様になるため、高周波特性の勝れた
ＩＣ用のパッケージが構成される。Since the lead length between the electrode pad of the working IC chip and each package terminal is short and uniform, an IC package with excellent high frequency characteristics is constructed.

実施例 本発明を実施例に基すいて説明する。Example The present invention will be explained based on examples.

まず、第１図に示すのは、第４図Ｃの２組の端子１と２
および４と３の間に、対向して、５，６というリードを
設けた６ピンのＩＣパッケージである。このコムパター
ン図面を第２図に示す。第２図すにチップを封入する付
近（ダム部）の拡大図を示しであるが、図から分るよう
に、このパッケージでは、チップ固定部３１から、ワイ
ヤボンドする端子３２〜３６までの長さ、および、プラ
スチック封止部の端のリード端までの長さを、はとんど
等しく、かつ１〜１・６闘とか々り短くてき６、−１ るため、４ＧＨ２（−ｊ近までの高周波ＩＧｉ封止でき
る。First, Figure 1 shows two sets of terminals 1 and 2 in Figure 4C.
It is a 6-pin IC package in which leads 5 and 6 are provided facing each other between 4 and 3. A drawing of this comb pattern is shown in FIG. Figure 2 shows an enlarged view of the area where the chip is sealed (dam part). Since the length and the length from the end of the plastic sealing part to the lead end are almost the same and are quite short, 1 to 1.6 mm, 4GH2 (-1) High frequency IGi can be sealed.

もちろん、端子５あるいは６どちらか１本をはずして、
６ピンとしても、同様の効果が可能である。Of course, remove either terminal 5 or 6,
A similar effect can be achieved even with 6 pins.

このよう々コムを用いると、樹脂封止後のコムの切断に
、従来の第４図すに示す４端子用の治具の一部を共用で
きるため、有利である。The use of such a comb is advantageous because a part of the conventional jig for four terminals shown in FIG. 4 can be used in common for cutting the comb after resin sealing.

本発明を拡張すれば、第３図に示すように、８端子のパ
ッケージも可能である。第３図すにそのダム内部のコム
パターンの略図を示す。By expanding the present invention, an 8-terminal package is also possible, as shown in FIG. Figure 3 shows a schematic diagram of the comb pattern inside the dam.

端子数が増えると、端子の引っ張り強度が低下するとい
う問題が生じる。この時は、接地端子（通常はチップを
固定する端子４）のみを太くして、他の導体リードヲ細
くすることにより、等価的な樹脂部の面積を増やすこと
により、引っ張り強度を強くできる。接地端子のみの太
さを太くするのは、高周波では特に接地インダクタンス
を小さくすることが、性能上要求されるため、この端子
を細くすると、問題が多いからである。As the number of terminals increases, a problem arises in that the tensile strength of the terminals decreases. In this case, the tensile strength can be increased by making only the ground terminal (usually the terminal 4 for fixing the chip) thicker and making the other conductor leads thinner, thereby increasing the area of the equivalent resin part. The reason why the thickness of only the ground terminal is made thicker is because performance demands that the grounding inductance be made smaller especially at high frequencies, so making this terminal thinner causes many problems.

７７、−７ 本発明を更に拡張して、更に多端子のパッケージも同様
に可能である。また、以上の説明は、プラスチック・パ
ッケージについて述べたが、セラミックパッケージを用
いても、同様のパッケージが構成できる。77,-7 It is also possible to further expand the present invention to create a multi-terminal package. Further, although the above description has been made regarding a plastic package, a similar package can be constructed using a ceramic package as well.

発明の効果 以上述べたごとく、本発明によれば、小形で高周波特性
に優れたＩＣ用のパッケージが構成でき、実用上極めて
有用である。Effects of the Invention As described above, according to the present invention, it is possible to construct an IC package that is small and has excellent high frequency characteristics, and is extremely useful in practice.

【図面の簡単な説明】[Brief explanation of the drawing]

のコムパターン平面図、第３図ａ、　　ｂは８ピンのＩ
Ｃパッケージの平面図、第４図ｆＬ　−ｄはプラスチッ
ク・パッケージの形状の平面図と側面図てあ第１図 第３図 （ＯＪン ｋ）４図 （□ｊ （Ｃ〕　　　　　　　　　イ （ｂ） ｔｄ］ （ｌｕ） 申comb pattern plan view, Figure 3 a and b are 8-pin I
Figure 4 fL-d is a plan view of the C package; ] (lu) Monkey

Claims (3)

【特許請求の範囲】[Claims] （１）５本以上の端子を、放射状に配置した円型又は楕
円型のパッケージを有する半導体装置。(1) A semiconductor device having a circular or elliptical package in which five or more terminals are arranged radially. （２）十文字方向に端子のでた４端子パッケージの対向
する２組の相隣る端子間に、対向する２本の端子を設け
て、６端子としたことを特徴とする特許請求の範囲第１
項記載の半導体装置。(2) Claim 1, characterized in that two opposing terminals are provided between two pairs of opposing terminals of a four-terminal package with terminals extending in the cross direction, resulting in six terminals.
1. Semiconductor device described in Section 1. （３）十文字方向に端子のでた４端子パッケージの４組
の相隣る端子間に、２組の対向する２本の端子を設けて
、８端子としたことを特徴とする特許請求の範囲第１項
記載の半導体装置。(3) Two sets of two opposing terminals are provided between four sets of adjacent terminals of a four-terminal package with terminals extending in a cross direction, resulting in eight terminals. The semiconductor device according to item 1.
JP17716385A 1985-08-12 1985-08-12 Semiconductor device Pending JPS6237952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17716385A JPS6237952A (en) 1985-08-12 1985-08-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17716385A JPS6237952A (en) 1985-08-12 1985-08-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6237952A true JPS6237952A (en) 1987-02-18

Family

ID=16026281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17716385A Pending JPS6237952A (en) 1985-08-12 1985-08-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6237952A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980753A (en) * 1988-11-21 1990-12-25 Honeywell Inc. Low-cost high-performance semiconductor chip package
JPH03151659A (en) * 1989-11-09 1991-06-27 Toshiba Corp Outside-surrounding equipment of semiconductor device
US5701234A (en) * 1995-12-06 1997-12-23 Pacesetter, Inc. Surface mount component for selectively configuring a printed circuit board and method for using the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980753A (en) * 1988-11-21 1990-12-25 Honeywell Inc. Low-cost high-performance semiconductor chip package
JPH03151659A (en) * 1989-11-09 1991-06-27 Toshiba Corp Outside-surrounding equipment of semiconductor device
US5701234A (en) * 1995-12-06 1997-12-23 Pacesetter, Inc. Surface mount component for selectively configuring a printed circuit board and method for using the same

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