JPH03283557A - Lead frame and semiconductor device using it - Google Patents

Lead frame and semiconductor device using it

Info

Publication number
JPH03283557A
JPH03283557A JP8136190A JP8136190A JPH03283557A JP H03283557 A JPH03283557 A JP H03283557A JP 8136190 A JP8136190 A JP 8136190A JP 8136190 A JP8136190 A JP 8136190A JP H03283557 A JPH03283557 A JP H03283557A
Authority
JP
Japan
Prior art keywords
tab
lead frame
package
semiconductor chip
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8136190A
Other languages
Japanese (ja)
Inventor
Kanako Sawada
佳奈子 澤田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP8136190A priority Critical patent/JPH03283557A/en
Publication of JPH03283557A publication Critical patent/JPH03283557A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the position dependency of coefficient of stress magnification in the peeling face of a tab as well as the maximum value of coefficient of stress magnification and to suppress package cracks by arranging a tab constituted with smooth curve form. CONSTITUTION:A lead frame is constituted of a tab 1a shaped elliptical or circular, suspension pins 2, and a plurality of leads 3. The tab 1a has a shape formed not by straight lines as a rectangle, but by smooth curves as ellipse or circle. Hereupon, the sizes of the tab 1a and a semiconductor chip 4 are so set that at least part of the edge of the tab 1a is covered with the semiconductor chip 4. Terminal electrodes of the semiconductor chip 4 are connected to leads 3 with bonding wires 5. That is, shaping the tab 1a elliptical and setting sizes so that part of its edge is covered with the semiconductor chip 4 yield resin-sealed type semiconductor IC devices which hardly develop package cracks.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、リードフレームに半導体素子を搭載し樹脂封
止して構成される半導体装置に係り、特にそのリードフ
レームの改良に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device constructed by mounting a semiconductor element on a lead frame and sealing it with resin, and particularly relates to an improvement of the lead frame. Regarding.

(従来の技術) 樹脂封止型の半導体装置では、組立てにリードフレーム
が用いられる。
(Prior Art) In resin-sealed semiconductor devices, lead frames are used for assembly.

第6図に従来の樹脂封止型の半導体装置の一例を一部切
開して示す。
FIG. 6 shows an example of a conventional resin-sealed semiconductor device with a portion cut away.

リードフレームは形状が長方形である素子搭載部(以下
、タブと称する)1b1吊リビン2、複数のリード3等
から構成されている。
The lead frame includes an element mounting portion (hereinafter referred to as a tab) 1b1 having a rectangular shape, a hanging rib 2, a plurality of leads 3, and the like.

半導体素子4はタブ1bにダイボンド剤により接着され
て搭載されている。半導体素子の電極部とリード3との
電気的接続はAuあるいはAfIなどを材料とするボン
ディングワイヤ5を介して行われる。素子の封止は、フ
ィラー、添加剤、そしてエポキシ樹脂などの樹脂等を成
分とする熱硬化性モールド剤を170℃程度の温度で加
熱して素子をその中に埋め込んでパッケージ6を成型し
て完成する。
The semiconductor element 4 is adhered and mounted on the tab 1b using a die bonding agent. Electrical connection between the electrode portion of the semiconductor element and the lead 3 is performed via a bonding wire 5 made of Au, AfI, or the like. The device is encapsulated by heating a thermosetting molding agent containing fillers, additives, and resins such as epoxy resin at a temperature of about 170° C., embedding the device therein, and molding the package 6. Complete.

このように形成されたパッケージ6はエポキシ樹脂が吸
湿性を持つため、エポキシ樹脂とリードフレームとの接
合界面に水分が蓄積される。
Since the epoxy resin in the package 6 formed in this manner has hygroscopic properties, moisture accumulates at the bonding interface between the epoxy resin and the lead frame.

パッケージ6を基板に表面実装する際に、通常200℃
以上という高い温度のもとで行われる。
When surface mounting the package 6 on the board, the temperature is usually 200°C.
It is carried out at high temperatures.

その結果、半導体素子4とパッケージ樹脂と間に比べて
、密着性の悪いタブ1bの裏面とパッケージ樹脂との間
には、この過程で接合界面に蓄積した水が蒸発して発生
する水蒸気圧によって剥離が生じる。この剥離が進行す
ると最終的には全面剥離となりその形はタブと同形とな
ることが確認されている。
As a result, there is a gap between the back surface of the tab 1b and the package resin, which has poor adhesion compared to between the semiconductor element 4 and the package resin, due to the water vapor pressure generated by the evaporation of water accumulated at the bonding interface during this process. Peeling occurs. It has been confirmed that as this peeling progresses, the entire surface eventually peels off and its shape becomes the same as that of the tab.

この全面剥離に伴いタブ1b周辺の強度が最も弱い箇所
にはパッケージクラック7が発生する。
Along with this whole surface peeling, package cracks 7 occur in the area around the tab 1b where the strength is the weakest.

パッケージクラック7は一度それが発生するとパッケー
ジクラック7の先端部8を起点として第4図破線のよう
に円状に広がっていく。
Once the package crack 7 occurs, it spreads in a circular shape as shown by the broken line in FIG. 4, starting from the tip 8 of the package crack 7.

剥離の先端でのパッケージクラック7の進行のしやすさ
は、応力拡大係数と樹脂の破壊靭性値できまる。すなわ
ち、応力拡大係数が破壊靭性値より大きくなるとパッケ
ージクラックが進行する。
The ease with which the package crack 7 develops at the tip of the peeling is determined by the stress intensity factor and the fracture toughness value of the resin. That is, when the stress intensity factor becomes larger than the fracture toughness value, package cracking progresses.

次に剥離面の形が長方形のときの応力拡大係数とパッケ
ージクラックの関係を説明する。
Next, the relationship between the stress intensity factor and package cracks when the peeled surface is rectangular in shape will be explained.

第7図(a)、(b)、(c)は剥離面の形が長方形で
あるときの応力拡大係数の位置依存性を説明するための
図である。第7図(a)は剥離面に垂直な方向に−様な
内圧7が働いて剥離部8が形成されて全面剥離が生じる
様子を示す図である。
FIGS. 7(a), (b), and (c) are diagrams for explaining the position dependence of the stress intensity factor when the peeled surface has a rectangular shape. FIG. 7(a) is a diagram showing how a negative internal pressure 7 acts in a direction perpendicular to the peeling surface, forming a peeling portion 8 and causing full-scale peeling.

第7図(b)は基板面上方から見た剥離面である。FIG. 7(b) shows the peeled surface seen from above the substrate surface.

X軸、y軸は長方形の中心を通りそれぞれ長辺と短辺に
平行な直線である。θは長方形の中心と辺上の一点を結
んだときにできる直線とX軸とがなす角度で、辺上の点
と1対1に対応している。
The X-axis and y-axis are straight lines passing through the center of the rectangle and parallel to the long and short sides, respectively. θ is the angle formed between the X-axis and a straight line connecting the center of the rectangle and a point on the side, and corresponds one-to-one with the point on the side.

長方形の辺上の各位置での応力拡大係数は対称性からX
軸、y軸によって区分される四つの領域のうち、一つだ
けを考えれば十分であるので0″≦θ≦90°の範囲で
考える。第7図(C)はそのような範囲での剥離面に働
く応力拡大係数の分布を示す図である。この図が示すよ
うに応力拡大係数は位置により異なり、θ−90″のと
き、すなわち、長辺中央部で最大となっている。したが
って、破壊靭性値に位置依存性がなければ剥離面の長辺
中央部からパッケージクラックが起こりそこを起点とし
て次々にパッケージクラックが進行する。
Due to symmetry, the stress intensity factor at each position on the side of the rectangle is
Since it is sufficient to consider only one of the four regions divided by the axes and y-axes, we will consider the range of 0''≦θ≦90°.Figure 7 (C) shows the peeling in such a range. It is a diagram showing the distribution of the stress intensity factor acting on a surface. As this diagram shows, the stress intensity factor varies depending on the position, and is maximum at θ-90'', that is, at the center of the long side. Therefore, if the fracture toughness value has no position dependence, package cracks will occur from the center of the long side of the peeled surface and will progress one after another from that point as a starting point.

このように従来構造のリードフレームでは、全面剥離に
伴うパッケージクラックの発生により半導体装置の信頼
性の低下するという問題があった。
As described above, the lead frame having the conventional structure has a problem in that the reliability of the semiconductor device decreases due to the occurrence of package cracks due to peeling of the entire surface.

(発明が解決しようとする課題) 以上のように従来の樹脂封止したパッケージを表面実装
する際に、タブ裏面とパッケージ樹脂間に全面剥離が起
こり、応力拡大係数の大きいタブの部分を起点にしてパ
ッケージクラックが発生するという問題があった。
(Problems to be Solved by the Invention) As described above, when surface-mounting a conventional resin-sealed package, peeling occurs across the entire surface between the tab backside and the package resin, starting from the portion of the tab where the stress intensity factor is large. There was a problem that package cracks occurred.

本発明は、パッケージクラックが起こり難い樹脂封止型
半導体装置用のリードフレームを提供することを目的と
している。
An object of the present invention is to provide a lead frame for a resin-sealed semiconductor device in which package cracks are less likely to occur.

本発明はまた、そのようなリードフレームを用いた信頼
性の高い樹脂封止型の半導体装置を提供することを目的
としている。
Another object of the present invention is to provide a highly reliable resin-sealed semiconductor device using such a lead frame.

[発明の構成] (課題を解決するための手段) 上記の目的を達成するために、本発明に係るリードフレ
ームでは、滑らかな曲線形状をもって構成されたタブを
有することを特徴とする。
[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the lead frame according to the present invention is characterized by having a tab configured with a smooth curved shape.

また、本発明に係る半導体装置は、滑らかな曲線形状を
もって構成されたタブを有するリードフレームと、この
リードフレームのタブに搭載された+′−導体素子と、
この半導体素子を樹脂封止したパッケージとを有するこ
とを特徴とする。
Further, a semiconductor device according to the present invention includes a lead frame having a tab configured with a smooth curved shape, a +'- conductor element mounted on the tab of the lead frame,
It is characterized by having a package in which the semiconductor element is sealed with resin.

この場合リードフレームにおいては、タブの縁辺の少く
とも一部が半導体素子により覆われるように、タブの大
きさを設定することが望ましい。
In this case, in the lead frame, it is desirable to set the size of the tab so that at least a portion of the edge of the tab is covered by the semiconductor element.

(作用) 本発明によれば、タブの剥離面での応力拡大係数の位置
依存性が小さくなり、かつ応力拡大係数の最大値が小さ
くなって、パッケージクラックが起こり難くなる。
(Function) According to the present invention, the positional dependence of the stress intensity factor on the peeled surface of the tab is reduced, and the maximum value of the stress intensity factor is also reduced, making it difficult for package cracks to occur.

(実施例) 以下、本発明の詳細を図示の実施例によって説明する。(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

第1図は本発明の一実施例に係るリードフレムの平面図
である。
FIG. 1 is a plan view of a lead frame according to an embodiment of the present invention.

リードフレームの材料は例えば、4270イまたは銅合
金(銅を主成分としてFe、Sn、Pを目的に応じて1
〜数種類を数%添加したもの)などである。本実施例で
は素材に関しては特別な制限はなく、これらの素材の中
から各種ICの特性、組立て方法、パッケージ形状など
を考慮して選択使用すれば良い。
The material of the lead frame is, for example, 4270I or copper alloy (copper as the main component, Fe, Sn, P depending on the purpose).
~ several types added in several percentages). In this embodiment, there is no particular restriction on the material, and it is sufficient to select and use one of these materials in consideration of the characteristics of various ICs, assembly method, package shape, etc.

このリードフレームは形状が楕円または円であるタブl
as吊りビン2および複数のリード3等から構成されて
いる。このリードフレームが従来のそれと異なる点はタ
ブ1aの形状にある。タブ1aは、従来の長方形などの
ように直線で形成される形状でなく、楕円または円など
のように滑らかな曲線で形成される形状としている。
This lead frame has tabs that are oval or circular in shape.
It is composed of an AS hanging bottle 2, a plurality of leads 3, and the like. This lead frame differs from conventional lead frames in the shape of the tab 1a. The tab 1a does not have a straight line shape such as a conventional rectangle, but has a smooth curved shape such as an ellipse or circle.

第2図は、第1図のリードフレームを用いた本発明の一
実施例に係る半導体装置を一部切開して示したものであ
る。形状が長方形または正方形である半導体素子4はリ
ードフレームのタブ1aに搭載されている。
FIG. 2 is a partially cutaway view of a semiconductor device according to an embodiment of the present invention using the lead frame shown in FIG. A semiconductor element 4 having a rectangular or square shape is mounted on a tab 1a of a lead frame.

ここで、タブ1aと半導体素子4の大きさは、少くとも
タブ1aの縁辺の一部が半導体素子4によって覆われる
ように設定されている。半導体素子4の端子電極とリー
ド3の間は、ボンディングワイヤ5により接続されてい
る。こうしてリードフレームに一体化された半導体素子
4は、従来同様に、熱硬化性エポキシ樹脂等を用いた樹
脂パッケージ6により封止されている。
Here, the sizes of the tab 1a and the semiconductor element 4 are set so that at least a part of the edge of the tab 1a is covered by the semiconductor element 4. The terminal electrodes of the semiconductor element 4 and the leads 3 are connected by bonding wires 5. The semiconductor element 4 integrated into the lead frame in this manner is sealed with a resin package 6 made of thermosetting epoxy resin or the like, as in the conventional case.

次に上記実施例により、パッケージクラックが生じ難く
なる理由を以下に説明する。
Next, the reason why the above embodiment makes it difficult for package cracks to occur will be explained below.

第3図(a)、(b)、(c)はタブ1aと樹脂ハラケ
ージ6の間の剥離面の形が楕円となる実施例での応力拡
大係数の位置依存性を説明する図である。第3図(a)
は基板面上面から見た剥離面でありその形は楕円である
。座標軸の選び方は第5図と同じである。第3図(b)
の実線aはそのような剥離面の場合の応力拡大係数の位
置依存性を示す図である。破線すは、実施例と同程度の
周辺長をもつ長方形タブの場合の剥離面の応力拡大係数
の位置依存性を示す。この図から分かるように剥離面の
形が楕円となる上記実施例の場合、応力拡大係数は角度
θが増すと伴に緩やかに大きくなっている。すなわち、
剥離面の形が楕円のほうが長方形の場合より位置依存性
が小さくなっている。そして、タブの周辺長が従来と同
程度であれば応力拡大係数の最大値が従来のより小さく
なる。この結果、上記実施例によれば、効果的にパッケ
ージクラックを抑制することができる。
FIGS. 3(a), 3(b), and 3(c) are diagrams for explaining the position dependence of the stress intensity factor in an embodiment in which the shape of the peeling surface between the tab 1a and the resin cage 6 is elliptical. Figure 3(a)
is the peeled surface seen from the top of the substrate surface, and its shape is an ellipse. The method of selecting the coordinate axes is the same as in FIG. Figure 3(b)
A solid line a is a diagram showing the position dependence of the stress intensity factor in the case of such a peeled surface. The broken line indicates the position dependence of the stress intensity factor of the peeled surface in the case of a rectangular tab having a peripheral length comparable to that of the example. As can be seen from this figure, in the case of the above embodiment in which the peeled surface has an elliptical shape, the stress intensity factor gradually increases as the angle θ increases. That is,
The position dependence is smaller when the peeled surface is elliptical than when it is rectangular. If the peripheral length of the tab is about the same as that of the conventional one, the maximum value of the stress intensity factor will be smaller than that of the conventional one. As a result, according to the above embodiment, package cracks can be effectively suppressed.

以上のことからパッケージクラックが最も起こり難くい
タブの形は応力拡大係数の位置依存性が無い円であるこ
とが分かる。
From the above, it can be seen that the shape of the tab in which package cracks are least likely to occur is a circle in which the stress intensity factor has no position dependence.

第3図(c)は剥離面の形が楕円のとき、その面積をパ
ラメータとして応力拡大係数の位置依存性を示した図で
ある。実線Cは実線aより面積が小さいときの応力拡大
係数の示すカーブである。
FIG. 3(c) is a diagram showing the position dependence of the stress intensity factor using the area as a parameter when the peeled surface has an elliptical shape. The solid line C is a curve showing the stress intensity factor when the area is smaller than the solid line a.

この図から分かるように応力拡大係数の位置依存性を示
すカーブの形それ自体はあまり嚢わらないが、面積か小
さい方が応力拡大係数は小さい。すなわち、タブの面積
をできる限り小さくすることが、パッケージクラックを
抑制する上で好ましいことが分かる。
As can be seen from this figure, the shape of the curve showing the position dependence of the stress intensity factor is not very accurate, but the smaller the area, the smaller the stress intensity factor. That is, it can be seen that it is preferable to make the area of the tab as small as possible in order to suppress package cracks.

以上のようにして本実施例によれば、タブ1aの形を楕
円とし、かつ半導体素子4によりタブ1aの縁辺の一部
が覆い隠されるようにそれらの大きさを設定することに
より、パーツケージクラックが起こり難い樹脂封止型の
半導体集積回路装置を提供することができる。
As described above, according to this embodiment, the shape of the tab 1a is made into an ellipse, and the size of the tab 1a is set so that a part of the edge of the tab 1a is covered with the semiconductor element 4. It is possible to provide a resin-sealed semiconductor integrated circuit device that is less prone to cracking.

なお、タブ1aと半導体素子4の関係は上記実施例に限
定されるものではない。例えば、半導体素子上面から見
たタブ1aと半導体素子4の関係を第4図(a)〜(d
)の中から、適当に選ぶことができる。図中、(a)と
(b)は半導体素子4によりタブ1a仝体が覆い隠され
る場合の例を示し、(c)と(d)は半導体素子4によ
りタブ1aの縁辺の一部が覆い隠される場合の例を示し
ている。更に、タブ1aが半導体素子4により覆われな
い場合でも、第5図(a)〜(d)に示すようにタブ1
aの形状を、半導体素子の形状に合わせてできるだけ滑
らかにすることにより、はぼ同様の効果が期待できる。
Note that the relationship between the tab 1a and the semiconductor element 4 is not limited to the above embodiment. For example, FIGS. 4(a) to (d) show the relationship between the tab 1a and the semiconductor element 4 when viewed from the top surface of the semiconductor element.
) can be selected appropriately. In the figures, (a) and (b) show an example in which the body of the tab 1a is covered by the semiconductor element 4, and (c) and (d) show an example in which a part of the edge of the tab 1a is covered by the semiconductor element 4. An example of a case where it is hidden is shown. Furthermore, even when the tab 1a is not covered by the semiconductor element 4, the tab 1a is not covered with the semiconductor element 4 as shown in FIGS.
By making the shape of a as smooth as possible to match the shape of the semiconductor element, a similar effect can be expected.

[発明の効果] 以上述べたように本発明によれば、簡単な構成で樹脂パ
ッケージの強度を高くすることができ、基板に樹脂封止
半導体装置を表面実装する際に発生するパッケージクラ
ックの発生を抑制することができる。これにより、信頼
性の高い半導体装置を得ることができる。
[Effects of the Invention] As described above, according to the present invention, the strength of the resin package can be increased with a simple configuration, and the occurrence of package cracks that occur when surface mounting a resin-sealed semiconductor device on a substrate can be avoided. can be suppressed. Thereby, a highly reliable semiconductor device can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例に係るリードフレームの平面
図、 第2図はこのリードフレームを使用した半導体装置の一
実施例を示す図、 第3図(a)〜(c)は剥離面の形が楕円のときの応力
拡大係数の位置依存性を説明する図、第4図(a)〜(
d)はタブと半導体素子との種々の大きさと形の関係を
示す図、 第5図(a)〜(d)は更に他の実施例のタブと半導体
素子の関係を示す図、 第6図は従来の半導体装置を示す図、 第7図は剥離面の形が長方形のときの応力拡大係数の位
置依存性を説明する図である。 1a・・・タブ(素子搭載部)、2・・・吊りピン。 3・・・リード、4・・・半導体素子、5・・・ボンデ
ィングワイヤ、6・・・パッケージ。
Fig. 1 is a plan view of a lead frame according to an embodiment of the present invention, Fig. 2 is a diagram showing an embodiment of a semiconductor device using this lead frame, and Figs. 3 (a) to (c) are exfoliation. Figures 4(a) to 4(a) are diagrams explaining the position dependence of the stress intensity factor when the surface shape is an ellipse.
d) is a diagram showing the relationship between various sizes and shapes of the tab and the semiconductor element; FIGS. 5(a) to (d) are diagrams illustrating the relationship between the tab and the semiconductor element of other embodiments; FIG. 7 is a diagram showing a conventional semiconductor device, and FIG. 7 is a diagram illustrating the position dependence of the stress intensity coefficient when the peeled surface has a rectangular shape. 1a...Tab (element mounting part), 2...Hanging pin. 3... Lead, 4... Semiconductor element, 5... Bonding wire, 6... Package.

Claims (4)

【特許請求の範囲】[Claims] (1)滑らかな曲線形状をもって構成された素子搭載部
を有することを特徴とするリードフレーム。
(1) A lead frame characterized by having an element mounting portion configured with a smooth curved shape.
(2)滑らかな曲線形状をもって構成された素子搭載部
を有するリードフレームと、 このリードフレームの素子搭載部に搭載された半導体素
子と、 この半導体素子を樹脂封止したパッケージと、を有する
ことを特徴とする半導体装置。
(2) A lead frame having an element mounting part configured with a smooth curved shape, a semiconductor element mounted on the element mounting part of this lead frame, and a package in which this semiconductor element is sealed with resin. Characteristic semiconductor devices.
(3)前記素子搭載部の形状は、円または楕円としたこ
とを特徴とする請求項2記載の半導体装置。
(3) The semiconductor device according to claim 2, wherein the element mounting portion has a shape of a circle or an ellipse.
(4)素子搭載部の縁辺の少くとも一部が前記半導体素
子により覆われるように、前記素子搭載部と前記半導体
素子との大きさを設定したことを特徴とする請求項2記
載の半導体装置。
(4) The semiconductor device according to claim 2, wherein the size of the element mounting part and the semiconductor element is set so that at least a part of the edge of the element mounting part is covered by the semiconductor element. .
JP8136190A 1990-03-30 1990-03-30 Lead frame and semiconductor device using it Pending JPH03283557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8136190A JPH03283557A (en) 1990-03-30 1990-03-30 Lead frame and semiconductor device using it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8136190A JPH03283557A (en) 1990-03-30 1990-03-30 Lead frame and semiconductor device using it

Publications (1)

Publication Number Publication Date
JPH03283557A true JPH03283557A (en) 1991-12-13

Family

ID=13744199

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8136190A Pending JPH03283557A (en) 1990-03-30 1990-03-30 Lead frame and semiconductor device using it

Country Status (1)

Country Link
JP (1) JPH03283557A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009013294A (en) * 2007-07-04 2009-01-22 Sumitomo Bakelite Co Ltd Resin composition and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009013294A (en) * 2007-07-04 2009-01-22 Sumitomo Bakelite Co Ltd Resin composition and semiconductor device

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