JPS6237750A - Address generating circuit - Google Patents

Abstract

PURPOSE:To prevent the destruction of data and to minimize the degree of the discontinuance of data in a read mode by detecting the difference between a write address and a read address and adding the read address with +alpha as the write address when the difference between both addresses exceeds a prescribed level. CONSTITUTION:As the difference between the write and read addresses to be given to a RAM 5, a reset terminal 32 is added with alpha. The slight difference of frequency is produced between the clocks of the write and read address generating circuits 2 and 1. Thus the difference between the write and read addresses is gradually increased. When this difference exceeds a set level, an address load signal is produced from an address difference detecting circuit 3. Then the read address is loaded to the write address generating circuit 2. As a result, the difference of both addresses is reset to +alpha and the discontinuous period of the read data is only a period alpha.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an address generation circuit for writing and reading data to and from a memory.

BACKGROUND OF THE INVENTION In recent years, digital signal processing technology has made progress, and various fields are being digitized. Here, a compact disc (hereinafter referred to as CD) player will be taken as an example, and a conventional address generation circuit used therein will be explained.

Various methods have been developed for recording and reproducing digital signals to prevent errors in the data signals.
Among them, cross, interleaved, and Reed-Solomon codes are used.

This code is an error detection and correction code in which 8 symbols of parity are added to 24 data symbols (1 symbol - 8 bits) and time axis operations called scrambling and interleaving are performed. When decrypting,
It is necessary to solve this scrambling and interleaving, but this is usually done using random access memory (RA
This is done by generating an address (referred to as M) according to a rule and reading the data.

FIG. 3 shows a block diagram of the EFM demodulation and error correction portion of the CD player. In FIG. 3, 10 is an EFM demodulation circuit, 20 is an error correction circuit, 30 is a RAM, and 40 is a frequency dividing circuit. Also, in Fig. 4, among the error correction circuits,
1 shows a block diagram of a conventionally used address generation circuit. In FIG. 4, 50 is a circuit that divides the frequency of a clock oscillated by a crystal, 60 is a write address generation circuit, 70 is a read address generation circuit, and 90 is a selector that selects a read address and a write address.

This will be explained below with reference to the figures.

A signal detected from a CD by an optical pickup is waveform-shaped to a digital level, and at the same time, a bit clock synchronized with each data is extracted.

Since this data has undergone modulation called EFM, it is demodulated by a demodulation circuit in FIG. 3, and then sent to the error correction circuit 20. The error correction circuit first writes data into the RAM 30, and this write address is generated in synchronization with a clock generated by passing the previously generated bit clock through the frequency divider 20. Further, reading of the RAM is performed in synchronization with a clock generated by a crystal and passed through a frequency divider 50. It is desirable that the clock for writing to the RAM and the clock for reading are the same, but the extracted clock is not stable and contains jitter due to disk eccentricity and uneven rotation. On the other hand, on the reproduction side, since reading must be performed at a fixed timing, reading is performed using a clock generated from a crystal, rather than using the same clock as for writing. FIG. 5 is a diagram showing the state of memory addresses. It is assumed that the memory has a so-called ring memory configuration in which the address advances from the lowest to the highest in both reading and writing, and returns to the lowest when it reaches the highest address.

In FIG. 5, the shaded area indicates a data entry area, and the white area indicates an area where data has already been written. In FIG. 5, the difference between both addresses is α, indicating that both reading and writing are performed normally. (Reference document, JP-A-58-123253) Problems to be Solved by the Invention However, in the above configuration, as the timing deviation between the read and write clocks accumulates,
There is a possibility that a state may occur in which data is written on top of data before it is read, or a state in which data is read out so quickly that it is read out before it is written.

If this happens, the data will be corrupted and the CD will be damaged.
There was a problem in that a large abnormal noise was generated during playback.

In view of the above-mentioned problems, the present invention is designed to prevent data destruction and minimize data discontinuity during reading.

Means for Solving the Problems In order to solve the above problems, the address generation circuit of the present invention includes a circuit that detects the difference between the addresses on the writing side and the reading side, and a circuit that detects the difference between the addresses on the write side and the read side, and a circuit that detects the difference in address when the difference exceeds a certain number. , is equipped with a circuit that does not set the read address to 0, but sets only the write address to the read address +α.

Operation The present invention uses the above-described configuration to detect the difference between the write and read addresses, and when the difference exceeds a certain number, the write address is set to the read address + α, so that the data becomes invalid. is limited to the maximum α range, and abnormal noise can also be reduced.

Embodiment Hereinafter, one embodiment of the address generation circuit of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. 1 is a read address generation circuit, and 2 is a write address generation circuit, each having a clock input terminal of 11.21, and generates an address from an output terminal of 12.22 in synchronization with this clock. The input clocks have slightly different frequencies between 1 and 2. In addition, the write address generation circuit 2 has a built-in circuit that increases the address by +α, and the address load control terminal 2
4. It also has an address input terminal 23, a read address is loaded from 23 with a load signal 24, and outputted from 22 in synchronization with the clock 21. 3 is a circuit for detecting a difference between a read address and a write address, and is provided with a load signal output terminal 31 and an external reset terminal 32 for forcibly outputting a load signal. Reference numeral 6 denotes a memory circuit, which is composed of a selection circuit 4 for both addresses and a RAM 5.

The operation of the above circuit will be explained below.

The difference between the addresses for writing and reading data to the RAM 5 is due to the addition of input to the recess/node terminal 32.
It is assumed that α is set. Both writing and reading are synchronized with the input clock of the respective address generation circuits, but since the two clocks have slightly different frequencies,
The difference between the two addresses gradually widens. The difference between these addresses is
When the set tolerance value is exceeded, an address load signal is output from the address difference detection circuit 8, and the read address is loaded into the write address generation circuit. As a result, both addresses return to the address difference of +α, and the discontinuous period of read data becomes only the period α.

FIG. 2 shows another embodiment of the present invention, in which the read address generation circuit 1 is a hexadecimal counter 101, the write address generation circuit 2 is a load type hexadecimal counter 2, and a ten α adder 202. , a circuit consisting of EOR, AND, and OR gates is used as the address difference detection circuit. When the old GH power is applied to the external reset terminal 32, the load signal input terminal 24 becomes lligh, the read side address is loaded into the counter 201, and the adder 202 increments it by +α, and the write address becomes the read address "-α". Become. If the writing and reading timings match, the counter 101. 20
1 operate with clocks 11 and 21, respectively. However, if the timing deviates, the address difference detection circuit 3 (configured to detect an address difference of ±2 in the figure) causes the load signal input terminal 24 to become the old GH, and the external reset input The same behavior as when adding
The write address becomes the read address 10α.

In FIG. 2, the adder 202 is connected after the counter 201, but the address load terminal 23 and the counter 20
Even if it is connected during 1, the same operation will occur.

In this case, addition is not made every time an address is generated, but every time it is loaded, so the number of additions is reduced compared to FIG. 2, and faster operation can be achieved.

Effects of the Invention As described above, according to the present invention, data discontinuity can be minimized even when RAM is read and written using two clocks with slightly different frequencies, and a CD player can When used, abnormal noise can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an address generation circuit in one embodiment of the present invention, FIG. 2 is a block diagram showing an address generation circuit in another embodiment of the invention, and FIG. 3 is a block diagram showing an error correction section of a CD player. FIG. 4 is a block diagram showing a conventional address generation circuit, and FIG. 5 is a state diagram showing the address state of the memory. 1... Read address generation circuit, 2...
...Write address generation circuit, 3...Address difference detection circuit, 4...Selector, 5...
...RAM, 6...Memory circuit, 11.21.
...Clock input terminal, 12.22...
Address generation terminal, 31...address, load signal output terminal, 32...address, reset external input terminal. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 1 Part 2 /θl・
・ /2 side counter 20g ・−/・ 2ρ2, each adding book

Claims (1)

[Claims] a memory circuit for temporarily storing data; a first address generation circuit that generates a read address for the memory in synchronization with a clock; and a write address for the memory in synchronization with a clock different from that of the first address generation circuit. comprising a second address generation circuit that generates an address and a circuit that detects a difference between the addresses generated by both circuits,
An address generation circuit characterized in that when the difference between the addresses exceeds a certain value, the address generated by the second address generation circuit is set to the address generated by the first address generation circuit + α (arbitrary integer). .