JP2001202692A - Address data detector and disk device having the detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect address data from other address block without being adversely affected by a damaged address block while detecting the address data from plural address blocks. SOLUTION: The detector is provided with a first clock generating section which generates a clock S3 that sets the detection timing of address data of a first address block 7, a second clock generating section which generates a clock S5 that sets the detection timing of address data of a second address block 8, a first address data detecting section 21 which detects the address data from the block 7 based on the clock S3 and a second address data detecting section 22 which detects the address data from the block 8 based on the clock S5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting address data from a data block sequence in which address data indicating position information on a recording medium is recorded a plurality of times in a data block composed of a predetermined number of data units. The present invention relates to an address data detecting device and a disk device having the same.

[0002]

2. Description of the Related Art In recent years, disks as recording media, for example, optical disks, have been used for various purposes. Recording and reproduction of information on a disk by a disk device are generally performed in units of data blocks called sectors. In order to enable such recording and reproduction, the recording area of the disk is divided into a number of sectors, and at the beginning of each sector, an area for writing address data specifying the sector, that is, an address area is provided. I have.
In this area, address data is written in advance in the initial state of the disk or during manufacture of the disk. At the time of recording / reproducing on a disk, a predetermined sector is specified by reading the address data.

As described above, in the method of specifying a predetermined sector based on the address data of the address area arranged at the head of the sector, if an error occurs in the address area and the address data cannot be read, even if the address area cannot be read, the data area may be read. Even if there is no error, in the worst case, the entire sector becomes unusable. In this case, not only does the usable area of the disk decrease, but also recorded data cannot be reproduced. For this reason, it is necessary to reduce the bit error rate on the disk and increase the reliability.

On the other hand, in recent years, the amount of data to be handled has been dramatically increased in various fields using a disk, and it is desired to increase the recording capacity of the disk. In order to increase the recording capacity of a disk, it is necessary to record data on the disk at a high density. However, performing this high-density recording increases the data error rate. In this case, a failure in reading the address data is likely to occur, and as a result, as described above, there is a problem that the probability that the entire sector cannot be used increases.

Therefore, as a method of reducing the number of times that the data cannot be detected in the address area, a method of recording the address data in the same sector a plurality of times is disclosed in, for example, Japanese Patent Application Laid-Open No. H10-163,873.
No. 589,673. Hereinafter, this type of method will be described.

FIG. 3 shows an example of an address area of an optical disk on which address data is recorded a plurality of times. In the figure, one address area is provided with two address blocks, that is, first and second address blocks 7, 8 (ID1, ID2).

In FIG. 1, reference numeral 1 denotes a clock mark (C
M), and are arranged at a predetermined interval for generating a reproduction clock. Here, the PLL (Phase Lock Loop) is locked to the clock mark 1 and
A configuration of a so-called external clock system for generating a reproduction clock is used.

The address area has a sector mark (SM).
2, the address mark (AM) 3, the sector address number 4, the duplication order number (ID number) 5, and the error detection signal (CRC) 6.

The sector mark 2 indicates the head of a data block. The address mark 3 is formed by a special code pattern for indicating a start position of address data. The address data detection device detects the address synchronization position based on the address mark 3 and detects the address data.

Address number 4 is a data pattern indicating the position of a sector on the disk. Duplicate number 5
Indicates the position of the address block in the address area.

The error detection code 6 is generated from the address number 4 and the duplicate number 5. The error detection code 6 is a code for detecting a reading error of the address number 4 and the duplicate number 5. The error detection code 6 mainly includes C
Although an RC (Cycle Redundancy Check) code is often used, it does not need to be a CRC code. In addition, a code that can perform error correction as well as error detection may be used.

By changing the pattern of the address mark 3 for each of the address blocks 7 and 8 instead of the ID number 5, it is possible to detect the position of the address block in the address area. It is also possible to configure so that

In the above configuration, the probability of occurrence of an address data read error is reduced by recording address data in the same address area a plurality of times.

An optical disk device provided with a conventional address data detecting device has, for example, a configuration shown in FIG.

In FIG. 1, an optical disk 101 as a recording medium is mounted on a spindle motor 102 and rotates. The optical pickup 103 irradiates the optical disk 101 with a laser beam to read and write data on the optical disk 101 and read address data. A reproduction signal from the optical disk 101 read by the optical pickup 103 is amplified by a head amplifier 104.

The clock generation unit 105 has a PLL therein, inputs the reproduction signal passed through the head amplifier 104, and locks the PLL to the clock mark 1. The clock generation unit 105 further adjusts the phase only in a portion where an address gate signal described later is active, and generates a signal synchronized with the address data.
Then, when the address gate signal is inactive (outside the address area), the phase of the clock is held in the state at that time.

The address data output unit 106 receives the output signal of the clock generation unit 105 and the output signal of the head amplifier 104, detects address data, and outputs a result of the read error of the detected address data. The address data output unit 106 has a configuration shown in FIG.

That is, the address data output unit 106 includes a demodulation circuit 111, first and second synchronization detection circuits 112,
13, a first and a second error detection circuits 114 and 115, a decoder circuit 116, registers 117 and 118, a switching circuit 119, and a counter 120.

In FIG. 1, a demodulation circuit 111 demodulates an address signal. First and second synchronization detection circuits 112,
Reference numeral 113 performs synchronization detection on the first and second address blocks 7 and 8.

First and second error detection circuits 114 and 11
Reference numeral 5 inputs the address data and the error detection code output from the demodulation circuit 111 and performs error detection of the address data. The decoder circuit 116 outputs a correct / incorrect signal of the address data detected from the error detection results of the first and second error detection circuits 114 and 115 and a switching signal used in the switching circuit 119.

The registers 117 and 118 hold the address data read without error, respectively, and
19 is a register 117, 1 based on the switching signal.
In step 18, any one of the address data held is selected and output. The counter 120 outputs an address gate signal for estimating the positions of the first and second address blocks 7 and 8.

Next, the operation of the address data output unit 106 will be described. First, the laser beam reaches the address area of the optical disc 101, and the first synchronization detection circuit 11
2, when the first address mark 3 is detected,
The error detection circuit 114 performs error detection on the first address data. If no error is found as a result of the error detection, the detected address data 3 is held in the register 117. On the other hand, when an error is detected, it is not retained.

The same processing is performed when the second address mark 3 is detected by the first synchronization detection circuit 112. Therefore, when the second address data 3 can be read without errors, , The data in the register 117 is updated.

On the other hand, the second synchronization detection circuit 113
If the address mark 3 is detected, the second error detection circuit 115 detects an error in the second address data 3 based on the detected address mark 3. If there is no error, the second address is stored in the register 118. Data 3 is held.

The switching circuit 119 outputs the outputs of the first and second error detection circuits 114 and 115, that is, the decoder circuit 11
6 in response to the switching signal from
Output the address data 3 of the register in which is stored. Further, the decoder circuit 116 outputs an error detection result.

The counter 120 predicts the timing of the address area and outputs an address gate signal. The timing of the address area can be predicted by counting the reproduction clock since the interval between the address areas is defined in advance. That is, the counter 120 counts the prescribed count number to predict the position of the address area, activates the address gate signal (for example, at the “0” level), and outputs the signal to the clock generation unit 105.

As described above, the clock generation unit 105 adjusts the phase of the generated clock to match the phase of the address data when the address gate signal is active, that is, in the address area. Hold the phase state at that time.

In the conventional address data detecting device, address data is detected from the address blocks recorded a plurality of times in one address area as described above.

[0029]

However, the above-mentioned conventional address data detecting device has the following problems.

That is, in the conventional address data detecting device, the detection of the address is based on the premise that the address mark 3 is detected first. Therefore, if the address mark 3 cannot be detected, the address data cannot be detected.

On the other hand, as described above, when high-density recording is performed on a disk, the bit error rate increases, and the probability that the address mark 3 cannot be read increases. As a result,
The probability of occurrence of a sector whose address cannot be detected has increased.

In the conventional address data detecting device, the detection of the address data of the address block recorded in the address area a plurality of times is performed by the clock signal 1 which is the output of the clock generation unit 105 and is synchronized with the address data.
The system is running. For this reason, the phase of the clock cannot be matched with the address data due to the corruption of the data of the first address block, and so-called PLL lock loss occurs, and the clock may not be synchronized with the address data at all. obtain. In such a case,
Even if the subsequent address data is normal, it is impossible to detect the address data.

The present invention has been made in view of the above problems, and when address data of an address area is detected from a plurality of address blocks provided in one address area, any one of the address data is detected. An address data detection device and an address data detection device capable of detecting an address block or an address mark without being affected by presence / absence of address data detection in such an address block even in a situation where the address block or the address mark is damaged and cannot be read. The purpose of the present invention is to provide a disk device provided with a disk drive.

[0034]

According to the present invention, there is provided an address data detecting apparatus for detecting at least one of address data indicating the same position in each of a plurality of address blocks recorded in an address area of a recording medium. In the data detection device, first synchronization signal generation means for generating a first synchronization signal for setting a detection timing of the address data in a first address block;
A second synchronizing signal generating means for generating a second synchronizing signal for setting a detection timing of the address data in a second address block; and A first address data detecting means for detecting address data; and a second address data detecting means for detecting the address data from a second address block based on a second synchronization signal. And

According to the above configuration, the first synchronizing signal generating means generates the first synchronizing signal for setting the detection timing of the address data in the first address block, and the first address data detecting means. Detects address data from the first address block based on the first synchronization signal. Similarly, the second synchronizing signal generation means
A second synchronization signal for setting the detection timing of the address data in the address block of
Address data detecting means detects address data from the second address block based on the second synchronization signal.

As described above, in the present address data detecting device, the system of the first synchronizing signal generating means and the first address data detecting means and the system of the second synchronizing signal generating means and the second address data detecting means The address data is detected from a plurality of address blocks by independent systems.

Thus, even in one system,
For example, even if address data cannot be detected due to, for example, damage to an address block, the other system detects address data from another address block without being affected by the detection state of the one system. can do. Therefore, it is possible to reduce the occurrence of areas where address data cannot be detected, for example, sectors.

In the above address data detecting device,
The synchronization signal generating means and the address data detecting means may be provided for each of a plurality of address blocks.

According to the above configuration, the synchronizing signal generating means and the address data detecting means are provided for each of the plurality of address blocks, so that the function of reducing the occurrence of areas where address data cannot be detected can be further enhanced. Can be.

In the above address data detecting device, an address mark indicating a position of address data is provided in the address block, and in addition to the means, an address mark interpolation for interpolating the address mark based on the synchronization signal is provided. An address mark interpolating means for generating a signal, wherein the address data detecting means detects the address data based on the reproduction signal of the address mark, and when the address mark cannot be detected, the address data detecting means detects the address data based on the address data interpolating signal. A configuration for detecting address data may be employed.

According to the above arrangement, the address block is provided with the address mark indicating the position of the address data, and the address mark interpolation means performs the address mark interpolation signal for interpolating the address mark based on the synchronization signal. Generate The address data detecting means detects the address data based on the reproduction signal of the address mark, and detects the address data based on the address data interpolation signal when the address mark cannot be detected.

Thus, the address data detecting means
Even when the address mark cannot be detected due to its damage or the like, the address data can be detected based on the address data interpolation signal. Therefore, the function of reducing the occurrence of an area where address data cannot be detected can be further enhanced.

In the above address data detecting device,
The address data detecting means is further for detecting the presence or absence of an error in the detected address data, and the address mark interpolating means is provided when the address data detecting means detects that there is no error in the address data. The configuration may be such that the address mark interpolation signal in the next address block is generated based on the value indicated by the synchronization signal.

In the above address data detecting device,
The address data detection means further detects the presence or absence of an error in the detected address data, and the address mark interpolation means performs the synchronization with respect to the address data detected as having no error by the address data detection means. The configuration may be such that the address mark interpolation signal in the next address block is generated based on the value indicated by the signal (for example, when the synchronization signal is a clock, the count value of the clock counter).

According to the above configuration, the address mark interpolation signal in the next address block is generated based on the value indicated by the synchronization signal for the address data detected as having no error by the address data detection means. Address mark interpolation can be performed accurately. As a result, the address data can be detected more accurately.

In the above address data detecting device,
The address data detection means is for performing at least one of detection of the presence or absence of an error in the detected address data and correction of the error, and in addition to the means, among outputs of the plurality of address data detection means. Output switching means for selecting and outputting appropriate address data,
Address data interpolating means for generating address data to be output this time, based on address data previously output from the output switching means, when appropriate address data is not obtained as an output of the output switching means. Configuration.

According to the above arrangement, the address data detecting means performs at least one of the detection of the presence or absence of an error in the detected address data and the correction of the error, and the output switching means operates the plurality of address data detecting means. From the outputs, appropriate address data is selected and output. The address data interpolating means generates address data to be output this time based on the address data previously output from the output switching means when an appropriate address data is not obtained as an output of the output switching means.

Therefore, even when the address data cannot be obtained from the address block due to the damage of the address block, the address data can be obtained reliably. As a result, it is possible to reduce the occurrence of areas where address data cannot be detected, for example, sectors.

Any of the above address data detecting devices can be applied to a disk device using a disk as a recording medium. Such a disk device can detect an area where address data cannot be detected, for example, a sector. Can be reduced.

[0050]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1] An embodiment of the present invention will be described below with reference to FIGS. As shown in FIG. 2, the address data detecting device 10 of the present embodiment is provided in an optical disk device as a disk device.

This optical disk device includes an optical disk 11 as a recording medium, a spindle motor 12, an optical pickup 13, a head amplifier 14, first and second clock generators 15 and 16, and an address data output unit 17. Then, the address data detecting device 10
And second clock generating units 15 and 16 and an address data output unit 17.

The optical disk 11 is provided with the above-described address area shown in FIG. That is, following the clock mark 1 and the sector mark 2, first and second address blocks 7 and 8 are provided, and the first and second address blocks 7 and 8 have an address mark 3, an address number 4 and a duplication number 5. And an error detection code 6. The clock marks 1 are arranged at predetermined intervals in order to generate a reproduced clock, as described above, and here, a so-called external clock system is employed.

The optical disk 11 is mounted on a spindle motor 12 and rotates. The optical pickup 13 irradiates the optical disk 11 with a laser beam to read and write data on the optical disk 11 and read address data. The reproduction signal S1 from the optical disk 11 read by the optical pickup 13 is amplified by the head amplifier 14 and input to the first and second clock generators 15 and 16 and the address data output unit 17.

The first clock generator 15 has a PLL inside.
And the PLL is locked to the clock mark 1. Then, based on the address gate signal S2 from the address data output unit 17, the phase of the PLL output clock is adjusted in the first address block 7 (when the light beam scans the first address block 7), 1
A clock (first synchronization signal) S3 synchronized with the address block 7 is generated. On the other hand, in a portion other than the first address block 7 (when the light beam scans a portion other than the first address block 7), the phase state of the PLL output clock is adjusted without adjusting the phase of the PLL output clock. Hold.

Similarly, the second clock generation unit 16 has a PLL inside and locks the PLL to the clock mark 1. Then, based on the address gate signal S4 from the address data output unit 17, the phase of the PLL output clock is adjusted in the second address block 8, and the second
A clock (second synchronization signal) S5 synchronized with the address block 8 is generated. On the other hand, the portion other than the second address block 8 does not adjust the phase of the output clock of the PLL, and retains the state of the phase at that time.

The address data output unit 17 receives the reproduction signal S1 from the head amplifier 14 and the clocks S3 and S5 synchronized with the first and second address blocks 7 and 8, and receives the clock synchronized with the first address block 7. Using S3, detection of the address data of the first address block 7 and error detection or error correction of the address data are performed. The address data output unit 17 detects the address data of the second address block 8 and detects or corrects the error of the address data using the clock S5 synchronized with the second address block 8.

Further, the address data output section 17 outputs address gate signals S2 and S4 to the first and second clock generation sections 15 and 16. These address gate signals S2 and S4 represent the timings of the first and second address blocks 7 and 8, respectively, and are generated by counting the clocks S3 and S5. 8 is interpolated. The first and second clock generators 15 and 16
The above-described phase adjustment operation is performed based on the address gate signals S2 and S4.

The address data output section 17 has a specific configuration shown in FIG. That is, the address data output unit 17 includes a first address data detection unit (first address data detection unit) 21, a second address data detection unit (second address data detection unit) 22, and a first timing generation unit (address). Mark interpolating means) 23, a second timing generating unit (address mark interpolating means) 24, and a switching unit (output switching means) 25.

The first address data detecting section 21 receives the reproduction signal S1 from the optical disk 11 and the first address block 7
, The detection of the address data of the first address block 7 and the error detection or error correction of the address data are performed. As a result, the first address data detection unit 21 outputs the address data of the first address block 7, that is, the first address data S.
8 and a signal indicating an error detection result (whether or not the address data has been correctly detected) for the address data of the first address block 7, that is, an error detection result S9 is output to the switching unit 25.

The first timing generator 23 generates the address mark interpolation signal S6 of the first address block 7 by counting the clock S3, and supplies it to the first address data detector 21. When the first address data detection unit 21 cannot detect the address mark 3,
The address data is synchronized by using the address mark interpolation signal S6 to detect the address data. Also,
The first timing generator 23 outputs an address gate signal S2.

The second address data detecting section 22 receives the reproduction signal S1 from the optical disk 11 and the second address block 8
, The address of the second address block 8 and error detection or error correction are performed. Thereby, the second address data detection unit 2
Reference numeral 2 denotes a signal indicating an error detection result (whether or not the address data was correctly detected) for the address data of the second address block 8, ie, the second address data S10, and the address data of the second address block 8, ie, an error. The detection result S11 is output to the switching unit 25.

The second timing generation section 24 generates the address mark interpolation signal S7 of the second address block 8 by counting the clock S5, and supplies it to the second address data detection section 22. When the address mark 3 cannot be detected by the second address data detection unit 22,
The address data is synchronized by using the address mark interpolation signal S7 to detect the address data. Also,
The second timing generator 24 outputs an address gate signal S4.

In the above processing of the first and second address data detecting units 21 and 22 by the address mark interpolation signals S6 and S7, the interval between the address marks 3 is defined in advance, and the clocks S3 and S5 are changed by the defined interval. This is because the address mark 3 can be interpolated by counting.

The switching section 25 performs the first error detection based on the error detection result S 9 from the first address data detection section 21 and the error detection result S 11 from the second address data detection section 22.
First address data S from the address data detector 21
8 and the second address data S10 from the second address data detector 22 are to be output, and either one is output.

That is, the switching unit 25 outputs the one of the first and second address data S8 and S10 that has been correctly detected and the one determined based on the error detection results S9 and S10. Further, the first and second address data S8,
If it is determined that both of S10 are correct, only the first address data S8 among them is output.

The switching section 25 outputs an error detection signal together with any address data. As described above, this error detection signal is output when any address data is output (when any address data is detected).
While outputting as active (eg, “0” level), if both the first and second address data S8 and S10 cannot be detected, it outputs as inactive (eg, “1” level). Each unit that uses the address data in the subsequent stage determines whether or not the address data has been correctly read based on the error detection signal.

Next, the first timing generator 23 will be described in detail. The second timing generation unit 2
4 also has the same configuration as the first timing generation unit 23, and therefore, only the first timing generation unit 23 will be described here.

The first timing generator 23 has the configuration shown in FIG. 4 and includes a counter 31, a decoder 32 and a counter 33.

The counter 31 is for generating the address gate signal S2. A clock S3 synchronized with the first address block 7 (first address data) is input to a clock input of the counter 31, and an error detection result S9 from the first address data detection unit 21 is input to a reset terminal thereof. You. The counter 31 detects the first address data correctly, and indicates an error detection result S indicating this.
When 9 is input to the reset terminal, it is reset.

The counter 31 has a first predetermined value.
The position of the address block 7 is interpolated by counting the clock S3. For example, when the first address block 7 is provided every N clocks of the clock S3, the counter 31 counts for N clocks and outputs the count value to the decoding unit 32. The decoding unit 32 outputs the address gate signal S2 according to the count value of the counter 31. For example, the first address block 7 generates M clocks every N clocks (however,
(N> M), the address gate signal S2 is activated for M clocks.

The error detection result S9 is also input to the decoding unit 32 for the following reason. That is, in an initial state such as when the apparatus is started, the counter 31 is running independently of the position of the address block, and its count value is not synchronized with the first address block 7 at all. For this reason, the decoding unit 32 always outputs the address gate signal S2 as active, and the first clock generation unit 15 receiving the signal always pulls in the PLL so as to always detect the address data. If the address data is detected even once, the count value of the counter 31 is synchronized with the first address block 7, and thereafter, the decoding unit 32 activates the address gate signal S2 according to the count value. .

The counter 33 is for generating the address mark interpolation signal S6. Like the counter 31, the counter 33 counts a predetermined interval of the address mark 3 and outputs the address mark interpolation signal S6. .

The first timing generator 23 generates the clock S3 synchronized with the first address block 7 as described above.
, The address gate signal S2 and the address mark interpolation signal S6 are generated, so that both signals can be generated at accurate timing. This point is the same in the second timing generator 24. The second timing generator 24 counts the clock S5 synchronized with the second address block 8, thereby obtaining the address gate signal S4 and the address mark interpolation signal S7. Is output.

Since the clock S3 synchronized with the first address block 7 and the clock S5 synchronized with the second address block 8 are completely independent clocks, one of them is used for address data due to damage of the address block area or the like. Even if the phases are not synchronized, there is no effect on the other. Therefore, the address gate signal S
2, S4 and the generation of the address mark interpolation signals S6, S7 are not affected.

Next, the first address data detector 2
1 will be described in detail. Since the second address data detector 22 has the same configuration as the first address data detector 21, the first address data detector 21 is used here.
Only the following will be described.

The first address data detector 21 detects the address of the first address block 7 and detects or corrects an error, as described above. The first address data detection unit 21 has the configuration shown in FIG. 5, and includes a demodulation unit 41, an address mark (AM) detection unit 42,
An error detection unit 43 and a register 44 are provided.

The demodulation section 41 detects and demodulates address data from the reproduction signal S1 according to a predetermined method.

When demodulating address data, it is necessary to synchronize the address data, that is, to detect where the address data starts. The address mark detection unit 42 detects the address mark 3 serving as the synchronization signal, and outputs an address mark detection signal S21 to the demodulation unit 41.

The demodulation section 41 receives the address mark interpolation signal S6, and if the address mark 3 cannot be detected due to data corruption on the optical disk 11, the demodulation section 41 uses the address mark interpolation signal S6. Synchronize the address data and detect the address data.

The error detector 43 detects the presence or absence of an error in the address signal demodulated by the demodulator 41, and outputs the result as an error detection result S9. The address data demodulated by the demodulation unit 41 is stored in the register 44 and then output as the first address data S8.

As described above, when the address mark 3 cannot be detected due to data corruption on the optical disk 11, the demodulation section 41 synchronizes the address data based on the address mark interpolation signal S6, and Is detected. As a result, even if the address mark 3 cannot be detected for the above-described reason, if the subsequent data can be correctly detected, the address data can be obtained.

Since the address mark interpolation signal S6 is generated based on the clock S3 synchronized with the first address block 7 (first address data), the second address block 8 (second address data) is damaged. Thus, the PLL can be correctly interpolated without being affected by the loss of the PLL lock. The same applies to the second address data detection unit 22.

In the above configuration, the operation of the optical disk device mainly including the address data detecting device 10 will be described below.

FIG. 6 shows the waveforms of the respective units at the time of address detection in the normal state of the address data detecting device 10. The normal state is a state in which the address area of the optical disk 11 is not damaged or the like and both the first and second address blocks 7 and 8 can be detected.

In this state, when recording / reproducing on the optical disk 11, the light beam emitted from the optical pickup 13 reaches the address area of the optical disk 11 and reaches the sector mark 2. At this time, the address gate signal S2 output from the first timing generator 23 of the address data output unit 17 is in an active state ('0' level).
Becomes Note that the address gate signal S2 is generated based on the clock S3 synchronized with the first address block 7, as described above.

When the address gate signal S2 becomes active, the first clock generator 15 (see FIG. 2)
Adjusts the phase of the clock S3 so as to match the phase of the address data of the first address block 7. This clock S3 is input to the first address data detection unit 21 and the first timing generation unit 23 of the address data output unit 17 (see FIG. 1).

The first timing generator 23 having received the clock S3 uses it to generate the address mark interpolation signal S6.
(Interpolation signal of the address mark 3) is generated and supplied to the first address data detection unit 21. This address mark interpolation signal S6 is output at almost correct timing.
Since it is in the normal state now, the address mark 3 is also detected. Therefore, the first address data detection unit 21 performs synchronization based on the address mark detection signal included in the reproduction signal S1, performs demodulation of the address data and detects an error, and outputs the result to the switching unit 25.

Next, the light beam is applied to the first address block 7.
From the first address block 8 to the second address block 8,
The address gate signal S2 output from the timing generator 23 becomes inactive ('1' level). Thereby, the first clock generation unit 15 holds the state of the phase at that time.

On the other hand, due to the movement of the light beam, the address gate signal S4 output from the second timing generator 24 becomes active ('0' level) instead of the address gate signal S2. The address gate signal S4 is generated based on the clock S5 synchronized with the second address block 8, as described above.

When the address gate signal S4 becomes active, the second clock generator 16 (see FIG. 2)
Adjusts the phase of the clock S5 so as to match the phase of the address data of the second address block 8. This clock S5 is input to the second address data detector 22 and the second timing generator 24 of the address data output unit 17 (see FIG. 1).

The second timing generator 24 having received the clock S5 uses it to generate the address mark interpolation signal S7.
(Interpolation signal of the address mark 3) is generated and supplied to the second address data detection unit 22. Similarly, the address mark interpolation signal S7 is output at substantially correct timing, but since it is in a normal state, the address mark 3 is also detected. Therefore, the second address data detector 2
2 performs synchronization based on the address mark detection signal included in the reproduction signal S1, performs demodulation of the address data and detects an error, and outputs the result to the switching unit 25.

The switching unit 25 outputs error detection results S9 and S1 from the first and second address data detection units 21 and 22.
1, the first and second address data S8, S1
Of the 0s, the address data that is correctly detected is output. Note that the first and second address data S8, S1
If it is determined that both 0 are correct, for example, only the first address data S8 is output. The counter 3 of the first and second timing generators 23 and 24
1 and 33 are reset according to the error detection results S9 and S11.

Next, the operation of the address data detecting device 10 when the first address block 7 is damaged as shown in FIG. 7 will be described. In the state of FIG.
It is assumed that the first address block 7 is damaged and the address mark 3 cannot be detected in the second address block 8.

In this state, since the first address block 7 is damaged, the clock S3 to be synchronized with the first address block 7 cannot be synchronized at all. Therefore, the address gate signal S2 is not output at a correct position. Also, the address mark interpolation signal S6 cannot be interpolated at a correct position. Therefore, naturally, address data cannot be detected in the first address block 7.

However, the second address data detecting section 2 for detecting the address data of the second address block 8
2 includes a clock S synchronized with the first address block 7.
3, a clock S5 that is synchronized with the second address block 8 and is independent of the clock S5. Therefore, the clock S
Even if the synchronization of 3 is disturbed, it is not affected at all. Therefore, even if the address mark 3 of the second address block 8 is not detected, as shown in FIG. 7, the address mark interpolation signal S7 is interpolated at a correct position. As a result, the clock S5 is synchronized with the address data, and the address data can be detected.

As described above, in the address data detecting device 10 of the present embodiment, the optical disk 1 as a recording medium
In a configuration in which one address area has a plurality of address blocks, when address data is detected from an address area, an address data detection unit provided for each address block has a corresponding address block (address data). It is configured to input a synchronized clock.

Therefore, even if any address block cannot be detected due to its damage, etc.,
The address data in the address area can be detected without being affected by the detection result of the address data in the address block. As a result, occurrence of undetectable sectors of address data can be reduced.

The address data detection device 10 of the present embodiment has a configuration having two clock generation units for generating a clock synchronized with the address data. This is because recording and reproduction on the optical disk 11 having two address blocks in one address area are assumed. Therefore, for example, with respect to the optical disk 11 having four address blocks in one address area, the same function can be provided by providing four systems of clock generation units and four systems of address data detection units. Obtainable.

In the case where two or more address blocks are provided in one address area, a plurality of clocks of a system smaller than the number of address blocks and two address data detectors (for example, four address blocks) are provided. It is also possible to detect address data by a configuration having two clocks and two address data detectors for the block.

This configuration is inferior to the configuration having the same number of clocks as the address block and four address data detectors, for example, in terms of interpolation of the address mark 3. However, in comparison with the conventional configuration in which address data is detected using one system clock, the number of times address data cannot be detected can be reduced.
Moreover, the configuration can be simplified and the cost can be reduced as compared with the case where the same number of clock and address data detection units as the address area is provided.

[Embodiment 2] Another embodiment of the present invention will be described below with reference to FIGS. 2, 8 and 9. For convenience of explanation, means having the same functions as the means shown in the above-mentioned drawings are denoted by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 2, the address data detecting device 50 of the present embodiment
7, an address data output section 51 is provided. As shown in FIG. 8, the address data output unit 51 includes a first address data detection unit 21, a second address data detection unit 22, a first timing generation unit (address mark interpolation unit) 52, and a second timing generation unit ( An address mark interpolation unit) 53 and a switching unit 25 are provided.

The first timing generator 52 includes a clock S3 synchronized with the first address block 7 from the first clock generator 15 and a first address data detector 21.
, And the error detection result S9 of the second address block 8 from the second address data detection unit 22 is input. The first timing generator 52 receives these inputs and outputs an address gate signal S2 and an address mark interpolation signal S6.

Similarly, the second timing generator 53
Second address block 8 from second clock generator 16
Clock S5 synchronized with the first address data detection unit 2
1 from the error detection result S9 of the first address block 7,
And the error detection result S11 of the second address block 8 from the second address data detection unit 22 is input. The second timing generator 53 receives these inputs and outputs an address gate signal S4 and an address mark interpolation signal S7.

Next, the first timing generator 52 will be described in detail. The second timing generator 5
3 also has the same configuration as the first timing generation unit 52, so only the first timing generation unit 52 will be described here.

The first timing generator 52 has the configuration shown in FIG. 9 and includes counters 61 and 63, a decoder 32 and a counter 33.

The counter 61 is for generating the address gate signal S2. A clock S3 synchronized with the first address block 7 (first address data) is input to a clock input of the counter 61, and an error detection result S9 from the first address data detection unit 21 is input to a reset terminal thereof. You. The counter 61 detects the first address data accurately, and indicates an error detection result S indicating this.
When 9 is input to the reset terminal, it is reset.

The counter 61 has a first predetermined value.
The position of the address block 7 is interpolated by counting the clock S3. For example, when the first address block 7 is provided every N clocks of the clock S3, the counter 61 counts for N clocks, and outputs the count value to the decoding unit 32.

The load terminal of the counter 61 has an error detection result S11 from the second address data detector 22.
Is entered. When the second address data is correctly detected, and the error detection result S11 indicating this is input to the load terminal, the counter 61 is loaded with the data. The loaded values are as follows:

It is assumed that the period from when the light beam applied to the optical disk 11 reaches the first address block 7 in the next address area from the second address block 8 is L.
It is assumed that the clock (L <N) is specified. In this case, when the scanning of the light beam with respect to the second address block 8 is completed, the count value is (N
−L). Therefore, when the second address block 8 in the preceding address area can be detected correctly, the counter 61 is loaded with the count value of (NL). If the second address block 8 cannot be detected accurately, the counter 61 is not loaded with data.

The counter 61 outputs the count value to the decoding section 32. The decoding unit 32 includes a counter 61
Outputs the address gate signal S2 according to the count value.

The counter 62 is used to generate the address mark interpolation signal S6, and is reset when the first address block 7 can be detected correctly, similarly to the counter 61. When the address data of 8 is correctly detected, the value of (NL) is loaded. Then, when the count value reaches a specified value, an address mark interpolation signal S6 is output.

As described above, the first timing generator 52
Then, when the immediately preceding second address data can be accurately detected, the address gate signal S2 and the address mark interpolation signal S6 are loaded by loading the data into the address gate counter 61 and the address mark interpolation counter 62. Output. Such an operation is the same in the second timing generation unit 53,
The data is loaded into the counter when the first address block 7 is correctly detected, and the counter is reset when the second address block 8 is correctly detected.

With the above-described configuration, the address data detecting apparatus 10 according to the present embodiment detects the address mark interpolation signal S in accordance with the error detection result or the correction result of the address data.
6. Since the timing of S7 can be determined, that is, the value of the counter can be reset or loaded at the timing when the address data is correctly detected most recently, the supply of the address gate signal more accurately and the interpolation of the address mark 3 can be performed. And can be done. Therefore, more accurate address data can be detected.

[Embodiment 3] Another embodiment of the present invention will be described below with reference to FIGS. For convenience of explanation, means having the same functions as the means shown in the above-mentioned drawings are denoted by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 2, the address data detecting device 70 of the present embodiment
7, an address data output unit 71 is provided. This address data output unit 71
As shown in FIG. 8, the address data output unit 51 shown in FIG.
Is provided with an address data interpolating unit (address data interpolating means) 72 at the subsequent stage of the switching unit 25.

The address data interpolating unit 72 includes the switching unit 2
5, the first address data detector 2
1 and an error detection result S11 from the second address data detection unit 22 are input.
Then, the address data interpolating unit 72 outputs the error detection result S
9 or the address detection result indicated by the error detection result S11, if the address data is correctly detected, the address data is output. On the other hand, if the address data cannot be correctly detected, the next address is interpolated from the previous address data and output.

The address data interpolation section 72 has a configuration including a register 81, an OR circuit 82, and an adder 83, for example, as shown in FIG. Register 8
1, the address data output from the switching unit 25 is input to the OR circuit 82, and the error detection result S9 from the first address data detection unit 21 and the error detection result from the second address data detection unit 22 are input to the OR circuit 82. S11 has been input.

The register 81 stores the output from the OR circuit 82 to which the error detection results S9 and S11 indicating the detection result of the address data are input, in the first address block 7 or the second address block 2.
If it indicates that any of the address data in the address block 8 has been correctly detected, the input address data is held and output. On the other hand, when the output from the OR circuit 82 indicates that none of the address data has been correctly detected, the register 81 sets, as the address data, +1 to the previous address data by the adder 83. And output this.

With the above configuration, the present address data detecting device 70 outputs the address data when any one of the first and second address blocks 7 and 8 can be correctly detected. If the address data cannot be correctly detected, the current address data is interpolated based on the previously detected address data. This makes it possible to always obtain address data.

The address data interpolating unit 72 is provided in
The configuration is not limited to one, and may be realized by software, for example.

The address data detecting apparatus of the present invention performs only recording and reproduction or reproduction of information in units of a predetermined number of data blocks. This data block is composed of a data area and an address area indicating position information on a recording medium. The address area has a plurality of address blocks indicating the same position information, and each address block includes at least a synchronization signal, address data, an error detection signal, or an error correction signal. An address data detecting apparatus for detecting address data from a data block string having a configuration has an address detecting section corresponding to each address block for each data block, and this address detecting section detects address data of a corresponding address block. Error in the detected address data It may be configured to perform detection or correction.

In the above address data detecting device,
Each address block has a clock generator corresponding to each address block, and each address detector receives a clock from the clock generator. Based on this clock, each address detector detects address data. Alternatively, the configuration may be such that error detection or correction of the detected address data is performed.

In the above address data detecting device,
If the synchronization signal of each address block is missing,
The position of the synchronization signal may be interpolated based on the detection result of the preceding address block to detect the address data and to detect or correct an error in the detected address data.

The above-described address data detection device may be configured to select outputs of a plurality of address detection units and output address data according to the result of error detection or correction of each address block.

According to the above arrangement, when address data is detected from an address area having a plurality of address blocks, clocks synchronized with the address data of each address block are input.
Since there is an independent second address data detection unit, even if each address block cannot be detected due to damage or the like, it does not adversely affect the detection of address data in other address blocks.
Address data can be detected, and the occurrence of undetectable sectors of address data can be reduced.

The above-described address data detecting device may be configured to determine the subsequent synchronization signal interpolation timing based on the result of error detection or correction of the address data.

According to the above configuration, the interpolation timing of the synchronization signal of the address mark is determined based on the result of the error detection or correction of the address data. Can be reset or loaded. Therefore, more accurate address gate and address mark interpolation can be performed, and more accurate address data can be detected.

The above address data detecting device may be configured such that address interpolating means for obtaining an interpolated value of address data based on address data of a preceding data block is provided after an address selecting unit from a plurality of address detecting units. Good.

According to the above configuration, the interpolation of the address data is performed at the subsequent stage of the plurality of second address data detecting sections, so that even if the address data cannot be detected, the address data can be interpolated.

[0131]

As described above, the address data detecting device of the present invention detects at least one of the address data indicating the same position in each of the plurality of address blocks recorded in the address area of the recording medium. In the address data detection device, first synchronization signal generation means for generating a first synchronization signal for setting a detection timing of the address data in a first address block;
A second synchronizing signal generating means for generating a second synchronizing signal for setting a detection timing of the address data in a second address block; and The configuration includes first address data detecting means for detecting address data, and second address data detecting means for detecting the address data from a second address block based on a second synchronization signal. .

Therefore, in the present address data detecting device, the system of the first synchronizing signal generating means and the first address data detecting means and the system of the second synchronizing signal generating means and the system of the second address data detecting means are mutually different. Address data is detected from a plurality of address blocks by an independent system.

Thus, even in one system,
For example, even if address data cannot be detected due to, for example, damage to an address block, the other system detects address data from another address block without being affected by the detection state of the one system. can do. Therefore, it is possible to reduce the occurrence of areas where address data cannot be detected, for example, sectors.

In the above address data detecting device,
The synchronization signal generating means and the address data detecting means may be provided for each of a plurality of address blocks.

According to the above configuration, the synchronizing signal generating means and the address data detecting means are provided for each of the plurality of address blocks, so that the function of reducing the occurrence of an area where address data cannot be detected is further enhanced. Can be.

In the above address data detecting device, an address mark indicating a position of address data is provided in the address block, and in addition to the means, an address mark interpolator for interpolating the address mark based on the synchronization signal is provided. An address mark interpolating means for generating a signal, wherein the address data detecting means detects the address data based on the reproduction signal of the address mark, and when the address mark cannot be detected, the address data detecting means detects the address data based on the address data interpolating signal. A configuration for detecting address data may be employed.

According to the above configuration, the address block is provided with the address mark indicating the position of the address data, and the address mark interpolating means performs the address mark interpolation signal for interpolating the address mark based on the synchronization signal. Generate The address data detecting means detects the address data based on the reproduction signal of the address mark, and detects the address data based on the address data interpolation signal when the address mark cannot be detected.

As a result, the address data detecting means can
Even when the address mark cannot be detected due to its damage or the like, the address data can be detected based on the address data interpolation signal. Therefore, the function of reducing the occurrence of an area where address data cannot be detected can be further enhanced.

In the above address data detecting device,
The address data detecting means is further for detecting the presence or absence of an error in the detected address data, and the address mark interpolating means is provided when the address data detecting means detects that there is no error in the address data. The configuration may be such that the address mark interpolation signal in the next address block is generated based on the value indicated by the synchronization signal.

In the above address data detecting device,
The address data detection means further detects the presence or absence of an error in the detected address data, and the address mark interpolation means performs the synchronization with respect to the address data detected as having no error by the address data detection means. The configuration may be such that an address mark interpolation signal in the next address block is generated based on the value indicated by the signal.

According to the above configuration, the address mark interpolation signal in the next address block is generated based on the value indicated by the synchronization signal for the address data detected as having no error by the address data detection means. Address mark interpolation can be performed accurately. As a result, the address data can be detected more accurately.

In the above address data detecting device,
The address data detection means is for performing at least one of detection of the presence or absence of an error in the detected address data and correction of the error, and in addition to the means, among outputs of the plurality of address data detection means. Output switching means for selecting and outputting appropriate address data,
Address data interpolating means for generating address data to be output this time, based on address data previously output from the output switching means, when appropriate address data is not obtained as an output of the output switching means. Configuration.

According to the above arrangement, the address data detecting means performs at least one of detecting the presence or absence of an error in the detected address data and correcting the error, and the output switching means operates the plurality of address data detecting means. From the outputs, appropriate address data is selected and output. The address data interpolating means generates address data to be output this time based on the address data previously output from the output switching means when an appropriate address data is not obtained as an output of the output switching means.

Therefore, even if address data cannot be obtained from the address block due to damage to the address block or the like, the address data can be obtained reliably. As a result, it is possible to reduce the occurrence of areas where address data cannot be detected, for example, sectors.

Any one of the above address data detecting devices can be applied to a disk device using a disk as a recording medium. Such a disk device detects an area where address data cannot be detected, for example, a sector. Can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an address data output unit included in an address data detection device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of an optical disc device including an address data detecting device according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a configuration of an address area recorded on the optical disc shown in FIG. 2;

FIG. 4 is a block diagram illustrating a configuration of a first timing generation unit illustrated in FIG. 1;

FIG. 5 is a block diagram illustrating a configuration of a first address data detection unit illustrated in FIG. 1;

FIG. 6 is a timing chart showing signal waveforms of various parts of the address data detecting device shown in FIG. 1 in a normal state.

FIG. 7 is a timing chart showing signal waveforms of various parts of the address data detecting device shown in FIG. 1 when a part of address data is damaged.

FIG. 8 is a block diagram illustrating a configuration of an address data output unit in an address data detection device according to another embodiment of the present invention.

FIG. 9 is a block diagram illustrating a configuration of a first timing generation unit illustrated in FIG. 8;

FIG. 10 is a block diagram showing a configuration of an address data output unit in an address data detection device according to still another embodiment of the present invention.

FIG. 11 is a block diagram illustrating a configuration of an address data interpolation unit illustrated in FIG. 10;

FIG. 12 is a block diagram illustrating a schematic configuration of an optical disc device including a conventional address data detecting device.

FIG. 13 is a block diagram showing a configuration of an address data output unit shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Clock mark 2 Sector mark 3 Address mark 4 Address number 5 Duplication number 6 Error detection signal 7 First address block 8 Second address block 11 Optical disk (disk, recording medium) 15 First clock generation unit (First synchronization signal generation) Means 16 Second clock generation unit (second synchronization signal generation unit) 17 Address data output unit 21 First address data detection unit (First address data detection unit) 22 Second address data detection unit (Second address) Data detecting means) 23 First timing generating section (address mark interpolating means) 24 Second timing generating section (address mark interpolating means) 25 Switching section (output switching means) 31 Counter 32 Decoding section 33 Counter 41 Demodulating section 42 Address mark detection Unit 43 error detection unit 44 register 5 Address data detection device 51 Address data output unit 52 First timing generation unit (address mark interpolation unit) 53 Second timing generation unit (address mark interpolation unit) 61 Counter 62 counter 71 Address data output unit 72 Address data interpolation unit (Address data) Interpolation means) S1 reproduction signal S2 address gate signal S3 clock (first synchronization signal) S4 address gate signal S5 clock (second synchronization signal) S6 address mark interpolation signal S7 address mark interpolation signal S8 first and second address data S9 Error detection signal S10 First and second address data S11 Error detection signal

Claims (6)

[Claims] 1. An address data detecting device for detecting at least one of address data indicating the same position in each of a plurality of address blocks recorded in an address area of a recording medium, wherein the address in the first address block is First synchronizing signal generating means for generating a first synchronizing signal for setting data detection timing, and generating a second synchronizing signal for setting the address data detection timing in a second address block A first address data detecting unit that detects the address data from a first address block based on the first synchronizing signal; a second synchronizing signal generating unit that detects the address data from a first address block based on the first synchronizing signal; And second address data detecting means for detecting the address data from the second address block. An address data detecting device characterized by the above-mentioned. 2. The address data detecting device according to claim 1, wherein said synchronization signal generating means and said address data detecting means are provided for each of a plurality of address blocks. 3. The address block is provided with an address mark indicating a position of address data. In addition to the means, an address for generating an address mark interpolation signal for interpolating the address mark based on the synchronization signal is provided. Mark interpolating means, wherein the address data detecting means detects the address data based on the reproduction signal of the address mark, and detects the address data based on the address data interpolating signal when the address mark cannot be detected. 3. The address data detecting device according to claim 1, wherein: 4. The address data detecting means further comprises:
For detecting the presence or absence of an error for the detected address data, the address mark interpolation means, based on the value indicated by the synchronization signal for the address data detected as error-free by the address data detection means, 4. The address data detecting device according to claim 3, wherein an address mark interpolation signal for a next address block is generated. 5. The address data detecting means for detecting at least one of an error in the detected address data and correcting the error, and in addition to the means, a plurality of the address data detecting means. Output switching means for selecting and outputting appropriate address data from the output of the output switching means; and when the appropriate address data is not obtained as an output of the output switching means, the address data previously output from the output switching means. 3. The address data detecting device according to claim 1, further comprising address data interpolation means for generating address data to be output this time based on the address data. 6. A disk device comprising the address data detecting device according to claim 1 and using a disk as a recording medium.