JPS6237435Y2 - - Google Patents
Info
- Publication number
- JPS6237435Y2 JPS6237435Y2 JP1980065785U JP6578580U JPS6237435Y2 JP S6237435 Y2 JPS6237435 Y2 JP S6237435Y2 JP 1980065785 U JP1980065785 U JP 1980065785U JP 6578580 U JP6578580 U JP 6578580U JP S6237435 Y2 JPS6237435 Y2 JP S6237435Y2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- transistor
- rectifier circuit
- doubler rectifier
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Description
【考案の詳細な説明】
本考案はコンデンサと半導体素子とを組合せて
なる倍圧整流回路に関するものである。[Detailed Description of the Invention] The present invention relates to a voltage doubler rectifier circuit formed by combining a capacitor and a semiconductor element.
一般にコンデンサと整流素子とを組合せ低い交
流電圧から直流高電圧を得る方法として、第１図
に示すようなコツククロフト回路による倍圧整流
回路があり、その出力が比較的小電流、高電圧の
場合に有効な回路である。この場合コンデンサ４
の静電容量をＣ、段数をｎ（図においてはｎ＝
４）、端子１とアース２との間に印加される交流
電圧をVo sin wtとすると、負荷電流Ｉを供給し
ているときの端子３とアース２との間の直流出力
電圧Ｖは次式で表わされる。 Generally, as a method of obtaining high DC voltage from low AC voltage by combining a capacitor and a rectifying element, there is a voltage doubler rectifier circuit using a Kotscroft circuit as shown in Figure 1. When the output is relatively small current and high voltage, This is an effective circuit. In this case capacitor 4
The capacitance of is C, and the number of stages is n (in the figure, n=
4) If the AC voltage applied between terminal 1 and earth 2 is Vo sin wt, then the DC output voltage V between terminal 3 and earth 2 when supplying load current I is calculated by the following formula: It is expressed as
Ｖ＝2n Vo−Ｉ／ＦＣ（２／３n3＋１／２n2＋１／３
ｎ）
＝2nVo−△Vc ……(1)
右辺第１項は無負荷（Ｉ＝０）の場合の出力電
圧、第２項は負荷電流Ｉを供給するために生ずる
電圧降下分△Vcである。そして整流素子５の順
方向抵抗をＲ、端子１とアース２との間に交流電
圧を印加するための電源の抵抗をRtとすると、
これらによる電圧降下△ＶRは次式で表わされ、
直流出力電圧Ｖは
△ＶR＝３π）2/3NVo（ＮＲｔ＋Ｒ／ＶｏＩ）2/3……
(2)
この分がさらに減算されることになる。 V=2n Vo-I/FC (2/3n 3 +1/2n 2 +1/3
n) = 2nVo−△Vc ...(1) The first term on the right side is the output voltage in the case of no load (I = 0), and the second term is the voltage drop △Vc that occurs to supply the load current I. . If the forward resistance of the rectifying element 5 is R, and the resistance of the power supply for applying an AC voltage between the terminal 1 and the ground 2 is Rt, then
The voltage drop △V R due to these is expressed by the following formula,
The DC output voltage V is △V R =3π) 2/3 NVo (NRt+R/VoI) 2/3 ...
(2) This amount will be further subtracted.
従来第１図に示すようなコツククロフト回路に
おいて、整流素子としてシリコンダイオードを用
い、入力電圧が数Ｖ〜数10Vと低い場合には、シ
リコンダイオードの順電圧ＶFがが約0.6Vあり、
順方向抵抗Ｒが大きいために上述のように多段に
構成すると、シリコンダイオードによる電圧降下
分（△ＶR）が大きくなり、所定の直流出力電圧
を得るには段数を増加したりして高価なものとな
つていた。 Conventionally, in a Kotscroft circuit as shown in Fig. 1, a silicon diode is used as a rectifying element, and when the input voltage is as low as several volts to several tens of volts, the forward voltage V F of the silicon diode is approximately 0.6 V.
Since the forward resistance R is large, if the configuration is multi-staged as described above, the voltage drop due to the silicon diode (△V R ) will be large, and in order to obtain the desired DC output voltage, it will be necessary to increase the number of stages, which is expensive. It had become a thing.
本考案は上述の欠点を除去し、安価で効率の高
い倍圧整流回路を提供しようとするものである。 The present invention aims to eliminate the above-mentioned drawbacks and provide an inexpensive and highly efficient voltage doubler rectifier circuit.
すなわち、整流素子とコンデンサを組合せてな
るコツククロフト回路において、上記整流素子の
代りにトランジスタを用いて構成したことを特徴
とする倍圧整流回路である。 That is, the present invention is a voltage doubler rectifier circuit characterized by using a transistor instead of the rectifying element in a Cottcroft circuit formed by combining a rectifying element and a capacitor.
以下、本考案を第２図に示す実施例について説
明する。 The present invention will be described below with reference to an embodiment shown in FIG.
図はコンデンサ６、トランジスタ７、抵抗８を
４段に構成してなる倍圧整流回路を示し、ダイオ
ード５に代えてトランジスタ７のコレクタ、エミ
ツタの両端子間にコンデンサ６が接続され、トラ
ンジスタ７のベースより抵抗８を通じてアース２
にそれぞれ接続され、上記トランジスタ７のベー
ス電流を抵抗８によつて適切に流し、トランジス
タ７をスイツチングさせている。その結果トラン
ジスタ７の動作時はコレクタ、エミツタ間の電
圧、電流特性を飽和させた状態になるよう構成さ
れており、これによるオン時の電圧降下ＶCE
（sat）は約0.1V以下となる。 The figure shows a voltage doubler rectifier circuit consisting of a capacitor 6, a transistor 7, and a resistor 8 in four stages.In place of the diode 5, the capacitor 6 is connected between the collector and emitter terminals of the transistor 7. Ground 2 from the base through resistor 8
The base current of the transistor 7 is appropriately passed through the resistor 8, and the transistor 7 is switched. As a result, when the transistor 7 is in operation, the voltage and current characteristics between the collector and emitter are saturated, and this causes a voltage drop V CE when the transistor is on.
(sat) will be approximately 0.1V or less.
したがつて負荷電流Ｉを供給した場合、トラン
ジスタ７による電圧降下△ＶRは極めて小さくな
り、コンデンサ６と組合せ多段に構成した倍圧整
流回路の効率は著しく向上することができる。 Therefore, when the load current I is supplied, the voltage drop ΔV R due to the transistor 7 becomes extremely small, and the efficiency of the voltage doubler rectifier circuit configured in multiple stages in combination with the capacitor 6 can be significantly improved.
第３図は上記実施例に基づいてコンデンサ６と
トランジスタ７の段数を変えて電圧降下を測定し
た結果を示し、図から明らかのように本考案の倍
圧整流回路は電圧降下が極めて小さく、高効率の
ものが得られた。 Figure 3 shows the results of measuring the voltage drop by changing the number of stages of capacitor 6 and transistor 7 based on the above embodiment.As is clear from the figure, the voltage doubler rectifier circuit of the present invention has extremely small voltage drop and high Efficiency was obtained.
叙上のように本考案の倍圧整流回路は段数を増
加することなく構成でき、小形で高効率を実現さ
せるなどの特徴を有し、実用的価値の極めて大な
るものである。 As mentioned above, the voltage doubler rectifier circuit of the present invention can be constructed without increasing the number of stages, is compact and has high efficiency, and has extremely great practical value.
第１図は従来の倍圧整流回路図、第２図は本考
案の一実施例の倍圧整流回路図、第３図は本考案
の倍圧整流回路と従来の倍圧整流回路とを比較し
た段数−電圧降下特性図である。
２：アース、４，６：コンデンサ、５：整流素
子、７：トランジスタ、８：抵抗。
Figure 1 is a conventional voltage doubler rectifier circuit diagram, Figure 2 is a voltage doubler rectifier circuit diagram of an embodiment of the present invention, and Figure 3 is a comparison of the voltage doubler rectifier circuit of the present invention and a conventional voltage doubler rectifier circuit. FIG. 4 is a graph showing the number of stages vs. voltage drop characteristic. 2: Earth, 4, 6: Capacitor, 5: Rectifier, 7: Transistor, 8: Resistor.
Claims (1)
ロフト回路において、上記整流素子の代わりにト
ランジスタを用いて構成し、かつ該トランジスタ
のベース端子とコツククロフト回路のアース端子
間に該トランジスタをスイツチングさせる抵抗を
接続したことを特徴とする倍圧整流回路。 In a Kotscroft circuit consisting of a combination of a rectifying element and a capacitor, a transistor is used instead of the rectifying element, and a resistor for switching the transistor is connected between the base terminal of the transistor and the ground terminal of the Kotscroft circuit. Features a voltage doubler rectifier circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1980065785U JPS6237435Y2 (en) | 1980-05-13 | 1980-05-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1980065785U JPS6237435Y2 (en) | 1980-05-13 | 1980-05-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56166785U JPS56166785U (en) | 1981-12-10 |
| JPS6237435Y2 true JPS6237435Y2 (en) | 1987-09-24 |
Family
ID=29659899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1980065785U Expired JPS6237435Y2 (en) | 1980-05-13 | 1980-05-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6237435Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51147188A (en) * | 1975-06-12 | 1976-12-17 | Nec Corp | Semicoductor device |
| JPS5437825B2 (en) * | 1974-02-27 | 1979-11-17 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5437825U (en) * | 1977-08-22 | 1979-03-12 |
-
1980
- 1980-05-13 JP JP1980065785U patent/JPS6237435Y2/ja not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5437825B2 (en) * | 1974-02-27 | 1979-11-17 | ||
| JPS51147188A (en) * | 1975-06-12 | 1976-12-17 | Nec Corp | Semicoductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56166785U (en) | 1981-12-10 |
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