JPS6235680A - Amorphous silicon solar battery and manufacture of the same - Google Patents

Amorphous silicon solar battery and manufacture of the same

Info

Publication number
JPS6235680A
JPS6235680A JP60175084A JP17508485A JPS6235680A JP S6235680 A JPS6235680 A JP S6235680A JP 60175084 A JP60175084 A JP 60175084A JP 17508485 A JP17508485 A JP 17508485A JP S6235680 A JPS6235680 A JP S6235680A
Authority
JP
Japan
Prior art keywords
layer
amorphous silicon
solar cell
substrate
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60175084A
Other languages
Japanese (ja)
Inventor
Toshihiko Yoshida
利彦 吉田
Hisashi Kakigi
柿木 寿
Keitaro Fukui
福井 慶太郎
Mitsuo Matsumura
松村 光雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tonen General Sekiyu KK
Original Assignee
Toa Nenryo Kogyyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toa Nenryo Kogyyo KK filed Critical Toa Nenryo Kogyyo KK
Priority to JP60175084A priority Critical patent/JPS6235680A/en
Publication of JPS6235680A publication Critical patent/JPS6235680A/en
Pending legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/545Microcrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/548Amorphous silicon PV cells

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  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To improve an open-circuit voltage significantly by a method wherein an n1-layer is made of amorphous Si and an n2-layer contains fine-crystallized silicon and the thickness of the n1-layer is selected to be not less than 60Angstrom and not more than 400Angstrom . CONSTITUTION:An amorphous silicon solar battery is constituted by junctions composed of a substrate 1, a transparent conductive film 2, a p-layer 3, an i-layer 4 and an n1-layer 5 and an n2-layer 6 and by a metal electrode 7. The n1-layer is produced in a material gas such as silane, disilane or silicon fluoride which contains at least one of nitrogen compound such as ammonia, fluorine compound, carbon compound such as methane, oxygen compound or compound such as nitrogen monoxide or carbon monoxide and is practically in an amorphous condition. The silicon source is diluted by 10-60 times with hydrogen. The n2-layer is fine-crystallized by a conventional method. Moreover, the n1-layer is formed to have the thickness of 60-400Angstrom and the n2-layer is formed to have the thickness of 10-80Angstrom .

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、アモルファスシリコン(以下a −Siと略
記する。)太陽電池およびその製造法に関するもので、
詳しくはn層が電気伝導度の異なるa−Si層と、微結
晶化シリコン層の2層からなるpin型太陽電池および
、プラズマCVD法による当該太陽電池の製造法に関す
るものである。
Detailed Description of the Invention (Field of Industrial Application) The present invention relates to an amorphous silicon (hereinafter abbreviated as a-Si) solar cell and a method for manufacturing the same.
Specifically, the present invention relates to a pin type solar cell in which the n-layer is composed of two layers, an a-Si layer and a microcrystalline silicon layer having different electrical conductivities, and a method for manufacturing the solar cell using a plasma CVD method.

(従来の技術) 近年、クリーンで無限なエネルギー源として太陽エネル
ギーが注目され、太陽エネルギーの光電変換用に太陽電
池の開発が活発に推進されている。
(Prior Art) In recent years, solar energy has attracted attention as a clean and limitless energy source, and the development of solar cells for photoelectric conversion of solar energy has been actively promoted.

太陽電池は、太陽から放射されるエネルギーのうち地上
に達しうるエネルギーを100%電気エネルギーに変換
しうるちのが理想であるが、現状ではa−Stを用いた
ものは高々10%強の変換効率を達成しうるにとどまっ
ている。
Ideally, a solar cell would be able to convert 100% of the energy emitted by the sun that can reach the ground into electrical energy, but currently those using a-St have a conversion efficiency of just over 10%. It remains possible to achieve this.

a−S、i′太陽電池は、ガラス、ステンレスあるいは
ポリイミドの如き基板に電極を介してpinの接合が形
成されたものであり、大面積かつ安価なものが製造でき
ることから将来の太陽電池の中で主流を占めるといわれ
ている。
A-S, i' solar cells are made by forming pin junctions on a substrate such as glass, stainless steel, or polyimide through electrodes, and because they can be manufactured with large area and at low cost, they are expected to be used in future solar cells. It is said to be the mainstream.

a−Si太陽電池の開放電圧は、a−Stのバンドギャ
ップが1.7eVSp層のフェルミレベルが0.3eV
、およびn層のフェルミレベルが0.2eVであること
から理論的には1.2■の開放電圧が得られるはずであ
る。しかしながら、実際にはa−Si太陽電池の開放電
圧は0.80〜0.87 Vの実測値が得られているに
すぎない。
The open circuit voltage of an a-Si solar cell is such that the bandgap of a-St is 1.7eV and the Fermi level of the Sp layer is 0.3eV.
, and the Fermi level of the n layer is 0.2 eV, so an open circuit voltage of 1.2 .mu. is theoretically supposed to be obtained. However, in reality, the open circuit voltage of an a-Si solar cell has only been measured to be 0.80 to 0.87 V.

このような理論値と実測値の相違は種々の研究が行なわ
れた結果、p/i界面およびn/i界面での接合状態が
理想状態と現実の太陽電池とてかけはなれている為と考
えられている。
As a result of various studies conducted, this difference between the theoretical value and the measured value is thought to be due to the fact that the bonding state at the p/i interface and n/i interface is far from the ideal state and the actual solar cell. It is being

a−Si太陽電池は、グロー放電プラズマCVD法やス
パッタリング法等によって製造されるが、これら製造法
ではp/i界面やn/i界面をプラズマにより生じたエ
ネルギーの高い反応活性種が叩くことにより、欠陥や界
面で状態密度の高い部分をつ(るためと考えられる。
A-Si solar cells are manufactured by glow discharge plasma CVD method, sputtering method, etc., but in these manufacturing methods, high-energy reactive species generated by plasma hit the p/i interface and n/i interface. This is thought to be due to the formation of areas with high density of states at defects and interfaces.

このため、p/i界面およびi / n界面ではプラズ
マパワーを低下させる等、温和な条件が採用されている
。現実の太陽電池の開放電圧が理想よりもかなり小さい
理由としては、p/i界面およびi / n界面におい
てp、iおよびn層を構成する化合物の原子密度等の物
理化学的な相違から、欠陥を発生したり状態密度を増加
させるということも考えられる。このため、接合部分に
おいて構造を徐々に変化させることが検討されている。
Therefore, mild conditions such as lowering the plasma power are adopted at the p/i interface and the i/n interface. The reason why the open circuit voltage of an actual solar cell is much lower than the ideal is due to the physicochemical differences such as the atomic density of the compounds constituting the p, i, and n layers at the p/i interface and the i/n interface. It is also conceivable that this could cause the occurrence of , or increase the density of states. For this reason, consideration is being given to gradually changing the structure at the joint portion.

最近、pin型a−Si太陽電池における、n層に相当
する部分を二層化したpin−n型のa−Si太陽電池
が提案された。
Recently, a pin-n type a-Si solar cell has been proposed in which the portion corresponding to the n-layer in the pin type a-Si solar cell is made into two layers.

、これは、i / n界面において開放電圧の低下を抑
えるため、n層を形成する前にドーパントの濃度を下げ
てa−Stのn一層を形成せんとするものである。
In order to suppress the drop in open circuit voltage at the i/n interface, the dopant concentration is lowered before forming the n layer to form an a-St n layer.

一方、同様な観点からn/金属電極界面に当該n層と異
なる微結晶化したシリコン層を挿入したa−Si太陽電
池も提案されている(特開59−83774号公報)。
On the other hand, from a similar point of view, an a-Si solar cell has also been proposed in which a microcrystalline silicon layer different from the n layer is inserted at the n/metal electrode interface (Japanese Patent Laid-Open No. 59-83774).

これは、n層を形成したあとグロー放電電力を増大させ
て60八以上の微結晶化シリコン層を形成するもので、
とりわけ金属電極をスクリーン印刷と焼成によって形成
する場合に接触抵抗を低減し、出力電力を増大しうると
するものである。
This involves forming a microcrystalline silicon layer of 608 or more by increasing the glow discharge power after forming the n-layer.
In particular, when metal electrodes are formed by screen printing and firing, contact resistance can be reduced and output power can be increased.

(発明が解決しようとする問題点) 従来のpin−n型太陽電池は、n一層およびn層の各
々をa−Stで構成するものであるが、pin型と比べ
i/n界面での開放電力の低下は改善されるもののn/
金属電極界面での開放電力の低下は依然として克服され
ていない。
(Problems to be Solved by the Invention) In a conventional pin-n type solar cell, each of the n-layer and the n-layer is composed of a-St, but compared to the pin type, there is less openness at the I/N interface. Although the power drop is improved, n/
The reduction in open-circuit power at the metal electrode interface has still not been overcome.

また、既に提案されている2層のn層からなる太陽電池
のうち一方のn層をa−Stで構成し、他方の金属電極
側のn層を微結晶シリコンで構成するものは、製造コス
トが高くなるわりに出力電力が小さいという問題があっ
た。すなわち、この型の太陽電池はプラズマCVD法で
第一のn層を形成し次いでプラズマのパワーを増大させ
ることにより第二のn層を形成させ、最後に銀ペースト
等をスクリーン印刷し焼成することによりn1ili)
上へ金属電極を設けるものである。
In addition, among the solar cells that have already been proposed, which consist of two n-layers, one n-layer is made of a-St, and the other n-layer on the metal electrode side is made of microcrystalline silicon, the manufacturing cost is low. There was a problem in that the output power was low even though the power was high. That is, in this type of solar cell, a first n-layer is formed using a plasma CVD method, a second n-layer is formed by increasing the plasma power, and finally a silver paste or the like is screen printed and fired. by n1ili)
A metal electrode is provided on top.

従って、比較的高価な原料を用いているだけではなく焼
成条件が高温(例えば600℃以上)を必要とすること
があることから、n層との界面において不都合な原子状
態が生じ、この結果太陽電池として満足すべき開放電圧
が得られない。
Therefore, not only are relatively expensive raw materials used, but also firing conditions may require high temperatures (e.g., over 600°C), which creates unfavorable atomic states at the interface with the n-layer, resulting in A satisfactory open circuit voltage as a battery cannot be obtained.

(問題点を解決するための手段) 本発明者らは、2層のn層からなるpini′太陽電池
いて開放電圧を格段に高めることを目的に鋭意研究を重
ねることにより、性能の高い太陽電池を安価にしかも効
率的に製造する技術を確−立し本発明を完成させた。
(Means for Solving the Problems) The present inventors have conducted extensive research aimed at significantly increasing the open-circuit voltage of a pini solar cell consisting of two n-layers, and have developed a solar cell with high performance. The present invention has been completed by establishing a technology for manufacturing the product at low cost and efficiently.

本発明は、基板上に透明導電膜、pinの各層からなる
接合および金属電極を有し、n層が電気型導度の異なる
n1層およびn2層から構成される太陽電池において、
01層がa−8tでありn2層が微結晶化シリコンを含
有しているとともに、01層の厚さが60Å以上400
Å以下であることを特徴とする太陽電池である。
The present invention provides a solar cell that has a transparent conductive film, a junction consisting of pin layers, and a metal electrode on a substrate, and the n layer is composed of an n1 layer and an n2 layer having different electric type conductivities.
The 01 layer is a-8t, the n2 layer contains microcrystalline silicon, and the thickness of the 01 layer is 60 Å or more and 400 Å or more.
This is a solar cell characterized in that the solar cell has a thickness of Å or less.

また本発明は、グロー放電によるプラズマCvD法によ
り一ヒ記太陽電池を製造する方法であって、基板へ透明
導電膜、p層およびi層を順次形成した後、a−3in
I層を形成し、次いで基板の温度を変化させることによ
り微結晶化02層を形成し、最後にスパッタリング又は
真空蒸着により金属電極を形成することを特徴とするa
−Si太陽電池の製造法に関するものである。
The present invention also provides a method for manufacturing a solar cell using a plasma CVD method using glow discharge, in which a transparent conductive film, a p layer and an i layer are sequentially formed on a substrate, and then a
A characterized by forming an I layer, then forming a microcrystalline 02 layer by changing the temperature of the substrate, and finally forming a metal electrode by sputtering or vacuum evaporation.
-It relates to a method for manufacturing a Si solar cell.

本発明のa−3t太陽電池の構造は、第1回に示すとお
りである。
The structure of the A-3T solar cell of the present invention is as shown in Part 1.

すなわち、基板(1)、透明導電膜(2)p層(3)、
i層(4)およびn1層(5)とn2層(6)とからな
る接合、および金属電極(7)から構成される。
That is, a substrate (1), a transparent conductive film (2), a p-layer (3),
It is composed of an i layer (4), a junction consisting of an n1 layer (5) and an n2 layer (6), and a metal electrode (7).

基板は、ガラス、ステンレスやアルミニウム等の金属薄
板あるいはポリイミド等の耐熱性プラスチックといった
材料から選択されるが特に好ましいのはガラスである。
The substrate is selected from materials such as glass, thin metal plates such as stainless steel and aluminum, and heat-resistant plastics such as polyimide, with glass being particularly preferred.

透明導電膜は、酸化スズおよび又はインジウムを主成分
とし、これに少量の添加剤を含むものであり、酸化スズ
を用いるのが好ましい。
The transparent conductive film is mainly composed of tin oxide and/or indium, and contains a small amount of additives, and it is preferable to use tin oxide.

p層は、a−3i中にドーパントとしてのホウ素の如き
元素周期律表第■族の元素が倉荷される。
In the p layer, an element of group 1 of the periodic table of elements, such as boron, is stored as a dopant in a-3i.

i層はドーパントの存在しないa−3iである。The i-layer is a-3i with no dopant.

以上の基板からi層までの接合は、従来公知の構造であ
る。
The above-described bonding from the substrate to the i-layer has a conventionally known structure.

n層は、a−5iに比較的低濃度(0,01〜0.1%
)のリンの如き元素周期律表第■族の元素がドーパント
として含まれたもので、ドーパント以外に不純物として
フッ素、窒素、酸素および炭素の群から選択される一種
又は二種以上の元素を含むことができる。特に好ましい
のは窒素および又は酸素である。不純物の含有量は、n
1層の場合微結晶化を阻害する程度であり、窒素、酸素
とも0.1〜5原子パーセントの範囲か好ましい。
The n-layer has a relatively low concentration (0.01-0.1%) in a-5i.
) contains an element from group Ⅰ of the periodic table of elements such as phosphorus as a dopant, and in addition to the dopant, it also contains one or more elements selected from the group of fluorine, nitrogen, oxygen, and carbon as an impurity. be able to. Particularly preferred are nitrogen and/or oxygen. The content of impurities is n
In the case of a single layer, the amount of nitrogen and oxygen is preferably within the range of 0.1 to 5 atomic percent, since microcrystalization is inhibited.

01層の厚さは02層と比べて厚い方が好ましく、50
層以上、特に60八〜400八が好ましい。更に好まし
くは100〜300Aである。
The thickness of the 01 layer is preferably thicker than the 02 layer;
The number of layers or more is preferably 608 to 4008. More preferably, it is 100-300A.

02層は、微結晶化したシリコン層でn1層と比べて薄
めで100八以下、特にIOA〜80八が好ましい。
The 02 layer is a microcrystalline silicon layer, which is thinner than the n1 layer and preferably has a thickness of 1008 or less, particularly an IOA of 808 or less.

金属電極は、アルミニウム等の導電性金属祠料の薄層で
、本発明ではスパッタリングか真空蒸着により02層上
に形成される。
The metal electrode is a thin layer of a conductive metal abrasive, such as aluminum, and is formed on the 02 layer by sputtering or vacuum deposition in the present invention.

次に本発明のa−Si太陽電池を製造する方法について
説明する。
Next, a method for manufacturing the a-Si solar cell of the present invention will be explained.

本発明のa−3i太陽電池において、pin接合はプラ
ズマCVD装置を用いて製造される。プラズマCVD装
置は公知のものでよいがpinの各層を連続的にかつ安
定的に製造するため仕切りにより独立しうる反応室を有
し基板がベルトコンベアで運搬されるように構成された
装置を使用するのが好ましい。このプラズマCVD装置
により、基板上の透明電極へp層およびi層が公知の方
法で形成される。
In the a-3i solar cell of the present invention, the pin junction is manufactured using a plasma CVD apparatus. The plasma CVD apparatus may be any known one, but in order to continuously and stably manufacture each layer of pins, an apparatus is used that has reaction chambers that can be separated by partitions and is configured so that the substrate is transported by a belt conveyor. It is preferable to do so. With this plasma CVD apparatus, a p layer and an i layer are formed on a transparent electrode on a substrate by a known method.

次いで、n1+  n2層が製膜される。nl。Next, n1+ and n2 layers are formed. nl.

n2層の作製方法には、2つの方法があるが、いずれも
n1層はアモルファス層、02層は微結晶化層となるよ
うに工夫されている。
There are two methods for producing the n2 layer, but both are devised so that the n1 layer is an amorphous layer and the 02 layer is a microcrystalline layer.

まず、第1の方法は、n1層はシラン、ジシラン及びフ
ッ化珪素といった原料ガス中にアンモニア等の窒素化合
物、フッ素化合物、メタン等の炭素化合物、酸素化合物
、−酸化窒素や一酸化炭素といった化合物のいずれか一
種以上を含むようにして、製造され、実質的にアモルフ
ァス状態とされる。珪素源は水素によって10〜60倍
に希釈される。02層は、従来知られている方法で微結
晶化させる。さらに、n1層は、60〜400A。
First, in the first method, the n1 layer contains nitrogen compounds such as ammonia, fluorine compounds, carbon compounds such as methane, oxygen compounds, -compounds such as nitrogen oxide and carbon monoxide in the raw material gas such as silane, disilane, and silicon fluoride. It is manufactured so as to contain any one or more of the following, and is made into a substantially amorphous state. The silicon source is diluted 10-60 times with hydrogen. The 02 layer is microcrystallized by a conventionally known method. Furthermore, the n1 layer is 60 to 400A.

n2層は10〜80八になるように作製する。電力密度
は0.05〜0 、4W / cdが採用される。
The n2 layer is prepared to have a thickness of 10 to 808. The power density is 0.05~0, 4W/cd is adopted.

第2の方法は、n1層と02層の原料ガス組成は同じで
あるが、n1作製時の基板温度を180〜220℃にし
て、基板温度の制御により結晶化を抑制する。02作製
時の?m度は、220〜250℃にして、微結晶化させ
る。これ等は、U板温度が低いときは微結晶化しないと
いう特性を利用したものである。この場合も、n1層は
60〜300A、n2層は10〜80人になるように作
製する。この基板温度の変化は、急激でも良いし時間を
かけて徐々に変化させてもよい。02層はプラズマ電力
を変えても製造できるが、プラズマ電力を変えず基板温
度を変化させた方が良質のn2層が形成できる。n2層
の厚さは、n’1層よりも薄い方かよ<100A以下、
特に10八〜80^の範囲となるようにプラズマ条件が
設定される。
In the second method, the raw material gas compositions of the n1 layer and the 02 layer are the same, but the substrate temperature during the n1 fabrication is set to 180 to 220° C., and crystallization is suppressed by controlling the substrate temperature. At the time of 02 production? The temperature is set at 220 to 250°C to form microcrystals. These utilize the characteristic that microcrystalization does not occur when the U plate temperature is low. In this case as well, the n1 layer is made to have 60 to 300 A, and the n2 layer is made to have 10 to 80 people. This change in substrate temperature may be rapid or may be changed gradually over time. Although the 02 layer can be manufactured by changing the plasma power, a better quality N2 layer can be formed by changing the substrate temperature without changing the plasma power. Is the thickness of the n2 layer thinner than the n'1 layer?<100A or less,
In particular, the plasma conditions are set to be in the range of 108 to 80^.

こうしてpin接合を形成させた後、最後に金属電極が
形成される。金属電極は、通常スパッタリング法もしく
は真空蒸着法に依って形成される。
After forming the pin junction in this way, a metal electrode is finally formed. Metal electrodes are usually formed by sputtering or vacuum evaporation.

原料は、アルミニウムや銀等の金属が選定され、公知の
条件で02層上に薄膜化される。
A metal such as aluminum or silver is selected as the raw material, and a thin film is formed on the 02 layer under known conditions.

他の金属電極の形成法として、スクリーン印刷と焼成に
依る方法が知られているが、この方法に依ると焼成温度
が高い場合にはn2層との接触部分に欠陥を生じること
があり、一方、銀エポキシペーストを用いる低温法では
経済的に問題がある。
Another known method for forming metal electrodes is to use screen printing and firing, but if the firing temperature is high, defects may occur in the contact area with the N2 layer. However, the low temperature method using silver epoxy paste is economically problematic.

(作 用) 本発明のptnln2構造を有するa−8’>太陽電池
が、いかなる理由で高い開放電圧を示すかは、完全に解
明されてはいないが、おおよそ次のように考えることが
できる。
(Function) The reason why the a-8′> solar cell having the ptnln2 structure of the present invention exhibits a high open circuit voltage is not completely clear, but it can be roughly considered as follows.

まず、本発明のa−3t太陽電池は、i層がアモルファ
ス層であり、01層もアモルファス層であることから、
i / n 1界面の整合性が良く、界面準位の発生を
少なくすることができる。
First, in the A-3T solar cell of the present invention, since the i layer is an amorphous layer and the 01 layer is also an amorphous layer,
The i/n1 interface has good consistency, and the generation of interface states can be reduced.

また、n2層は微結晶化しており、電気伝導度は、n2
層の方が01層よりも高い。これはフェルミレベルの位
置が、01層では0.2eVであり、n2層では0.l
eV以下であることによる。つまり、このn2層を利用
することにより、開放電圧を向上させることができる。
In addition, the n2 layer is microcrystalline, and the electrical conductivity is n2
The layer is higher than the 01 layer. This means that the position of the Fermi level is 0.2 eV in the 01 layer and 0.2 eV in the n2 layer. l
This is because it is less than eV. In other words, by utilizing this n2 layer, the open circuit voltage can be improved.

しかし、01層のないp/i/n2型の太陽電池では、
L / n 2界面の整合性が悪く、開放電圧は向上せ
ず、本発明の構造にしないと、n2層の効果を充分に利
用できない。
However, in a p/i/n2 type solar cell without the 01 layer,
The matching of the L/n2 interface is poor, the open circuit voltage is not improved, and the effect of the n2 layer cannot be fully utilized unless the structure of the present invention is adopted.

また、01層と02層の膜厚については、n2層を厚く
すると、リーク電流が増加することがある。これを妨げ
るためには、n2層の厚みを10〜80Aにすることが
望しく、この場合、01層の厚みとしては、60〜40
0八が好しい。
Furthermore, regarding the film thicknesses of the 01 and 02 layers, if the n2 layer is made thicker, the leakage current may increase. In order to prevent this, it is desirable that the thickness of the n2 layer be 10 to 80A, and in this case, the thickness of the 01 layer should be 60 to 40A.
08 is preferable.

さらに、本発明のa−Si太陽電池では、このn2層は
微結晶化したシリコンなため、n2/金属電極界面で電
気伝導度が高くなるものと考えられる。
Furthermore, in the a-Si solar cell of the present invention, since the n2 layer is made of microcrystalline silicon, it is thought that the electrical conductivity is high at the n2/metal electrode interface.

また、本発明のようにn1層をプラズマCVDで形成し
たあと基板の温度を変化させ02層を形成させることに
より性能の良い太陽電池を得ることができるのは、従来
のようにプラズマ電力を増大させるよりも微結晶化シリ
コンの結晶状態が良好になるため、n 1 / n 2
界面およびn2/金属界面の接合状態が改善されるもの
と考えられる。
In addition, as in the present invention, a solar cell with good performance can be obtained by forming the N1 layer by plasma CVD and then changing the temperature of the substrate to form the O2 layer. Since the crystal state of microcrystalline silicon is better than that of n 1 / n 2
It is thought that the bonding condition at the interface and the n2/metal interface is improved.

実施例1 ガラス基板上に5n02の透明導電膜、p層およびi層
を形成したあと01層として低パワーでa−3i層を約
20〇八つけて、その後n2層として高パワーで微結晶
シリコン層を約60A製膜した。その結果開放電圧は、
0.88 Vまで改善された。
Example 1 After forming a 5n02 transparent conductive film, p layer and i layer on a glass substrate, an a-3i layer of about 2008 was formed as an 01 layer at low power, and then microcrystalline silicon was formed as an n2 layer at high power. A layer of approximately 60A was deposited. As a result, the open circuit voltage is
The voltage was improved to 0.88 V.

実施例2 01層として、基板温度200℃でa−8i層、n2層
として基板温度250℃で結晶化シリコン層を製膜した
。その結果開放電圧0.89 Vが得られた。この場合
、基板温度を200から250℃まで、連続に上昇させ
ても同様の効果が得られた。
Example 2 An a-8i layer was formed as the 01 layer at a substrate temperature of 200°C, and a crystallized silicon layer was formed as the n2 layer at a substrate temperature of 250°C. As a result, an open circuit voltage of 0.89 V was obtained. In this case, the same effect was obtained even when the substrate temperature was continuously raised from 200 to 250°C.

実施例3 次表のような原料ガスを用いて実施例2の方法で太陽電
池を製造した。
Example 3 A solar cell was manufactured by the method of Example 2 using the raw material gases shown in the following table.

不純物としては、NH3からのNが膜中に混入する。X
線回折から、01層は微結晶化せず、n2層は、微結晶
化していることがわかった。このn1層とn2層を用い
た太陽電池は開放電圧GJ(l Vとなった。また、F
、Co、NOを用いても同様な結果が得られた。
As an impurity, N from NH3 is mixed into the film. X
Linear diffraction revealed that the 01 layer was not microcrystalline, and the N2 layer was microcrystallized. The solar cell using this n1 layer and n2 layer had an open circuit voltage GJ (l V. Also, F
Similar results were obtained using , Co, and NO.

実施例4 TI  (nt層のあつみ)、T2(n2層のあつみ)
の和71 +T2−200人となるよう(こして、厚み
依存性を見た。01層、12層の作製は実施例2と同じ
である。40<72 <TIで、高い開放電圧が得られ
ることが、表よりわかる。
Example 4 TI (nt layer strength), T2 (n2 layer strength)
The sum of 71 + T2 - 200 people (Thus, we looked at the thickness dependence. The fabrication of the 01 and 12 layers is the same as in Example 2. When 40 < 72 < TI, a high open circuit voltage can be obtained. This can be seen from the table.

(発明の効果) 本発明のa−3i太陽電池は、従来の太陽電池よりも格
段に改善された開放電圧を示す性能の高い太陽電池であ
る。また、本発明のプラズマCVD法によれば、高性能
の太陽電池を安定的に効率よく生産しうるという効果が
あるから、本発明は産業上きわめて有用なものである。
(Effects of the Invention) The a-3i solar cell of the present invention is a high-performance solar cell that exhibits a significantly improved open circuit voltage than conventional solar cells. Further, according to the plasma CVD method of the present invention, high performance solar cells can be produced stably and efficiently, so the present invention is extremely useful industrially.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の太陽電池の構造を例示する説明図で
ある。
FIG. 1 is an explanatory diagram illustrating the structure of the solar cell of the present invention.

Claims (1)

【特許請求の範囲】 1)基板上に透明導電膜、pinの各層からなる接合お
よび金属電極を有し、当該n層がn1層およびn2層の
2層から構成されるアモルファスシリコン太陽電池にお
いて、n1層がアモルファスシリコンであり、n2層が
微結晶化シリコンを含有するアモルファスシリコンであ
り、n1層の厚さが60Å以上400Å以下であること
を特徴とするアモルファスシリコン太陽電池。 2)n1層n2層のいずれか又は両層にフッ素、窒素、
酸素および炭素の群から選択される一種又は二種以上の
不純物が含有されている特許請求の範囲第1項に記載の
太陽電池。 3)グロー放電によるプラズマCVD法によりアモルフ
ァスシリコン太陽電池を製造する方法において、基板上
に透明導電膜、アモルファスシリコンのp層およびi層
を形成した後、アモルファスシリコンのn1層を形成し
、次いで基板の温度を変化させることにより少なくとも
一部が微結晶化したアモルファスシリコンのn2層を形
成し、最後にスパッタリング又は真空蒸着により金属電
極を形成することを特徴とするアモルファスシリコン太
陽電池の製造法。
[Claims] 1) In an amorphous silicon solar cell having a transparent conductive film, a junction consisting of pin layers, and a metal electrode on a substrate, and the n layer consisting of two layers, an n1 layer and an n2 layer, An amorphous silicon solar cell characterized in that the n1 layer is amorphous silicon, the n2 layer is amorphous silicon containing microcrystallized silicon, and the thickness of the n1 layer is 60 Å or more and 400 Å or less. 2) Fluorine, nitrogen,
The solar cell according to claim 1, which contains one or more impurities selected from the group of oxygen and carbon. 3) In a method of manufacturing an amorphous silicon solar cell by a plasma CVD method using glow discharge, after forming a transparent conductive film, a p-layer and an i-layer of amorphous silicon on a substrate, an n1 layer of amorphous silicon is formed, and then the substrate A method for producing an amorphous silicon solar cell, which comprises forming an N2 layer of amorphous silicon at least partially microcrystallized by changing the temperature of the amorphous silicon, and finally forming a metal electrode by sputtering or vacuum evaporation.
JP60175084A 1985-08-09 1985-08-09 Amorphous silicon solar battery and manufacture of the same Pending JPS6235680A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60175084A JPS6235680A (en) 1985-08-09 1985-08-09 Amorphous silicon solar battery and manufacture of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60175084A JPS6235680A (en) 1985-08-09 1985-08-09 Amorphous silicon solar battery and manufacture of the same

Publications (1)

Publication Number Publication Date
JPS6235680A true JPS6235680A (en) 1987-02-16

Family

ID=15989963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60175084A Pending JPS6235680A (en) 1985-08-09 1985-08-09 Amorphous silicon solar battery and manufacture of the same

Country Status (1)

Country Link
JP (1) JPS6235680A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63318166A (en) * 1987-06-19 1988-12-27 Sanyo Electric Co Ltd Photovoltaic device
JPH01280365A (en) * 1988-05-06 1989-11-10 Mitsui Toatsu Chem Inc Photoelectric transducer
JPH07122761A (en) * 1993-10-22 1995-05-12 Hitachi Ltd Solar battery
US5769963A (en) * 1995-08-31 1998-06-23 Canon Kabushiki Kaisha Photovoltaic device
JP2009290115A (en) * 2008-05-30 2009-12-10 Kaneka Corp Silicon-based thin-film solar battery
WO2010050271A1 (en) * 2008-10-31 2010-05-06 三菱重工業株式会社 Photoelectric conversion device and method for manufacturing photoelectric conversion device
JP2010533969A (en) * 2007-07-18 2010-10-28 アイメック Emitter structure fabrication method and resulting emitter structure
WO2011044362A2 (en) * 2009-10-08 2011-04-14 Ovshinsky Innovation, Llc Monolithic integration of photovoltaic cells
WO2011068197A1 (en) * 2009-12-04 2011-06-09 株式会社アルバック Photoelectric conversion device and manufacturing method for same

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63318166A (en) * 1987-06-19 1988-12-27 Sanyo Electric Co Ltd Photovoltaic device
JPH01280365A (en) * 1988-05-06 1989-11-10 Mitsui Toatsu Chem Inc Photoelectric transducer
JPH07122761A (en) * 1993-10-22 1995-05-12 Hitachi Ltd Solar battery
US5769963A (en) * 1995-08-31 1998-06-23 Canon Kabushiki Kaisha Photovoltaic device
JP2010533969A (en) * 2007-07-18 2010-10-28 アイメック Emitter structure fabrication method and resulting emitter structure
JP2009290115A (en) * 2008-05-30 2009-12-10 Kaneka Corp Silicon-based thin-film solar battery
JP2010109279A (en) * 2008-10-31 2010-05-13 Mitsubishi Heavy Ind Ltd Photoelectric conversion device and method of manufacturing the same
WO2010050271A1 (en) * 2008-10-31 2010-05-06 三菱重工業株式会社 Photoelectric conversion device and method for manufacturing photoelectric conversion device
US8859887B2 (en) 2008-10-31 2014-10-14 Mitsubishi Heavy Industries, Ltd. Photovoltaic device and process for producing photovoltaic device
WO2011044362A2 (en) * 2009-10-08 2011-04-14 Ovshinsky Innovation, Llc Monolithic integration of photovoltaic cells
WO2011044362A3 (en) * 2009-10-08 2011-08-18 Ovshinsky Innovation, Llc Monolithic integration of photovoltaic cells
WO2011068197A1 (en) * 2009-12-04 2011-06-09 株式会社アルバック Photoelectric conversion device and manufacturing method for same
JPWO2011068197A1 (en) * 2009-12-04 2013-04-18 株式会社アルバック Photoelectric conversion device and method of manufacturing photoelectric conversion device

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