JPS6234448U - - Google Patents
Info
- Publication number
- JPS6234448U JPS6234448U JP12665685U JP12665685U JPS6234448U JP S6234448 U JPS6234448 U JP S6234448U JP 12665685 U JP12665685 U JP 12665685U JP 12665685 U JP12665685 U JP 12665685U JP S6234448 U JPS6234448 U JP S6234448U
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductivity type
- semiconductor substrate
- electrode connection
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 2
- 230000006698 induction Effects 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 230000003068 static effect Effects 0.000 claims 1
Landscapes
- Thyristors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
第１図は本考案の一実施例を示す断面図、第２
図は本考案の他の実施例を示す断面図、第３図は
従来例を示す断面図である。
５……アノード層、６……半導体基体、７……
ゲート層、８……カソード層、１０……ゲート接
続層、１１，１２……高濃度不純物層。
Fig. 1 is a sectional view showing one embodiment of the present invention;
The figure is a sectional view showing another embodiment of the present invention, and FIG. 3 is a sectional view showing a conventional example. 5... Anode layer, 6... Semiconductor substrate, 7...
Gate layer, 8... cathode layer, 10... gate connection layer, 11, 12... high concentration impurity layer.
Claims (1)
ゲート層、該ゲート層と電気的に連なり、その一
部がエツチングにより露出されたゲート電極接続
層、前記半導体基体の一面に形成された逆導電型
のアノード層を備える静電誘導型半導体装置にお
いて、前記ゲート電極接続層およびアノード層を
取り囲むように前記半導体基体に、夫々逆導電型
の高濃度不純物層を形成したことを特徴とする静
電誘導型半導体装置。 a gate layer of an opposite conductivity type embedded in a semiconductor substrate of one conductivity type, a gate electrode connection layer electrically connected to the gate layer and a part of which is exposed by etching, and a gate electrode connection layer formed on one surface of the semiconductor substrate. A static induction type semiconductor device including an anode layer of opposite conductivity type, characterized in that highly concentrated impurity layers of opposite conductivity type are formed on the semiconductor substrate so as to surround the gate electrode connection layer and the anode layer, respectively. Electrostatic induction type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12665685U JPS6234448U (en) | 1985-08-20 | 1985-08-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12665685U JPS6234448U (en) | 1985-08-20 | 1985-08-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6234448U true JPS6234448U (en) | 1987-02-28 |
Family
ID=31020667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12665685U Pending JPS6234448U (en) | 1985-08-20 | 1985-08-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6234448U (en) |
-
1985
- 1985-08-20 JP JP12665685U patent/JPS6234448U/ja active Pending
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