JPS6234431U - - Google Patents
Info
- Publication number
- JPS6234431U JPS6234431U JP1985126159U JP12615985U JPS6234431U JP S6234431 U JPS6234431 U JP S6234431U JP 1985126159 U JP1985126159 U JP 1985126159U JP 12615985 U JP12615985 U JP 12615985U JP S6234431 U JPS6234431 U JP S6234431U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor element
- copper foil
- mounting structure
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 239000011889 copper foil Substances 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Description
第1図aはこの考案にかかる実装構造の説明の
ための縦断面図、第1図bはその背面図、第2図
は従来の実装構造の縦断面図、第3図はこの考案
にかかる実装構造の説明のための縦断面図、第4
図はこの考案にかかる実装構造の補足説明のため
の背面図である。 1……半導体素子、2……基板絶縁部材、3…
…基板銅箔、4……半田バンプ。
ための縦断面図、第1図bはその背面図、第2図
は従来の実装構造の縦断面図、第3図はこの考案
にかかる実装構造の説明のための縦断面図、第4
図はこの考案にかかる実装構造の補足説明のため
の背面図である。 1……半導体素子、2……基板絶縁部材、3…
…基板銅箔、4……半田バンプ。
Claims (1)
- 【実用新案登録請求の範囲】 (1) 半田バンプ付き半導体素子を、銅箔付き基
板にフエースダウンボンデイングしてなる半導体
装置において、予め該半導体素子の半田バンプを
接合すべき銅箔パターン部下の絶縁部材を取り除
いた該基板に、該半導体素子を該基板の銅箔面の
裏側からフエースダウンボンデイングし、該半導
体素子表面と該基板銅箔面との間に、絶縁部材を
挾持していることを特徴とする実装構造。 (2) 前記基板の半導体素子搭載部を凹状とした
ことを特徴とする実用新案登録請求第1項記載の
実装構造。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985126159U JPS6234431U (ja) | 1985-08-19 | 1985-08-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985126159U JPS6234431U (ja) | 1985-08-19 | 1985-08-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6234431U true JPS6234431U (ja) | 1987-02-28 |
Family
ID=31019698
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1985126159U Pending JPS6234431U (ja) | 1985-08-19 | 1985-08-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6234431U (ja) |
-
1985
- 1985-08-19 JP JP1985126159U patent/JPS6234431U/ja active Pending