JPS6234161B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a temperature compensated oscillation device for an electronic timepiece.

[Prior Art] A beat signal generated between two crystal oscillator circuits with different frequency-temperature characteristics is detected, and the frequency of this beat signal changes linearly with temperature. There is a method in which temperature compensation is performed on a crystal oscillation circuit that serves as a timekeeping reference or a frequency dividing circuit interposed between the crystal oscillation circuit and the timekeeping circuit by performing processing equivalent to square conversion. in particular,
Two crystal oscillation circuits having frequency-temperature characteristics in which two almost similar quadratic curves are shifted from each other in the temperature axis direction and the frequency axis direction, and a beat signal is output by detecting the frequency difference between the two crystal oscillation circuits. a first timer that counts n beat signals to generate a cycle time proportional to the beat signal cycle; and a programmable second timer that counts the frequency-divided signal to generate a constant pulse width β, and is a temperature-compensated oscillator that performs frequency correction by obtaining a correction amount corresponding to the square of the beat signal frequency, As a frequency correction means, the lower frequency side is used as a reference crystal oscillation circuit, and the signal is switched to the higher frequency side crystal oscillator circuit for the constant pulse period β seconds, resulting in a correction amount corresponding to the square of the beat signal frequency. A pulse interrupt etc. is generated for the frequency dividing circuit following the reference crystal oscillator circuit according to the method of obtaining the signal and the number corresponding to the square of the beat frequency obtained by passing the beat signal using the constant pulse period β seconds as a gate time. There is a method of obtaining a correction amount corresponding to the square of the beat signal frequency.

If the temperature at which the beat frequency becomes zero is called the intersection temperature, the number corresponding to the square of the beat signal frequency becomes a downwardly convex quadratic curve with the intersection temperature as the apex. The temperature characteristic of is an upwardly convex quadratic curve with the apex at the apex temperature (hereinafter referred to as ZTC temperature). Therefore,
If the intersection temperature and the ZTC temperature are matched, the quadratic curve of the reference crystal oscillation circuit and the correction amount
The curves have their apexes facing each other, and the temperature characteristics after correction can be made flat.

[Problems to be Solved by the Invention] As mentioned above, in the conventional method, the intersection temperature of the temperature characteristics of two crystal oscillation circuits must be set to match the ZTC temperature of the reference crystal oscillation circuit. , it was necessary to equip at least one of the crystal oscillation circuits with a trimmer capacitor, and adjust the frequency of one by raising or lowering it. That is, 2
It had only secondary correction means and relied on the trimmer capacitor for primary correction. However, it is well known that this trimmer capacitor is an unsuitable component for high-precision electronic watches that require long-term stability. In other words, in the case of trimmer capacitors with oil injected between the electrodes, the characteristics change due to mechanical shock, changes in humidity, or evaporation of this oil, which is the biggest cause of aging in crystal oscillator circuits. be. In order to reduce the effect of the trimmer capacitor, there is a way to reduce the amount of trimmer effectiveness by increasing the proportion of the built-in IC capacitance, but this also narrows the adjustment range, so it may not be possible to make the full adjustment. It's coming.
For this reason, in addition to the cost of adjusting the trimmer, the cost of sorting the crystal oscillators and sorting them for combination is costly, resulting in a further problem of increased costs.

In this way, the type that uses two crystal oscillator circuits is
This method provides particularly good temperature compensation characteristics among electronic watches with temperature compensation, and is the most suitable method for high-precision electronic watches. This resulted in problems of poor accuracy and high costs.

An object of the present invention is to eliminate the need for a trimmer capacitor and solve the above problems by digitally performing adjustment for primary correction to match the ZTC temperature and the intersection point temperature.

[Means for Solving the Problems] In addition to the configuration of the conventional example, the temperature compensated oscillator of the present invention has a third configuration that generates a waveform with a duty ratio α/n by counting α beat signals. A timer and a signal switching circuit that alternately switches the output signals of the two crystal oscillation circuits at a ratio of α:n−α according to the signal of the α/n duty and outputs the signals to the frequency dividing circuit. Features.

[Function] The frequency-temperature characteristics of the output signal of the signal switching circuit of the present invention are obtained by moving the characteristics of the first and second crystal oscillation circuits in parallel, and form an upwardly convex quadratic curve. can be made to match the intersection temperature by appropriately selecting the value of α.

Therefore, by simply setting α digitally, it is possible to perform the primary correction that was conventionally performed using a trimmer capacitor.

[Example] FIG. 1 shows an example of the temperature characteristics of _two crystal oscillation circuits used in a temperature compensated oscillation device according to the present invention. ₂ has ZTC temperatures T ₁ and T ₂ respectively, and has an intersection temperature T ₀ between T ₁ and T ₂ such that ₁ = ₂ = F ₀ . ₃ shows the frequency temperature characteristics of the output signal of the signal switching circuit of the present invention,
₁ and ₂ are switched at a ratio of α:n−α. ₄ is ₃ plus 2
The average frequency temperature characteristic when the second-order correction is added. ₅ is a part of the average frequency-temperature characteristic when only the conventional second-order correction means is used. ₁ (θ)≒F ₁ +a×F ₀ × (θ−T ₁ ) ² [Hz] ₂ (θ)≒F ₂ +a×F ₀ × (θ−T ₂ ) ² [Hz] a: Secondary temperature coefficient θ: Temperature ₃ (θ) = ₂ + (α/n) × ( ₁ - ₂ )
[Hz]. ₃ becomes as follows when _B = | ₁ - ₂ |. ₃ (θ)= ₂ +α/n× _B (θ<T ₀ ) ₃ (θ)= ₁ + (n-α)/n× _B
(θ<T ₀ ) Also, ₄ and ₅ are as follows: ₄ (θ) = ₁ + (α/n) x ( ₁ - ₂ ) + β/n x _B ² ₅ (θ) = ₁ + β/n x _B ² be. Each constant is assumed as follows.

T ₁ = 10°C T ₂ = 40°C F ₁ = 32768.115Hz F ₂ = 32768.459Hz a = -0.035×10 ^-6 At this time, F ₀ and T ₀ are as follows.

F ₀ =32768Hz T ₀ =20°C The set values are n = 64, α = 43, and β = 16 seconds.

FIG. 2 is a block diagram showing one embodiment of the present invention. Both the output signal P1 of the first crystal oscillation circuit 1 and the output signal P2 of the second crystal oscillation circuit 2 have rectangular waveforms, and their frequency-temperature characteristics are shown in FIG.
Represented by ₁ and ₂ . The output signal P3 of the phase difference detection circuit 3 is the aforementioned beat signal, and is output when the phase difference between P1 and P2 becomes zero, and its frequency is _B =| _{1-2 |} . Beat signal P
3 is frequency-divided by 1/n by a beat frequency divider circuit 4, which is a first timer, and becomes a signal P4. The β timer 7 is a second timer, which operates once every cycle of P4, and operates as the output signal of the first or second crystal oscillation circuit or its frequency divided signal (in FIG. 2, the second
By counting the crystal oscillation circuit output signal P2), a signal with a constant pulse width β seconds is created and sent to the signal switching circuit 8. The embodiment shown in FIG.
Since this is a type that performs temperature compensation by using the crystal oscillation circuit on the lower frequency side as the reference crystal oscillation circuit at any temperature, a phase polarity discrimination circuit 5 is provided to discriminate the magnitude relationship between frequencies ₁ and ₂ , and its output Signal P7 is output to signal switching circuit 8. The signal switching circuit 8 normally outputs a crystal oscillation circuit signal with a lower frequency, and outputs the output signal P6 of the β timer 7.
The crystal oscillation circuit signal with the higher frequency is output only while the signal is at a high level. With the above configuration, quadratic correction of the crystal oscillation circuit is possible, and flat characteristics can be obtained by making the intersection temperature of the two crystal oscillation circuit temperature characteristics match the ZTC temperature of one of the crystal oscillation circuits. However, if the intersection point temperature and the ZTC temperature do not match, as shown in FIG. 1, the temperature characteristics will be significantly tilted. The present invention adds an α timer 6, which is a third timer, and a second signal switching circuit to perform primary correction. α timer 6 outputs signal P4
The output signal P5 with a constant duty α/n is generated by counting α beat signals P3. The second signal switching circuit simply changes the outputs P1 and P2 of the first and second crystal oscillation circuits to α:n
- Since the signal is simply switched and output at a rate of α, the signal switching circuit 8 can be used also. Therefore,
The output signal P5 of the α timer 6 is sent to the signal switching circuit 8. At this time, in order to make both the primary correction and the secondary correction operations compatible, it is necessary to match the start timing of the β timer 7 of the secondary correction means to the high frequency → low frequency switching timing of the primary correction means. Therefore, the α timer output P5 is inputted to the β timer 7, and the β timer 7
is configured to start with the negative edge of P5, and furthermore, the output signal P7 of the phase polarity discrimination circuit 5 is input to the α timer 6, and the α timer 6
is configured to invert the output signal P5 by P7. The output signal P of the signal switching circuit 8 is sent to a digital frequency adjustment device 9, and the frequency is adjusted if there is an error that does not depend on temperature.

FIG. 3 is a time chart showing the operation of FIG. 2. FIG. 3a shows the state of the signal when θ=10°C, with the horizontal axis representing time.
output signal P4 of α timer 6, output signal P5 of α timer 6,
This is the output signal P6 of the β timer 7.

Note that the output signal P of the signal switching circuit 8 is shown with the vertical axis representing the frequency; in this case, the upper side is the frequency ₁ of the output signal P1 of the first crystal oscillation circuit, and the lower side is the output signal P2 of the second crystal oscillation circuit. The frequency is ₂ , and the step is equal to the beat frequency _B. P4, P
5, P6 is shown on the vertical axis potential.

The period of the signal P4 is n times the beat period 1/ _B , which is n/ _B , the time ratio of the high level of the signal P5 is α/n, and the time ratio of the high level of the signal P6 is β×
_B /n. The signal switching circuit 8 has P5, P6
is configured to use the higher-frequency crystal oscillation circuit output (P1 in this case) as the output signal while P is at a high level, and the average frequency _P of the output signal P is
is _P = ₂ + (α/n+β× _B /n)× _B .

The values of n, α, and β are set as follows.

n=64 α=43 β=16 seconds Also, ₁ , ₂ , and _B at 10°C are as follows. ₁ = 32768.115Hz ₂ = 32767.427Hz _B = 0.688Hz When _P is calculated from the previous equation, _P = 32768.008Hz, which shows that it has been corrected to be almost equal to F ₀ .

Similarly, FIG. 3b is a time chart showing the state of the signal when θ=40°C.

₁ , ₂ , _{and B} at 40°C are respectively ₁ = 32767.083Hz ₂ = 32768.459Hz _B = 1.376Hz, and since the magnitude relationship of ₁ and ₂ is reversed, P5 is reversed, and as the beat frequency increases, As a result, cycle times are becoming shorter. In this case, the average frequency P of the output signal _P is determined by the formula _P = ₁ + {(n-α)/n + β× _B /n}× _B , and the result is _P = 32768.008 Hz, which is also close to F ₀ . It will be done.

FIG. 4 is a circuit configuration diagram showing the block diagram of FIG. 2 in slightly more detail.

1 is a first crystal oscillator that outputs the signal P ₁ , which includes an oscillation inverter 1a, resistors 1b and 1c, a crystal oscillator 1d, and further 1 and 1e.
It consists of a fixed capacitance capacitor that can incorporate an IC. 2 is a second crystal oscillator that outputs the above-mentioned signal P ₂ , and is composed of an oscillation inverter 2a, resistors 2b and 2c, a crystal oscillator 2d, and fixed capacitors 2f and 2e that can incorporate an IC. has been done. 3 is a phase difference detection circuit, and pulses are generated through each differentiating circuit (that is, three differentiating circuits consisting of a capacitor 3a and a resistor 3d, a capacitor 3b and a resistor 3e, and a further capacitor 3c and a resistor 3f) and inverters 3g to 3k as shown in the figure. The three signals are each a signal P ₁ that captures the rising edge of P ₁
↑, a signal P ₂ ↑ that captures the rising edge of P ₂ ↑, a signal P ₂ ↓ that captures the falling edge of P ₂ , AND gates 3m and 3l detect the rising signal P ₁ ↑ of P ₁ and the rising signal P of P _2, respectively. ₂
↑, the rising signal P ₁ ↑ of P ₁ and the falling signal P ₂ ↓ of P ₂ are used to set and reset the flip-flop 3n. At this time, the rising signal of _P1
The sum of the pulse width of P ₁ ↑ and the rising signal of P _{2 ↑} , the sum of the pulse width of P _{1 ↑} and the falling signal of _{P 2 ↓} is P It is smaller than the half cycle of ₂ to avoid malfunction. _P1
The rising signal P ₁ ↑ is the flip-flop 3n
is sent to the phase polarity discrimination circuit 5 together with the output signal _P3 .

5a and 5b are data type flip-flops that determine whether ₁ < ₂ or ₁ > ₂ from the phase relationship between the rising signal P ₁ ↑ of P ₁ and the signals P ₂ and P ₃ ;
The output signal _P7 of the phase polarity discrimination circuit 5 is ₁ < ₂
The configuration is such that a low level signal is output when ₁ >2, and a high level signal is output when 1> ₂ .
The beat frequency divider circuit 4 is composed of a counter frequency divider 4b of rising operation, and the frequency division ratio is the aforementioned 1/n. Reference numeral 6 denotes an α timer which starts at the rising edge of _P4 , and is composed of a presettable up-down counter 6a and a flip-flop 6b with a rising trigger.

When the present invention is applied to this embodiment, it is necessary to invert the α/n duty signal as described above, so an up-down counter is used, but an exclusive-OR gate may also be used for inversion. 7 is β- which starts at the falling edge of _P5 .
A timer with a presettable counter 7a and a rising trigger flip-flop 7b for counting the divided signal of either P1 _{or P2} or P.
It is composed of: 8 is a signal switching circuit which simultaneously performs both signal switching at a ratio of α:n−α and signal switching for secondary correction. 8
d, 8e are inverters, 8b, 8f, 8g, 8
h and 8i are AND gates, and 8a, 8j, and 8k are OR gates. Here, the OR gate 8a which takes P5 and P6 as input signals, the AND gate 8b and the D type flip-flop 8c which take P1 and P2 as input signals will be explained. P5 and P
6 indicates the time at which the higher frequency crystal oscillator circuit signal should be output, so the output signal of the OR gate 8a will indicate this time, but if the switching operation is directly controlled by this signal, it will be at the end of P6. Due to this switching, there is a probability that a lead error of one pulse of the crystal oscillation circuit signal will always occur. To solve this problem, the timing is determined by the AND signal of P1 and P2 and the D type flip-flop 8c.

As already explained, the signal P maintains an average frequency that does not change depending on the temperature; in other words, it has a constant error regardless of the temperature. Therefore, the signal P is sent to the next zero-order compensation means in order to eliminate the deviation of this average frequency as a timekeeping signal source. The O-order compensation means is generally referred to as digital frequency adjustment, and has, for example, a configuration as shown in FIG. 9. This digital frequency adjustment device 9 is an example of correcting a delay, in which F ₂ to F ₂₀ are frequency dividers for rising operation, 9c, 9d, 9e, and 9f are AND circuits, 9b is an OR circuit, and 9d is an exclusive divider. It is an OR circuit. By inverting the output signal of the flip-flop _F1 by the pulse signals obtained from the four AND circuits, a half period's worth of correction is performed for each inversion. The four pulse signals are signals that do not overlap in timing or frequency, and can be corrected up to a maximum of 30.5 ppm at intervals of an average correction amount of 1.9 ppm by setting the setting terminals _J0 to _J3 . Of course, it is also possible to increase the maximum correction amount by increasing the number of terminals and to correct the advance by modifying the circuit configuration. Note that the counters 6a and 7a are reset at the rising edge and preset at a high level, and are indicated by R and PE, respectively, in FIG.

FIG. 5 is a block diagram showing a conventional example. As in FIG. 2, 1, 2, 3, 4, and 7 are the first crystal oscillation circuit, the second crystal oscillation circuit, and
These are a phase difference detection circuit, a beat frequency division circuit, and a β timer. The output signals are also P as in Fig. 2.
1, P2, P3, P4, and P6. 19 is a digital frequency adjustment device, and 10 is an AND gate. The AND gate 10 is the β timer 7
The beat signal P3 from the phase difference detection circuit 3 is passed through using the high level time of the signal P6 from the phase difference detection circuit 3 as a gate time, thereby creating an output signal P8. The digital frequency adjustment device 19 inputs the output signal P1 of the first crystal oscillation circuit 1, which is a reference crystal oscillation circuit, and divides the frequency thereof, and also adjusts the frequency division ratio according to the number of pulses of the signal P8 from the AND gate 10. The frequency is adjusted in the direction of making the clock advance. With the above configuration, secondary correction of the crystal oscillation circuit is possible,
If the intersection temperature of the temperature characteristics of two crystal oscillation circuits is made to match the ZTC temperature of one of the crystal oscillation circuits, flat characteristics can be obtained. However, the first
If the intersection temperature and ZTC temperature do not match, as shown in the figure, the temperature characteristics will be significantly tilted.

[Effects of the Invention] As described above, according to the present invention, it is possible to digitally adjust the temperature characteristics of a high-precision electronic timepiece without using a trimmer capacitor, which has problems with long-term stability and cost. Ta. This makes it possible for all items to be automatically adjusted using a microcomputer, resulting in dramatic improvements in the precision and cost reduction of quartz clocks.

[Brief explanation of the drawing]

FIG. 1 is a characteristic diagram showing the temperature characteristics of two crystal oscillation circuits used in the temperature-compensated oscillation device of the present invention, FIG. 2 is a block diagram showing one embodiment of the temperature-compensated oscillation device of the present invention, and FIG. Figures a and b are time charts of each signal at 10°C and 40°C of the temperature compensated oscillator of the present invention, Figure 4 is a detailed circuit diagram of Figure 2, and Figure 5 is a block diagram showing a conventional example. It is a diagram. DESCRIPTION OF SYMBOLS 1...First crystal oscillation circuit, 2...Second crystal oscillation circuit, 3...Phase difference detection circuit, 4...Beat frequency division circuit, 5...Phase polarity discrimination circuit, 6...α timer, 7, 17...β timer, 8, 18... signal switching circuit, 9, 19... digital frequency adjustment device.

Claims (1)

[Claims] 1. Two crystal oscillation circuits having frequency-temperature characteristics in which two almost similar quadratic curves are shifted from each other in the temperature axis direction or in both the temperature and frequency axes, and a beat signal is generated by detecting the frequency difference between the two oscillation circuits. a phase difference detection circuit that outputs the oscillation signal from the crystal oscillator circuit; a first timer that counts n beat signals to create a cycle time proportional to the beat signal cycle; A programmable second timer that generates a constant pulse width β by counting, and a frequency correction means that corrects the frequency of the crystal oscillation circuit using the constant pulse width β determined by the second timer as a correction period. In the temperature-compensated oscillator device, a programmable third timer operates at each cycle time to count α of the beat signals to generate a waveform with a duty ratio α/n; An oscillation device with temperature compensation, comprising a signal switching circuit that alternately switches and outputs the output signals of the two crystal oscillation circuits according to the signal.