JPS6234153B2 - - Google Patents

Info

Publication number
JPS6234153B2
JPS6234153B2 JP56134566A JP13456681A JPS6234153B2 JP S6234153 B2 JPS6234153 B2 JP S6234153B2 JP 56134566 A JP56134566 A JP 56134566A JP 13456681 A JP13456681 A JP 13456681A JP S6234153 B2 JPS6234153 B2 JP S6234153B2
Authority
JP
Japan
Prior art keywords
electrode
pair
electrodes
flat
mold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56134566A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5834951A (ja
Inventor
Yasuo Matsumura
Juji Tomita
Shigeshizu Fujita
Shoji Kumano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
Original Assignee
NEC Home Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd filed Critical NEC Home Electronics Ltd
Priority to JP56134566A priority Critical patent/JPS5834951A/ja
Publication of JPS5834951A publication Critical patent/JPS5834951A/ja
Publication of JPS6234153B2 publication Critical patent/JPS6234153B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
JP56134566A 1981-08-26 1981-08-26 ダブルヒ−トシンク形半導体装置の製造方法 Granted JPS5834951A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56134566A JPS5834951A (ja) 1981-08-26 1981-08-26 ダブルヒ−トシンク形半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56134566A JPS5834951A (ja) 1981-08-26 1981-08-26 ダブルヒ−トシンク形半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS5834951A JPS5834951A (ja) 1983-03-01
JPS6234153B2 true JPS6234153B2 (enExample) 1987-07-24

Family

ID=15131327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56134566A Granted JPS5834951A (ja) 1981-08-26 1981-08-26 ダブルヒ−トシンク形半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS5834951A (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE246840T1 (de) * 1994-06-10 2003-08-15 Avx Corp Vorformen für die herstellung von oberflächenmontierbaren festelektrolytkondensatoren und herstellungsverfahren der genannten kondensatoren
EP1742265B1 (en) * 2000-04-19 2013-08-07 Denso Corporation Coolant cooled type semiconductor device
JP4479121B2 (ja) * 2001-04-25 2010-06-09 株式会社デンソー 半導体装置の製造方法
JP5141076B2 (ja) 2006-06-05 2013-02-13 株式会社デンソー 半導体装置
ITMI20112300A1 (it) 2011-12-19 2013-06-20 St Microelectronics Srl Realizzazione di dispositivi elettronici di tipo dsc tramite inserto distanziatore

Also Published As

Publication number Publication date
JPS5834951A (ja) 1983-03-01

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