JPS6233389A - Memory device - Google Patents

Abstract

PURPOSE:To make a dynamic memory high speed by inputting a row address strobe signal, thereafter outputting an address fetch completion signal, changing over the address externally of a dynamic memory based on the completion signal and inputting a column address. CONSTITUTION:A row address strobe signal is supplied from the external of a DRAM 30, a row address fetch signal is generated from this signal, and based on this fetch signal, a column address timing signal is generated. This signal is outputted to the external of the DRAM 30 and impressed to a select terminal of a selector 23. When a column address timing signal is changed, an output address is changed over and its output is changed over from the row address to the column address. When a column address strobe signal is externally received, the column address fetch signal is generated in the DRAM 30, based on this signal, the column address timing signal rises, changes over an output address and changes over the output from the column address to the row address. Thereby, the high speed of a dynamic memory can be corresponded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a device for specifying addresses by multiplexing address information.

[Prior Art] In order to reduce the number of input bins in a dynamic memory, address information is multiplexed and input.

Multiplexing of address information means, for example, when 16-bit address information is required, the address is divided into two parts, and the upper 8 bits (hereinafter referred to as the "low address") and
It is given in the order of the lower 8 bits (hereinafter referred to as "column address").

Furthermore, in order to multiplex address information, it is necessary to generate a timing signal outside the storage element and switch and supply the address information in synchronization with this timing signal. In this case, it is necessary to design the timing by considering the maximum and minimum delay times of each circuit element.

FIG. 5 is a block diagram showing a conventional example of a dynamic memory.

The 16-bit address is divided into a row address (MA8 to MA15) and a column address (MA15) by the -selector 17.
It is divided into MAO-MA7). This divided address is sent to a DRAM (dynamic RAM) 10. In addition, selector 1 is set to the right of address switching signal V).
7 output address is switched.

Here, the column address buffer 13 uses a hold type (a type that requires a long hold time, although the set-up time may be short), and the row address buffer 11 uses a high-speed hold type (a type that requires a long hold time). time>0, and the hold time is short), and efforts have been made to increase the speed of the system.

Furthermore, the timing within the DRAMIO is controlled by a timing generator 16.

FIG. 6 is a block diagram showing, as an example, a part of the timing generator 16 in the conventional example.

A leading edge differentiating circuit 16a generates a row address pulse by differentiating the leading edge of the row address strobe signal,
Based on this row address pulse, the row address buffer 11 takes in the row address, and the leading edge differentiator circuit 16b creates a column address pulse by differentiating the leading edge of the column address strobe signal. Based on this, the column address buffer 13 takes in the column address.

FIG. 7 is a timing diagram showing the operation of the conventional example.

At the start of a memory cycle, the selector 17 outputs a row address, and at the fall of the row address strobe signal, a row address pulse is generated, and the row address buffer 11 takes in the row address, after a predetermined time. , the output address of the selector 17 is switched to a column address, a column address pulse is generated at the fall of the column address strobe signal, and the column address buffer 13 takes in the column address.

After the row address is taken into the row address buffer 11, it is decoded by the row address decoder 12, and then the memory cell array 15 is accessed. On the other hand, the column address is taken into the column address buffer 13 and then decoded and selected by the column address decoder/selector 14 to input and output data.

On the other hand, the period between the rising edge and the falling edge of the row address strobe signal is the precharge time, and when this precharging is completed, the next memory cycle is started and the next address is taken in.

In the above case, timing design is performed taking into consideration the maximum and minimum delay time of each circuit element.

[Problems with the Prior Art] When designing a timing circuit as described above, it is necessary to design the timing by considering the maximum and minimum values of the delay time of each circuit element in consideration of mass productivity. in this case,
Since there is a considerable amount of margin in timing, wasted time occurs.

In other words, the row address must be determined before and after the fall of the o-7 address strobe signal at the start of the memory cycle.On the other hand, considering the variation in the timing of the selector 17, the row address strobe signal There is a limit to shortening the time from the fall of the signal to the time before switching the output of the selector 17. That is, regarding the time from the fall of the row address strobe signal to address switching, it is necessary to maintain a sufficient hold time even if a minimum delay is expected.

Furthermore, it is necessary to allow for a maximum delay in the time from when the row address is switched to the column address until the column address is determined.

On the other hand, regarding the delay time from the fall of the row address strobe signal to the fall of the column address strobe, it is necessary to allow for a minimum time; It is a necessary condition to ensure that the set-up time>Q is not too early.

The above conditions are necessary for error-free operation even in the worst case scenario. but.

Normally, the above-mentioned worst case hardly occurs, so the above-mentioned expected minimum time and maximum time result in wasted time.

Therefore, taking these factors into consideration, in order to shorten the time required to enter an address, it is necessary to use a very fast and consistent element.0 When using a normal element,
The problem is that it will not be able to cope with the expected increase in the speed of dynamic memory in the future, and will become a brake.

[Object of the Invention] The present invention has been made in view of the problems of the above-mentioned conventional example, and an object of the present invention is to provide a storage device that can cope with the increase in speed of dynamic memory.

[Summary of the Invention] In order to be able to cope with the increase in speed of dynamic memory, the present invention outputs an address capture completion signal (column address timing signal) after inputting a row address strobe signal. Based on the address capture completion signal, addresses are switched outside the dynamic memory and column addresses are input.

[Embodiment of the Invention] FIG. 1 is a block diagram showing an example of a DRAM used in an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the DRAM.

The main difference between this embodiment and the conventional example is that a column address timing signal as one of the address capture completion signals is generated and output within the timing generator 31, and the address is determined based on the column address timing signal. This is a point that can be switched.

Components that are the same as those used in the conventional example shown in FIG. 5 are designated by the same reference numerals and their explanations will be omitted.

The selector 23 receives the column address timing signal as a select signal and switches address information.

Next, the operation of the above embodiment will be explained.

FIG. 3 is a time chart showing the operation of the above embodiment.

First, a row address strobe signal is supplied from outside the DRAM 30, a row address capture signal is generated based on the leading edge of this row address strobe signal, a row address is fetched, and then, based on the row address capture signal, a row address capture signal is generated. Then, a column address timing signal is generated.

This column address timing signal is output to the outside of the DRAM 30 and applied to the select terminal of the selector 23.

The selector 23 switches the output address when the column address timing signal changes.

In the above case, the output is switched from row address to column address.

Next, when a column address strobe signal is received from outside the DRAM 30, a column address capture signal is generated within the DRAM 30, and a column address timing signal rises based on the column address capture signal.

In response to the rise of this column address timing signal,
The selector 23 switches the output address. in this case,
Switches its output from column address to row address.

After this, the above operation is repeated.

In the above embodiment, the address is switched in response to the address capture completion signal, and the address capture completion signal is output from the DRAM 30. Therefore, D
In the embodiment described above, there is no need to create timing for address switching outside the RAM 30, and an intermediate timing with no wasted time, such as the address capture completion signal, is created, so that it is possible to cope with higher speeds of the DRAM 30.

FIG. 4 is a block diagram showing the timing generator.

As shown in this figure, the column address timing signal as the address capture completion signal is generated based on the row address capture pulse and the trailing edge of the column address capture pulse.

[Effects of the Invention] According to the present invention, it is possible to cope with an increase in the speed of dynamic memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a DRAM used in one embodiment of the present invention. FIG. 2 is a block diagram showing the above embodiment. FIG. 3 is a time chart showing the operation of the above embodiment. FIG. 4 is a diagram showing the timing generator in the above embodiment. FIG. 5 is a block diagram showing a conventional DRAM. FIG. 6 is a block diagram showing a timing generator in a conventional example. FIG. 7 is a timing chart showing the operation in the conventional example. 11...Row address buffer. 13... Column address buffer, 15... Memory cell array, 23... Selector, 30... DRAM, 31... Timing generator. Patent applicant: ASCII Co., Ltd. Figure 1, Figure 2, Group 4, -31 r---=----7-i

Claims (2)

[Claims] (1) A storage device that accesses a memory by switching and multiplexing address information, the storage device being characterized in that it outputs an address capture completion signal based on an address strobe signal. (2) The storage device according to claim 1, wherein the address capture completion signal causes the address information to be switched outside the storage device.