JPS6232554A - Extended memory controlling system - Google Patents

Abstract

PURPOSE:To execute a program at a high speed by restarting an execution of program at the time point when a block transfer from a backing store bus been completed, in case when no necessary information exists in an actual extended storage device, when executing a block transfer instruction between a virtual extended storage device and a main storage. CONSTITUTION:In case when a retrieval by an address converting mechanism 5 is unsuccessful, a transfer instruction executing mechanism 2 sets an instruction counter to a main storage address in which this block load instruction exists, and thereafter, starts a process control mechanism 4 by a wait command signal W and also starts a hierarchy control mechanism 6 by an assigning command ST2, in order to set a process which has executed this instruction to a wait state. When a block transfer from a backing store device 9 is completed, the hierarchy control mechanism 6 starts a process control mechanism 4 by an assignment completing signal C2. The process control mechanism 4 receives it and executes a release of the wait state.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a control method for extended storage having a hierarchical structure.

(Prior art and its problems) Conventionally, a method called the virtual memory method has been known, and this technology is widely used in general-purpose computers (Kaneda Hiroki Electronic Computer (21F92-98 Corona Publishing 1978).
Published in 2013).

By providing a virtual main memory with a vast address space, it allows the user to have virtually unlimited capacity.
In a virtual memory computer system, programs and data are accessed using virtual addresses.

Virtual memory actually consists of main memory and a ninth backing store that holds data that cannot be stored in main memory. In a computer system that employs a page-knob virtual memory method, when accessing main memory, it is necessary to check whether the page containing the specified virtual address is valid on real main memory, that is, whether it is allocated on real main memory or not. , it is checked whether it is available or not, and if it is valid,
The corresponding page on the real main memory is immediately accessed, and if it is not valid, that is, when a page slip occurs, this program is interrupted, a page on the main memory is allocated to this light, and the corresponding page is backed up. The program is imported from the store to the main memory and then resumes execution of the program.

That is, if a page fault occurs, the process executing this program will be interrupted and placed in a waiting state. Generally, the processor executes other processes until the above-mentioned page lift process is completed and the process becomes executable.

It is possible to apply such a concept of virtual memory to an extended storage device in a computer system.

Expanded storage is a storage device connected to main memory that enables high-speed block data transfer to and from main memory. , which aims to improve the processing power of computer systems.

However, conventional expanded storage devices merely provide high-speed block transfer devices;
When a person creating a program intends to use this, he/she must be aware of the capacity of the extended storage device, decide on the information to be stored on the extended storage device, and its storage location, and based on this, It is necessary for the program to issue commands for block transfers to the main memory, block transfers from the expanded storage device to the disk device, and block transfers from the disk device to the expanded storage device, which not only complicates program creation but also increases the 1 fC if the storage capacity changes
However, there was a problem in that the allocation of information to the expanded storage device had to be reconsidered.

The present invention provides a virtual extended storage device with a sufficiently large address space as an extended storage device, and allows a program to treat it as if it were a large extended storage device with virtually unlimited capacity. It is something. Hereinafter, this will be referred to as a virtual extended storage device.

This eliminates the need for the program to control the allocation of information on the extended storage device, the data transfer with the disk device based on this allocation, and the like.

Of course, even in this case, it is possible to effectively improve performance by issuing appropriate commands from the program.

Virtual expanded storage actually consists of a relatively small-capacity expanded storage (high-speed section) and a large-capacity backing store (low-speed section), and when accessing virtual expanded storage, the requested block is If it exists in expanded storage, it immediately transfers the data to and from main storage at high speed; if it does not exist, it allocates this refined storage location in virtual expanded storage and retrieves the required data from backing store. The block is transferred to the expanded storage device, validated, and then transferred to and from the main memory.

As mentioned above, high-speed block data transfer is possible between the extended storage device and the main storage device, and if the necessary block exists in the extended storage device (high-speed section), the main memory Since the block transfer to and from the program is completed quickly, the transfer instruction is completed immediately, and the program can continue with the next instruction without entering a wait state.

On the other hand, if it does not exist (hereinafter referred to as a miss time), it will take a long time to transfer the block from the backing store (low speed part: usually realized by a magnetic disk device). It is necessary to temporarily put this program into a waiting state so that it can hand over the 10 sets to another program.

(Objective of the Invention) An object of the present invention is to immediately perform a block transfer as the execution of a virtual expanded storage device when necessary information exists in the real expanded storage device when executing a block transfer instruction between the main memory and the virtual expanded storage device. If the task that executed the program does not exist, the task that executed the program is placed in a waiting state, and program execution is resumed when the transfer from the backing store to the real extended memory is completed, thereby eliminating unnecessary task switching. In addition, an object of the present invention is to provide an extended storage control method that can effectively utilize a processor, speed up program execution, and improve the processing capacity of a computer system. In an extended storage control method for an information processing apparatus, the information processing apparatus includes a virtual extended storage device having at least two hierarchies, a high-speed section and a low-speed section, and a main storage device that transfers data in blocks between the high-speed section and the high-speed section. It has an instruction code section indicating that it is a block transfer instruction between a storage device and the virtual extended storage device, a first operand section that specifies a main memory address, and a second operand section that specifies a virtual extended storage address. A block transfer command is prepared, and in response to a search command instructing to search for a block specified by the second operand section, when a block to be searched exists in the high speed section, a presence signal is generated. address converting means for converting a virtual extended memory address in the operand section of the operand section into a virtual address in the high speed section and generating an absence signal when the block to be searched does not exist in the high speed section; block transfer command execution means for generating a search command, generating a first activation signal in response to the supply of the presence signal, and generating a second activation signal and a wait signal in response to the supply of the absence signal; , in response to the supply of the first activation signal, block transfer is performed between the real address of the high-speed section obtained by the address conversion means and the main memory address specified by the first operand section. block transfer control means for generating a first completion signal in response to completion;
hierarchical control means for activating a block of the virtual extended storage device designated by the second operand section in the high speed section in response to the supply of the activation signal, and generating a second completion signal in response to this completion; and process control means for placing the process that issued the block transfer command in a wait state in response to the supply of the wait signal, and causing the process to be executed by the block transfer command in response to the supply of the second completion signal. configured.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In this embodiment, it is assumed that the virtual expanded storage device is composed of the real expanded storage device 8 and the backing store device 902 level.

In this embodiment, the block transfer instruction has an instruction code section and first and second operand sections. The first operand S indicates a real block address of the main storage device 7, and the second operand section indicates a virtual block address of the virtual expanded storage device.

As block transfer commands, a block store command for a detailed block transfer from the main storage device 7 to the extended storage and a block load command for a detailed transfer in the reverse direction are provided.

The value of the instruction code section of the instruction register l is determined by the instruction decoder 11.
The value of the first operand part is applied to the main memory device 7 as a block address. Second
The value of the operand part is applied to the address translation mechanism 5 and the hierarchy control mechanism 6. The output of the instruction decoder 11 is applied to the transfer instruction execution mechanism 2, which further includes:
A coincidence detection signal F, which is the output of the address conversion mechanism 5, and a transfer completion signal C1 from the block transfer control mechanism 10 are also applied. The transfer instruction execution mechanism 2 sends search instructions 1. to the address conversion mechanism 5. Block transfer control mechanism lO
For block transfer command ST1 with main storage device 7,
An allocation command STz is applied to each hierarchical control mechanism 6. Further, a wait command signal W, which is an output of the transfer command execution mechanism 2, is applied to the process control mechanism 4. The process control mechanism 4GC is also applied with an allocation completion signal C2 from the hierarchical control mechanism 6. .

The address conversion mechanism 5 is an elaborate mechanism that converts a virtual block address specified by the second operand part of the instruction register l into a real block address for a block of virtual expanded storage allocated on the real expanded storage device 8. , the converted real block address is applied to the real extended storage device 8. Further, a signal indicating whether the f conversion is successful or unsuccessful (coincidence signal 2) is applied to the transfer command execution mechanism 2.

The hierarchical control mechanism 6 is the ninth mechanism that manages the allocation of 10 disks to the real expansion storage device 8 and the backing store device 9, and the data transfer between the two devices based on the determination of this allocation. The completion signal C2 is applied to the process control mechanism 4.

Next, the operation of the extended storage control method shown in FIG. 1 will be explained in the case of a block load instruction.

When an instruction is read from the main memory 7 and stored in the instruction register l, and the instruction decoder 11 detects that the instruction is a block load instruction, the transfer instruction execution mechanism 2 is activated and the address conversion mechanism 5 is Then, search command I is issued.

If the search is successful, that is, if the block of the virtual expanded storage device specified by the second operand part of the instruction exists in the real expanded storage device 8, the block transfer control mechanism l
A block transfer command STl is issued to O, thereby the address translation mechanism 5 obtains the t real extended storage device 8.
A transfer of the block is started from the storage location specified by the real block address in the main memory 7 to the storage location specified by the first operand portion of the instruction register l.

When the block transfer control mechanism 10 completes the block transfer, the transfer instruction execution mechanism 2 is notified by a transfer completion signal C1, thereby completing the block load instruction.

If the search in the address translation mechanism 5 is unsuccessful, that is, if the block of the virtual extended storage device specified by the second operand part of the instruction register l does not exist in the real expanded storage device 8, the transfer instruction execution mechanism Step 2 sets the instruction counter to the main memory address where this block load instruction exists, and then activates the process control mechanism 4 with a wait command signal W in order to place the process that has passed this instruction T in a wait state. At the same time, the hierarchical control mechanism 6 is activated by the assignment command 8T2. The process control mechanism 4 receives the wait command signal w2 and puts this process into a wait state. In response to the allocation command 5T2t-, the hierarchical control mechanism 6 determines the storage location in the real expanded storage device 8 to which the block of the virtual expanded storage device specified by the second operand part of the instruction register I is to be allocated, and this determines the storage location of the 9th block to be written. If so, this is written back to the backing store device 9, and the block at the corresponding storage location in the backing store device 9 is transferred to the determined ninth storage location in the actual expansion storage device f8, and in accordance with this new allocation. The address translation mechanism 5 is also updated. When the block transfer from the batch door device 9 is completed, the hierarchical control mechanism 6 activates the process control mechanism 4 in response to the allocation completion signal C2. Process control mechanism 4
In response to this, it issues a block load command and releases the wait state at the ninth point when it restarts the process that is in the 9-eight state because the necessary block in the real extended storage device 8 is not valid. When this process is made executable by the process control mechanism 4 and a processor is allocated, the instruction counter indicates the previous block load instruction, so this instruction will be executed again. Since the necessary blocks exist in memory 8, block transfer to main memory 7 can be executed immediately.

It is clear that the invention is not limited to the examples. For example, the format of the block load/block store instruction in this embodiment is not limited to this embodiment. Various conventionally known addressing methods can be applied to both the second operand.
Naturally, the methods of implementing the present invention may also differ. In addition, in the description of this embodiment, the specific implementation methods of the instruction decoder, transfer instruction execution control mechanism, address translation mechanism, etc. are not directly related to the gist of the present invention, and Since these can be realized using conventionally known techniques, it is clear that various realizations can be considered.

(Effects of the Invention) In the present invention, when necessary information exists in the real expanded storage device when executing a block transfer instruction between the main memory and the virtual expanded storage device, the block transfer is performed immediately as the execution of this instruction. , if it does not exist, the task that executed the program is placed in a wait state and the block transfer from the backing store to the real extended memory is completed and the program execution is resumed at a fixed point, thereby saving unnecessary task switching costs. This has the effect of making effective use of the processor, speeding up program execution, and improving the processing capacity of the computer system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. l...Instruction register, 2...Transfer instruction execution mechanism, 4...Process control mechanism, 5...
... Address translation mechanism, 6 ... Hierarchical control mechanism, 7 ... Main storage device, 8 ... Real expansion storage device, 9 ... ... Backing up 7. Store device, lO・
...Block transfer control mechanism, 11...Instruction decoder. f1 country

Claims (1)

[Claims] In the expanded storage control method for an information processing device, the information processing device includes a virtual expanded storage device having at least two hierarchies, a high-speed section and a low-speed section, and a main storage device that transfers data in blocks between the high-speed section and the high-speed section. an instruction code section indicating that the instruction is a block transfer instruction between the main storage device and the virtual extended storage device, a first operand section specifying the main memory address, and a second operand section specifying the virtual extended storage address. and generating a presence signal when the block to be searched exists in the high-speed section in response to a search command instructing to search for the block specified by the second operand section. address converting means for converting a virtual extended memory address in the second operand section into a real address in the high speed section and generating an absence signal when the block to be searched does not exist in the high speed section; Block transfer command execution means for generating the search command, generating a first activation signal in response to the supply of the presence signal, and generating a second activation signal and a wait signal in response to the supply of the absence signal. and the first
In response to the supply of the activation signal, block transfer is performed between the real address of the high-speed section obtained by the address conversion means and the main memory address specified by the first operand section, and in response to the completion of the transfer. block transfer control means for generating a first completion signal in response to the supply of the second activation signal; and enabling the block of the virtual extended storage device designated by the second operand section in the high speed section in response to the supply of the second activation signal. hierarchical control means for generating a second completion signal in response to this completion;
and process control means for placing the process that issued the block transfer command in a wait state in response to the supply of the wait signal, and causing the process to be executed by the block transfer command in response to the supply of the second completion signal. An extended storage control method featuring: