JPS63201839A - Logical simulation device - Google Patents

Abstract

PURPOSE:To shorten the computer processing time of a logical simulation by equivalently modeling and executing the contents of the processing of a microprogram. CONSTITUTION:A microprogram execution control logic circuit 1 transmits the leading address ADR (address 1 in an example) and the start signal STRT of the microprogram to a microprogram execution logic circuit 2. When a microprogram execution pseudo procedure 3 receives a driving signal, it decides whether the pseudo routine of said microprogram is registered in said procedure 3 or not from the leading address ADR of the simultaneously received microprogram. If the routine is registered, a suppression signal (SUP) for suppressing the execution of the microprogram is transmitted to the microprogram execution logic circuit 2. Thereafter, said procedure 3 selects the required microprogram pseudo routine required the leading address of the received microprogram and equivalently models the contents of the processing described in the microprogram.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic simulation device for an information processing device.

[Conventional technology]

An example of logic simulation of microprogram execution according to the prior art will be explained with reference to FIGS. 2 and 3.

FIG. 2 shows an example of a logic circuit that executes a microprogram, and is composed of a microprogram execution control logic circuit 1 that instructs execution of the microprogram, and a microprogram execution logic circuit 2 that executes the microprogram.

The microprogram execution logic circuit 2 further includes a control storage (C8) that stores the microprogram.
) 5. Control storage address register (C
8AR) 6. Control storage data register (C8
DR) 7, a decoder (DEC) 8 that decodes each function written in the microprogram, and a plurality of function execution units 9 that execute each function of the microprogram based on the decoding results.

The function execution unit 9 further includes a memory device (MEM) 10 for storing data, a memory device address register (MAR) 11 for holding an access address of the memory device,
A register A (RA) 12 that holds data, a register B (RB) 13, a register C (RC) 14, an adder (ADD) 15 that adds data, and a storage device (
MEM) 10 and register A (RA) 12, register B
It is composed of a data bus (BUS) 16 and the like for switching and transmitting data to and from (RB) 13.

In FIG. 2, the control storage (CS) 5 and the storage device (MEM) 10 are pseudo procedures whose access operations are modeled in order to improve the operability of logic simulation.

FIG. 3 shows an example of a microprogram executed by the logic circuit shown in FIG.
Read the data at address 1'100'X and '200'
Write processing to address 100'X of 10 is performed.

Hereinafter, the operation of the microprogram will be explained based on FIGS. 2 and 3.

First, the microprogram execution control logic circuit 1 sends the start address (ADR: address 1 in this example) of the microprogram to be executed and a start signal (STRT) to the microprogram execution logic circuit 2. Launch execution.

In response to this, the microprogram execution logic circuit 2
Set the sent ADR to C3AR6, read the microprogram from C85 at that address, and
Set to R7. , C3DR7, the individual functions written in the microprogram are decoded by the DEC 8, and each function is executed by the corresponding function execution unit 9.

When all functions of the microprogram at the beginning (address 1 in this example) have been executed, the microprogram read address held in C3AR6 is updated (address 2 in this example). Based on the updated microprogram read address, the next microprogram is read and the microprogram at address 2 is also executed in the same manner as the microprogram at address 1 was executed.

Thereafter, all addresses of the microprogram are executed in the same manner.

In this example, specifically, the microprogram performs the following operations.

Address 1: Set '100' X to MARII.

Address 2: MEMIO (7) '100' Read the data at address X and set it to RA12 via BUS16. At the same time, '200' X is set in MARll for the next MEMIO access.

Address 3: '200' of MEMIO Read the data at address X and set it to RB13 via BUS16.

Address 4: Add the data of RA12 and RB13 and set the result to RC14.

At the same time, for the next MEMIO access, '
Set 100'X.

Address 5: RC14 data to ME via BUS16
Write to address '100'X of MIO.

In this way, in the logic simulation of microprogram execution, the corresponding logic circuits and pseudo procedures (in this example, C85 and MEMIO) operate one by one based on the individual functions described in the microprogram, and the microprogram is executed one by one. Running.

Incidentally, related technologies of this type include, for example, (1) Transactions of the Information Processing Society of Japan VOL, 21N0.5
SEP, 1980 P, 354 Super Large Computer
Logic simulation of HITACM-200H.

(2) FUJITSU, 37, 2. (03,198
6) P, 136 EACOM M-780 development DA system.

etc.

[Problem that the invention seeks to solve]

In this manner, in the logic simulation of microprogram execution according to the prior art, the corresponding logic circuits and pseudo procedures operate one by one based on the individual functions described in the microprogram.

Therefore, even if the microprogram and microprogram execution logic circuit have already been confirmed to operate normally in the previous logic simulation, each time the logic simulation of microprogram execution is performed, the logic There was a problem in that circuits and pseudo-procedures operated, and it took a long time to execute the microprogram.

In particular, in the case of logic simulation where interrupt operations occur frequently, the microprogram for interrupt processing is generally very long, and its execution requires a lot of logic simulation time.

An object of the present invention is to reduce the computer time required for logic simulation to execute a microprogram.

[Means for solving problems]

The above object is achieved by a pseudo-procedure for executing a microprogram, which equivalently models a microprogram and a logic circuit (including necessary pseudo-procedures) for executing the microprogram.

[Effect]

The above-mentioned pseudo procedure is activated by activation information issued when the logic circuit attempts to execute a microprogram.

The activated pseudo procedure inhibits the execution of the microprogram by the logic circuit, and then equivalently models and executes the processing content described in the microprogram.

After the execution is completed, the inhibition of microprogram execution that was initially applied to the logic circuit is released, a termination signal is sent to the logic circuit, and the processing of the pseudo procedure is ended.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 3.

Microprogram execution pseudo procedure 3 shown in Figure 1
is a pseudo procedure that equivalently models and executes the processing contents described in a microprogram instead of a logic circuit.

The microprogram execution control logic circuit 1 sends the microprogram start address (ADH: address 1 in this example) and a start signal (STRT) to the microprogram execution logic circuit 2.

The microprogram execution pseudo procedure 3 detects the start signal (STRT), and at the same time, from the received microprogram start address (ADH), the pseudo routine of the microprogram is inserted into the microprogram execution pseudo procedure 3. , determine whether it is registered or not.

If it is not registered, the process of the microprogram execution pseudo procedure 3 is immediately finished, and the execution of the microprogram is started by the microprogram execution logic circuit 2, as in the prior art.
Leave it to me.

If it has been registered, an inhibition signal (S) is sent to the microprogram execution logic circuit 2 to inhibit execution of the microprogram.
UP) is sent. Thereafter, the microprogram execution pseudo-procedure 3 selects a necessary microprogram pseudo-routine from the start address of the received microprogram, equivalently models and executes the processing contents described in the microprogram. Here, assuming that the microprogram used in this embodiment is shown in FIG. data and '20
The data at address 0' Describe (1) L A, 100...M's '100' X
Read address data to REG#A.

(2) A A, 200...Add the data of REG#A and the data of address '200'X of M, and store the result in REG#A.

(3) ST A, 100...Write the data of REC4A to address '100'X of M.

There are three steps.

When the microprogram execution pseudo-procedure 3 finishes executing the microprogram pseudo-routine, the microprogram execution pseudo-procedure 3 transmits the inhibit signal (
SUP) is released, an end signal (END) is sent to the microprogram execution control logic circuit 1, and the process ends.

〔Effect of the invention〕

According to the present invention, since the processing contents of a microprogram can be modeled and executed isometrically, the computer time for logic simulation for executing the microprogram can be reduced.
It has a big effect.

[Brief explanation of the drawing]

FIG. 1 is an operational diagram of a logic simulation that executes a microprogram according to an embodiment of the present invention, and FIG.
FIG. 3, which is an operational diagram of a logic simulation for executing a microprogram according to the prior art, is an explanatory diagram showing an example of a microprogram used to explain the present invention. 1... Microprogram execution control logic circuit, 2...
・Microprogram execution logic circuit, 3...Microprogram execution pseudo procedure, 4...Storage device, 5
...Control storage, 6.Control storage address register, 7.Control storage data register, 8.Decoder, 9.Function execution unit, 10.Storage. device, 11... storage device address register, 12.
...Register A, 13...Register B, 14...Register C115...Adder, 16...Data bus.

Claims (1)

[Claims] 1. In a logic simulation device that executes a microprogram, the microprogram and the logic circuit that executes the microprogram are put together, a pseudo procedure that equivalently models and executes the processing contents of the microprogram is provided, and the microprogram is executed. A logic simulation device characterized in that logic simulation time is reduced by equivalently executing a microprogram using the pseudo procedure instead of a logic circuit.