JP3163196B2 - Instruction interruption information storage control method in virtual storage control - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a virtual storage control technique for a computer system, and more particularly to a method for efficiently storing instruction interruption information when a translation exception is detected during an address translation process.

[0002]

2. Description of the Related Art In a computer system of a virtual storage system, the address of an instruction in an application program is represented by a logical address in a virtual space, and is converted into a real address of a memory when the instruction is executed, and the memory is accessed. The virtual space is managed using segments and pages, and virtual storage control is performed to dynamically allocate the real space to the real space of the real memory.

In the process of converting a logical address of an instruction issued in an application program into a real address, if there is no real address to be converted, that is, a virtual page of a virtual space containing the virtual address is stored in a real memory. When there is no real page allocation,
Since address translation is impossible, it is detected as a translation exception, and the OS is interrupted to perform real page allocation processing.

[0004] By the way, an instruction for executing a simple function is:
Even if a conversion exception occurs during the processing, it is possible to execute again from the beginning after allocating a real page. However, if a conversion exception occurs during the processing of an instruction having many functions, it is often impossible to re-execute the instruction from the beginning. For example, an MO having a function of transferring a plurality of data in one area to another area with one instruction.
In the case of a VE (area transfer) instruction, if a conversion exception occurs during the conversion of the transfer destination address of the intermediate data, at that point, part of the transferred data in the transfer source area has already been destroyed and the instruction cannot be re-executed. Sometimes it is possible. For this reason, the instruction processing is interrupted by the interruption due to the conversion exception, the interruption information necessary for restoring the CPU state at that time is saved, the CPU state is restored after the real page is allocated, and the instruction processing is interrupted. Control is performed to restart from the point in time. Next, details of the control will be described.

FIG. 3 is an explanatory diagram showing a method of controlling storage of instruction interruption information in a conventional example. In the figure, 1 is a CPU
And represents a hardware function. Reference numeral 2 denotes an OS (operating system), 3 denotes a memory, 4 denotes a fixed area in which instruction interruption information is saved, and 5 denotes a task control area (TCB) in which control information for managing tasks is set. It is a number representing an operation procedure. FIG. 4 shows the information contents of the fixed area and the task control area.

When the CPU does not allocate a real memory to a virtual address to be accessed during instruction processing, the CPU first interrupts the instruction processing and generates a conversion exception interrupt. The information (interruption information) inside the CPU necessary to restart the instruction processing is saved in the fixed area 4 on the memory, and the program status word (PS
A flag (IR flag) indicating interruption is set in W).

When a conversion exception interrupt occurs, an operating system (OS) performs a process of allocating a real memory to the virtual address where the exception has occurred. If input / output is required in this process, the interruption information is stored in the task control area (TC
The task is transferred to the save area B) and saved, and the task in which the exception has occurred is put into a waiting state, and another task is put into an execution state.

When the real memory allocation is completed, the OS restores the interruption information from the TCB to the memory fixed area, returns the task in which the exception has occurred to the execution state, and passes control to the task.

The CPU determines from the IR flag of the PSW that it is in the interrupted state, restores the instruction processing state from the interrupt information, and resumes processing from the point where the exception occurred.
Here, the interruption information necessary for resuming the interrupted instruction differs depending on the architecture of the hardware constituting the CPU. Generally, the amount of data ranges from several bytes to several hundred bytes. For example, in the case of the MOVE instruction, an area for two addresses and one counter is required, and in the case of a decimal operation instruction, the data amount is 16 since it is necessary to store 16-digit data as an intermediate operation result. More. In the conventional virtual storage control device, the area for storing the interruption information is a memory fixed area (fixed address / fixed length) uniquely defined by the CPU architecture.
Met.

For this reason, the OS saves the specified fixed-length area to an area such as the TCB and restores it from the area regardless of the actual effective length of the interruption information. In some cases, it contained a lot of waste. Also,
As a result of the redesign of the CPU, if the information defining the internal state of the CPU increases, the interruption information also increases, and the OS needs to be changed.

[0011]

SUMMARY OF THE INVENTION The present invention relates to an OS for storing instruction interruption information when a translation exception occurs during address translation.
In addition to eliminating unnecessary transfer processing in
It is an object of the present invention to optimize the processing of the OS so as to expand the range of the architecture of the CPU that can be applied in common without modifying the OS.

[0012]

According to the present invention, the OS sets an area having a size corresponding to the maximum information amount of the instruction interruption information of the CPU as a task-specific area as a save area for storing instruction interruption information. . On the other hand, in the fixed area of the memory, only the address is stored and can be referred to from the CPU.
This eliminates the need for processing for storing instruction suspension information in a fixed area and further transferring the information to a task control block (TCB) as in the related art.

In the present invention, a special instruction is used in advance.
And notifies the OS of the maximum information amount of the instruction interruption information,
The OS determines the size of the instruction interruption information save area to be set in the task unique area based on the notified maximum information amount value. Thus, even if the maximum information amount of the instruction interruption information changes due to a difference in the architecture of the CPU, it is possible to easily adapt without changing the OS itself.

According to the configuration of the present invention, a computer system of a virtual memory system, and a central processing unit which is interrupted when a translation exception is detected in an address translation for translating a logical address of an issued instruction into a real address. A system for saving instruction interruption information on the state of a processing unit in a memory
In the instruction interruption information storage control method in the virtual storage control , the OS provides a save area in the memory for storing the instruction interruption information in the task-specific area when the task is generated , It sets the address in the control register of the fixed region or the central processing unit in the memory, a central processing instrumentation
When the above conversion exception is detected, the instruction processing is interrupted to read the address set in the fixed area or the control register of the central processing unit, and the instruction is interrupted to the save area on the memory determined by the address. When the information processing is performed and the interrupted instruction processing is resumed, the instruction interruption information on the memory determined by the address set in the fixed area or the address set in the control register of the central processing unit is read, and the central processing unit It is characterized by performing processing for restoring the internal state. Furthermore, in the above configuration,
The maximum amount of instruction interruption information to the OS using special instructions
The OS has been notified for each task created.
A save area of a size commensurate with the maximum amount of instruction interruption information
The feature is that it is set in the task specific area on the memory.
I do .

FIG. 1 is a diagram illustrating the principle of the present invention. In FIG. 1, reference numeral 1 denotes a CPU of a virtual storage system, which has an address conversion mechanism for converting a logical address in an instruction into a real address when executing an instruction of an application program. If the corresponding real page does not exist and a conversion exception is detected, the instruction processing is interrupted and the OS is interrupted. When the real page allocation processing is completed, the suspended state is restored, and the instruction processing is resumed.

Reference numeral 2 denotes an OS, which has a virtual storage control function for allocating a virtual space to a real memory. Further, it has a function of setting an area for saving instruction interruption information of the CPU 1 at the time of occurrence of a conversion exception with a size designated as the maximum information amount and referable to the CPU 1.

Reference numeral 3 denotes a memory, which functions as a main memory for the CPU 1. Reference numeral 6 denotes a task-specific area.
Is an area such as a task control block (TCB) acquired as a resource for each task.

Reference numeral 7 denotes an instruction interruption information save area, which is provided by OS2.
The instruction interruption information is stored by the CPU 1 when a conversion exception occurs. Reference numeral 8 denotes a fixed area of the memory. The start address of the instruction interrupt information save area 7 is set by the OS 2 and is referred to by the CPU 1 at the time of instruction interruption or instruction interruption recovery, and the save area 7 is accessed.

[0019]

The operation of the present invention shown in FIG. 1 will be described with reference to the procedure numbers and the like in the figure.

When executing a job of an application program, the OS 2 acquires a task specific area 6 in the memory 3 as one of task resources each time a task is generated, and simultaneously sets an instruction interruption information save area 7 and a fixed area 8 And store the address. The size of the save area 7 set by the OS 2 can be externally specified by a command,
It is possible to easily adapt to a change in the maximum information amount of instruction interruption information due to a difference or change in CPU architecture.

When the CPU 1 does not convert the logical address to the real address by the address conversion of the instruction being executed and detects a conversion exception, the CPU 1 interrupts the instruction processing, reads the address from the fixed area 8, and uses the address as the save area. 7 to store the instruction interruption information and raise an interrupt to OS2.

The OS 2 assigns a real page to a virtual page including a logical address to be converted which has become a conversion exception by interruption due to a conversion exception, and if necessary,
Performs in / out input / output processing. When this interrupt processing is completed, the CPU 1 accesses the save area 7 again using the address of the fixed area 8, reads the instruction interruption information, restores the interrupted state of the CPU, and resumes the instruction processing.

By performing such an operation, even when the OS performs input / output processing in the interrupt processing of the conversion exception, it is not necessary to save the instruction interruption information again, so that the processing time is shortened, and Since the maximum information amount can be specified to the OS, the same OS can be applied to various CPUs that differ only in the maximum information amount of the instruction interruption information.

[0024]

FIG. 2 shows an embodiment of the present invention. In FIG. 2, 1 is a CPU, 2 is an OS, 3 is a memory, 8 is a fixed area for storing the address of the interrupt information save area, 9 is a special instruction for notifying the OS of the maximum number of bytes of the interrupt information, Reference numeral 10 denotes a fixed area prepared for setting the maximum number of bytes of the interruption information. 11-0, 11-1, ..., 1
1-N are task 0, task 1,..., Task N, respectively.
, Ie, a task-specific area such as TCB. 1
, 12-N are suspend information save areas allocated in the resources of task 0, task 1, ..., task N, respectively, and have a size corresponding to the maximum number of bytes of the suspend information. With.

The special instruction 9 is an instruction for storing the value of the maximum number of bytes of the interruption information specified by the operand in the fixed area 10 of the memory specified by the operand address, and the administrator issues this special instruction. Then, the OS 2 is instructed on the maximum number of bytes of interruption information that is optimal for the architecture of the CPU 1.

Each time the OS 2 generates a task, the OS 2 stores the task resources on the memory 3 as 11-0, 11-1,.
Assign as follows. At that time, the maximum number of bytes of the interruption information stored earlier is read by referring to the fixed area 10, and
The interruption information saving area corresponding to the size of the value is set to 12-0, 1
Each task resource 1 such as 2-1,..., 12-N
1-0, 11-1,..., 11-N. The address serving as a pointer to the interruption information save area of the task in the execution state is stored in the fixed area 8 by the OS 2.
When the task executed by the OS 2 is switched, the fixed area 8
The addresses in the table are also updated corresponding to the task-specific save area. Regardless of which task is being executed, the firmware or the control program of the CPU 1 accesses the fixed area 8 when a translation exception is detected at the time of address translation, reads the address, and saves the address in the task resource pointed to by the address. To store the suspend information.

If the OS2 needs to perform input / output processing with the disk device after allocating a real page to the page of the logical address for which the conversion failed in the interrupt processing of the conversion exception, it was being executed. The task is placed in a waiting state and another executable task is started. However, since the suspend information is already stored in the save area of the memory resource of the task in the waiting state, the transfer processing as in the conventional example of FIG. 3 is performed. No need to do.

[0028]

According to the present invention, the interruption information when the conversion exception is detected is directly stored by the CPU in the task-specific area instead of the fixed area, so that the processing is simplified and the efficiency is improved.

According to the present invention, even if the maximum information amount of the interruption information changes due to a change in the architecture of the CPU, the above-described special instruction can be issued to notify the OS of the new maximum information amount easily. Therefore, it is possible to adapt to a change in the CPU architecture or a CPU having a different architecture without modifying the OS itself, thereby reducing the development burden.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a conventional example.

FIG. 4 is an explanatory diagram of information contents of a fixed area and a task control area of a memory in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 OS 3 Memory 6 Task specific area (TCB) 7 Instruction interrupt information save area 8 Fixed area of memory

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Satoru Araki 98-2, Unoki-nu, Unoki-cho, Hebei-gun, Ishikawa Pref. Within Fujitsu Limited (72) Inventor Masahiro Urata 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Within Fujitsu Limited (56) References JP-A-53-84540 (JP, A) JP-A-54-1873 (JP, A) JP-A-61-117635 (JP, A) JP-A-5-143331 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 12/08-12/12 G06F 9 / 46

Claims (2)

(57) [Claims] 1. An instruction relating to a state of a central processing unit which is interrupted when a translation exception is detected in an address translation for translating a logical address of an issued instruction into a real address in a computer system of a virtual storage system. In virtual memory control of a system that saves suspend information on memory,
In the instruction interruption information storage control method , the OS provides a save area in the memory for storing the instruction interruption information when the task is generated in the task specific area, and stores the address of the save area in a fixed area in the memory or the central processing unit. The central processing unit performs instruction processing when the above conversion exception is detected.
Then, the address set in the fixed area or the control register of the central processing unit is read, the instruction interruption information is stored in the save area on the memory determined by the address, and the interrupted instruction processing is resumed. In the case, the virtual storage control is characterized by reading out the instruction interruption information on the memory determined by the address set in the fixed area or the control register of the central processing unit and restoring the internal state of the central processing unit. Control method for storing instruction interruption information. 2. The method according to claim 1, wherein the special instruction is set in advance.
To notify the OS of the maximum amount of instruction interruption information
The OS sets an evacuation area of a size corresponding to the maximum information amount of the notified instruction interruption information in a task-specific area on a memory for each generated task. Storage control method.