JPH11120011A - Interruption processing method and multitask execution system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently use a memory for an input/output interruption in the multitask execution system. SOLUTION: When tasks 131 to 134 operate while having individual logical spaces, this system 100 is provided with a logical space switching means 135 which switches only the logical spaces of the tasks. When an interruption corresponding to an input/output request that one of the tasks has issued is initiated, the logical space switching means 135, (1) saves register values needed for the interruption process, (2) switches the logical space to the logical space of the task having issued the input/output request, (3) executes an interruption process routine, (4) reswitches the logical space to the logical space right before the switching by the said process (2), and reloads the register values saved in the said (1).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multitask execution system, and more particularly to a method for efficiently processing an input / output interrupt.

[0002]

2. Description of the Related Art In a multitasking execution system in which a plurality of programs (tasks) operate in parallel, when one task requests input / output and waits for completion of input / output, another task usually executes on the system. (Scheduled),
I / O completion is notified to the system in the form of an interrupt.

An interrupt for an input / output request is generated as a result of a task making an input / output request. (1) If input is completed, input data is stored in the area of the task that issued the request, and (2) If the output is completed, data transfer processing (interrupt processing) such as storing the result in the area of the task that issued the request must be performed.

However, when an interrupt occurs,
Since a task different from the task that issued the input / output request is operating, the task execution environment is different from that at the time of the input / output request.

[0005] As a process when such an input / output interrupt occurs, an APC (Asynchronous Procedure Cal.) In a Windows NT device driver, which is an OS of Microsoft Corporation, is used.
As in l), the task that normally issues the I / O request is again scheduled by the operating system, and the execution of the data transfer process is delayed until the task returns to the same task execution environment as when the I / O request was issued.

[0006]

In the input / output interrupt processing using the APC, the input / output data is stored in the area of the task which has requested the input / output data since the task is in the execution environment of another task from the completion of the input / output to the rescheduling of the task. Cannot be stored directly. During this time, a buffer area for temporarily storing input / output data is required. That is, in addition to the area provided by the task for storing the input / output data, an area for the system to temporarily store the data (from the completion of the input / output to the rescheduling of the task requesting the input / output) is required. . Therefore, when a large-capacity file or the like is input by the APC, utilization of the memory becomes extremely inefficient.

An object of the present invention is to provide a method capable of overcoming the problems of the prior art, easily executing an interrupt process at the time of occurrence of an input / output interrupt, and a multitask execution system capable of effectively utilizing a memory. It is in.

[0008]

In order to achieve the above object, in an input / output interrupt method when a plurality of tasks operate with respective logical spaces, an input / output request issued by one of the tasks is provided. When an interrupt occurs, the task execution environment is switched from the task that is operating only the logical space to that of the task that is the input / output request source.

Here, the task execution environment is a general term for (a) a logical space of a task, (b) a register value (a program counter, a general-purpose register, etc.), and (c) a file. Each task has its own task environment. In a multitask execution system, a plurality of tasks are operated in parallel by sequentially switching the task execution environment.

[0010] In the multitask execution system of the present invention,
When an input / output interrupt occurs, there is provided a logical space switching means for switching only the logical space in the task execution environment to the logical space of the task which issued the input / output request. The logical space switching means is usually provided as a part of the operating system of the multitask execution system.

With the logical space switching means, the interrupt processing of the multitask execution system of the present invention executes the following series of operations as processing when an input / output interrupt occurs.

(1) When an input / output interrupt occurs, the value of a register required for interrupt processing is saved. That is, among the registers used for the processing of the running task, the conflicting register values are saved.

(2) Switching to the logical space of the task that issued the I / O request by the logical space switching means. Switching of the logical space is achieved by invalidating a TLB (Translation Look-aside Buffer) or cache storage as needed after switching the page table. Depending on the type of hardware, this invalidation processing may not be necessary.

(3) Execute interrupt processing. That is,
Store the input / output data in the task area of the input / output request issuer.

(4) Switching to the logical space immediately before switching in the process of (2) is performed again.

(5) The register value saved in (1) is restored.

By performing these series of processes, the input / output data can be stored in the area of the task that issued the request when the input / output interrupt occurs. This eliminates the need for the system to temporarily store data,
Efficient use of memory can be performed. Also, since only the logical space is switched instead of switching all task execution environments, the time required for interrupt processing can be shortened.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an embodiment of the multitask execution system of the present invention. In this system, a plurality of tasks operate on a single computer with independent logical spaces. In the figure, reference numeral 100 denotes a computer system, which includes a central processing unit (CPU) 110, a main storage device 111, and an input / output control device (I / O) 112 as internal devices, which are connected by a CPU bus 120. The input / output control device 112 includes a disk device 113 and a terminal 114.
Is connected. The TLB 115 and the cache memory 116 exist inside the CPU 110.

An operating system (OS) 130 and tasks 131 to 134 exist on the main storage device 111 and are sequentially executed by the CPU 110. OS13
0 manages the execution states of the tasks 131 to 134 and constitutes a multitask execution environment in which a plurality of tasks operate in parallel. In this embodiment, the four tasks 131
Although the presence of .about.134 is shown, a system configuration in which more or less tasks operate is also possible.

FIG. 2 is a conceptual diagram illustrating the configuration of a logical space. As shown in the figure, the logical space includes an OS space and a task logical space, and the latter is mapped to a physical space for each task. All information such as page tables is O
It is arranged in the S space, and by switching this, the task logical space can be switched.

The logical space switching routine 135 is executed by the OS
130 are provided as one routine. Although this routine 135 cannot be directly executed by a task or a user, it can be executed from an input / output interrupt processing routine incorporated and operated in the OS, and executes a logical space switching process. Switching of the logical space is performed by switching a page table or the like which is data inside the OS.

FIG. 3 shows a data structure inside the OS used for switching the logical space. In the OS, the page table entry address 140 and the page table 1
41 to 144, an executing task number 150, and task control blocks 151 to 154 exist to manage the execution status of each task.

The page tables 141 to 144 indicate the correspondence between the logical space and the physical space of the tasks 131 to 134, respectively. In the present embodiment, a page table is provided for each task, but one page table can be configured by the system. A part of the correspondence between the logical space and the physical space of the page table is transcribed in the TLB 115, and enables high-speed address translation by hardware. The page table entry address 140 indicates the head address of the page table corresponding to the currently used logical space. For example, if the task 133 is being executed, the page table entry address 140 indicates the head address of the page table 143.

The task control blocks 151 to 154 are data for managing the execution status of the tasks 131 to 134, respectively, and include register values, states (whether the task is in an execution state or a waiting state), and input / output during execution. The type of processing, the file being used, the position of the page table, and the like are saved, and are used when scheduling a task.

The running task number 150 is a value indicating the number (ID) of the task currently being executed in the system. Depending on the type of CPU 110, an area for storing the task number being executed may be provided by hardware.

The TLB 115 has tasks 131 to 134
A part of the page table indicating the correspondence between the logical space and the physical space is stored. The contents of TLB115 are
Depending on the type of CPU 110, the logical space is 32
When referring to a bit address (4 Gbytes at maximum), it is usually divided into a 4 Kbyte or 1 Kbyte space (page) and mapped to a page in the physical space. Therefore, the TLB 115 indicates a correspondence table between pages in the logical space and pages in the physical space represented by 20 bits or 22 bits.

The CPU 110 converts a logical address into a physical address at high speed using the page correspondence table, and refers to the instruction and data of the main storage device 111 using the converted physical address. If the specified logical page number does not exist in the TLB, a correspondence table between the logical space and the physical space is read from the page table and registered in the TLB.

Since a normal TLB has only a correspondence between a logical page number and a physical page number, when scheduling is performed between tasks having different logical spaces, the logical space and the physical space indicated by the TLB are determined. Is invalidated, so all contents of the TLB must be deleted (invalidated). However, depending on the type of CPU, TLB
Some of them can store the correspondence between the logical page number, the task number being executed, and the physical page number, and have a configuration suitable for a multitask execution system.

FIG. 4 shows the internal structure of the TLB which does not need to be invalidated when switching between logical spaces. The TLB 115 is divided into a plurality of entries, and each entry has a logical page number 16
0 indicates the correspondence between the task number 161 and the physical page number 162. In the case of a CPU using such a TLB, there is no need to delete the contents of the TLB even when the inter-task scheduling is performed.

The cache memory 116 stores the main storage device 11
This is a high-speed buffer that temporarily stores the data read from No. 1. Depending on the type of CPU, the cache memory 116 also has (1) a physical cache that stores data using a physical address as an index, (2) a logical cache that stores data using a logical address as an index, and (3) a pair of a logical address and a task number as an index. Either logical cache configuration is adopted. When the logical cache of (2) is used, all data on the cache storage must be deleted at the time of inter-task scheduling.

FIG. 5 shows a flowchart of the input / output interrupt processing. In this embodiment, the occurrence of an input / output interrupt
Description will be made assuming that 130 performs all interrupt processing.
First, when an input / output interrupt occurs, the value of a register used during interrupt processing is saved so that the system can return to the state before the interrupt (s171).

Some types of CPU 110 have two general-purpose registers (bank 0 and bank 1), and the bank is switched by hardware simultaneously with the occurrence of an interrupt. When such a processor is used, it is not necessary to save the register value. Note that the subsequent interrupt processing must be executed in an interrupt disabled state (a state in which another interrupt cannot be accepted), but is omitted from the drawing because a normal processor shifts to the interrupt disabled state simultaneously with the occurrence of an interrupt. .

Steps s172 to s175 indicate a logical space switching process. These processes correspond to the logical space switching routine 135, but the actual logical space switching is performed in steps s174 to s175. OS of FIG.
The basic logical space switching process will be described with reference to the data structure.

First, the page table is switched (s174). Here, only the head address of the page table corresponding to the input / output request issuing task is registered in the page table entry address 140. For example, when the task issuing the input / output request is the task 134, the head address of the page table 144 is stored in the page table entry address 140.

Next, the number of the task issuing the input / output request is registered in the task number under execution 150 (s175). This process differs depending on the type of the CPU 110. For example, in a processor SH-3 provided by Hitachi, for example, there is a register for registering a task number currently being executed. On the other hand, the processor MC provided by Motorola
In 68030 and the like, there is no hardware for registering the task number under execution. Therefore, when a processor such as MC68030 is used, the running task number 150
Must be secured as OS internal data, but S
In a processor such as the H-3, a register prepared as it is on hardware can be used as the task number 150 being executed.

Thus, the basic logical space switching processing is completed. However, the data in the logical space of the task that was being executed until immediately before the interruption is stored in the TLB 115, the cache storage 1
16 may remain. In this case, s172
The data must be deleted in advance in steps s173.

First, the contents of the TLB are invalidated in s172. An ordinary processor has a function of invalidating all the contents of the TLB, thereby deleting all the contents of the TLB. However, in a TLB having a task number in an entry (FIG. 4), the same logical page number of a different task can be distinguished, so that there is no need to invalidate the TLB entry.

When a CPU equipped with a logical cache having a logical address as an index is used, the process in s173 is executed under a new logical space, and all data in the cache memory is invalidated. In the case of a write-back cache, it is necessary to rewrite.

Next, an interrupt process is performed in s176. In the input / output interrupt processing, the data read or output result via the input / output control device 112 is stored in an area provided by the task which issued the input / output request. In the above switching process, the task of the I / O request issuing task has been switched to the logical space. Therefore, in this interrupt processing, data can be directly stored in the area provided by the I / O request issuing task. .

Therefore, there is no need to temporarily store input / output data in a buffer or the like of the OS, and the memory can be used efficiently. In addition, since it is not necessary to switch all of the task execution environments, especially in the case of a CPU using a TLB capable of storing a task number and a physical cache (or a logical cache having a logical address and a task number as an index), a page table entry is used. The input / output data can be stored in the area of the request source task only by the overhead of rewriting the address 140 and the task number being executed.

Next, in s177 to s180, the logical space is switched again to the logical space before the occurrence of the interrupt. These processes are:
172 to s175. Finally, the register saved in step s181 is restored, and the processing executed before the interrupt is generated is continued. In addition, C having two registers
In the PU, since bank switching is performed at the same time as the end of the interrupt, there is no need to perform register recovery.

FIG. 7 is a time chart showing the system operation of the input / output interrupt processing. FIG. 1A shows a conventional example, and FIG.
However, in the processing of the present embodiment, the operations from the time point are the same.

When one task issues an input / output request in the multitask execution system, the task enters a waiting state without continuing the processing until the input / output processing is completed. At this time, in order to use the CPU efficiently,
A task in another executable state executes a process (another task is scheduled). Such task states include a run (execution) state (a state in which the task is being executed by the CPU), a ready (executable) state (a state in which the task can be processed but another task occupies the CPU), There are three types of wait (waiting) state (waiting for completion of input / output).

In the example of FIG. 7, there are two tasks. As an initial state, task 1 (Task 1) is in an execution state, and task 2 (T
ask2) is in an executable state. In this situation, it is assumed that task 1 issues an input / output processing request (at). The OS that has received the request immediately shifts the task 1 to the waiting state and issues an I / O request to the input / output control device (I / O) (at the time).

Next, the OS schedules the executable task 2 to use the CPU while the task 1 is in the waiting state. Therefore, the execution environment (logical space, register value, file, etc.) of task 1 is switched to the execution environment of task 2 (-), and task 2 transitions to the execution state.

During execution of task 2, the input / output control unit
It is assumed that an I / O completion interrupt has occurred (at). At this point, since the task 2 is in the execution environment, the logical space of the task 1 cannot be referred to. For this reason, conventionally, the result of the input / output processing is copied to a buffer in the OS (from (a)). Here, the OS makes the task 1 executable, and at the same time, continues the processing of the task 2.

When the processing of the task 2 is completed (at the time), the OS immediately switches to the execution environment of the task 1 (from (a)), and then, the result of the input / output processing copied to the buffer is transferred to the task. Then, the task 1 is transferred to the logical space 1 (from (a)), and then the task 1 transitions to the execution state.

As described above, conventionally, a buffer for temporarily storing an input / output processing result at the time of an I / O completion interrupt is required.
Further, when the task 1 is re-executed, the transfer from the buffer is required, so that the task 1 cannot be executed immediately.

On the other hand, in this embodiment, when an I / O completion interrupt occurs (at the time), the OS switches only the logical space to that of the task 1 (from (b)). This switching process can be performed at a very high speed because switching to a task execution environment other than the logical space, such as a register value and a file, is not performed. After the switching, the OS directly writes the result of the input / output processing into the logical space of the task 1 (from (b)). Next, only the logical space is switched to that of the task 2 again (from (b)), and the processing of the task 2 is restarted.

When the task 2 ends at the point of (b), the result of the input / output processing has already been stored in the logical space of the task 1, so the OS switches to the execution environment of the task 1 (from (b) to (b)). ) Alone executes task 1.

According to the present embodiment, since the result is written to the logical space of task 1 at the time of completion of I / O, a buffer is not required, and task 1 is scheduled immediately after completion of task 2.

[0052]

According to the multitask execution system of the present invention, when an input / output interrupt occurs, the input / output data can be directly referred to in the area of the task that issued the input / output request. Thus, there is no need to provide a temporary input / output data area until the data is stored, and efficient memory management can be performed.

According to the interrupt processing method of the present invention,
Since it is not necessary to transfer input / output data from the OS to the input / output request source task and only the logical space needs to be switched at the time of input / output interrupt and return, the overhead can be reduced and the processing speed can be increased.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing a configuration of a logical space.

FIG. 3 is a conceptual diagram showing a data structure inside an OS.

FIG. 4 is a conceptual diagram showing a configuration of a TLB in which a task number can be registered.

FIG. 5 is a flowchart of an input / output interrupt process according to an embodiment of the present invention.

FIG. 6 is a conceptual diagram showing a data structure inside an OS for switching a logical space.

FIG. 7 is a time chart showing a conventional example of a system operation of input / output interrupt processing and a present example.

DESCRIPTION OF SYMBOLS 100: Computer, 110: Central processing unit, 111: Main storage device, 112: Input / output control device, 113: Disk device, 114: Terminal, 115: TLB, 116: Cache storage, 120: CPU bus , 130 ... OS, 131-
134: task, 135: logical space switching routine,
140 ... Page table entry address, 141-1
44: Page table, 150: Running task number, 1
51 to 154: task control block, 160: logical page number, 161: task number, 162: physical page number.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Shigenori Kaneko 5-2-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Omika Plant of Hitachi, Ltd.

Claims (5)

[Claims] 1. An input / output interrupt method when a plurality of tasks operate with respective logical spaces, wherein when an interrupt corresponding to an input / output request issued by one of the tasks occurs, a task execution environment An interrupt processing method characterized in that only the logical space is switched from the running task to that of the input / output request source task. 2. An input / output interrupt method when a plurality of tasks operate with respective logical spaces, wherein an input / output completion interrupt corresponding to an input / output request issued by one of the tasks is interrupted by another task. If it occurs during execution, save the register values required for the interrupt processing, switch to the logical space of the task that issued the I / O request,
An interrupt processing method comprising: executing an interrupt processing routine; thereafter, re-switching to a logical space of the interrupted task, and restoring the value of the register. 3. The interrupt processing method according to claim 2, wherein the interrupt processing routine reads / writes input / output data directly from / to an area in a logical space of the task that issued the input / output request. . 4. In a multitask execution system in which a plurality of tasks operate with respective logical spaces, when an I / O completion interrupt corresponding to an I / O request issued by one of the tasks occurs, A multitask execution system comprising means for switching only a logical space between a task and an input / output request source task. 5. In a multitask execution system in which a plurality of tasks operate with respective logical spaces, an operating system (OS) stores an input / output request issuing task and responds to the input / output request. A multitask execution system, in which, when an interrupt occurs, an interrupt process is executed after switching to a logical space of the issuing task.