JPS6232552U - - Google Patents

Info

Publication number
JPS6232552U
JPS6232552U JP12306485U JP12306485U JPS6232552U JP S6232552 U JPS6232552 U JP S6232552U JP 12306485 U JP12306485 U JP 12306485U JP 12306485 U JP12306485 U JP 12306485U JP S6232552 U JPS6232552 U JP S6232552U
Authority
JP
Japan
Prior art keywords
semiconductor device
utility
device characterized
model registration
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12306485U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12306485U priority Critical patent/JPS6232552U/ja
Publication of JPS6232552U publication Critical patent/JPS6232552U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例を示す縦断面図、第
２図は本考案の他の実施例を示す縦断面図、第３
図は半導体装置の従来例を示す縦断面図、第４図
は第３図のＡ―Ａ′線断面図である。 Ｐ……パツケージ、１，１′……下部チツプキ
ヤリア、２，２′……上部チツプキヤリア、１ａ
，２ａ……窪部、３，４……ワイヤボンデイング
パツド、５，５′，６，６′……ＩＣチツプ、７
，８……リードワイヤ。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 複数のＩＣチツプを、同一パツケージの対
    向しあう内壁面に互いに向かい合わせて実装して
    なることを特徴とする半導体装置。 (2) 実用新案登録請求の範囲第１項において、
    前記パツケージは中央内壁部に窪部を有する上下
    一対のチツプキヤリアからなり、該窪部に前記Ｉ
    Ｃチツプを前記各チツプキヤリアの内周縁に設け
    たワイヤボンデイングパツドに接続しつつ実装し
    てなることを特徴とする半導体装置。
JP12306485U 1985-08-09 1985-08-09 Pending JPS6232552U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12306485U JPS6232552U (ja) 1985-08-09 1985-08-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12306485U JPS6232552U (ja) 1985-08-09 1985-08-09

Publications (1)

Publication Number Publication Date
JPS6232552U true JPS6232552U (ja) 1987-02-26

Family

ID=31013825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12306485U Pending JPS6232552U (ja) 1985-08-09 1985-08-09

Country Status (1)

Country Link
JP (1) JPS6232552U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04324670A (ja) * 1991-03-30 1992-11-13 Samsung Electron Co Ltd 半導体パッケージ及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04324670A (ja) * 1991-03-30 1992-11-13 Samsung Electron Co Ltd 半導体パッケージ及びその製造方法

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