JPS62296457A - Cmos-type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To easily enable a CMOS semiconductor integrated circuit to be difficult to cause power supply latch-up by connecting the source of a MOS transistor constituting the internal circuit and the power supply terminal via a polycrystalline silicon resistance layer. CONSTITUTION:In the equivalent circuit diagram of a parasitic bi-polar transistor, a transistor Tr1 is a pnp transistor consisting of a p<+> type diffusion region 4 which is the source of a p-MOS transistor, an n-type silicon substrate 1 and a well region 2, and a transistor Tr2 is an npn transistor consisting of the source 7 of an n-MOS transistor, a p-well region 2 and the n-type silicon substrate 1. Further, a parasitic resistance R1 is the resistance value between the p-well region 2 and an n<+> type diffusion layer 5, and a resistance R3 is the resistance value of a polycrystalline silicon resistance layer 15. When the power supply voltage VDD rises and Tr2 breaks over, a current flows through R1. When the current flowing through R1 becomes large, emitter-base of Tr1 is forwardly biased and Tr1 attempts to turn on, the potential of the emitter lowers due to the resistance R3, preventing Tr1 from turning on. As a result, latch-up is difficult to occur.

Description

[Detailed description of the invention] Detailed description of the invention [Industrial application field] The present invention relates to a CMOS type semiconductor integrated circuit.

[Conventional technology]

Since a CMOS type semiconductor integrated circuit is a combination of a 9MO3) transistor and an nMO3) transistor, a parasitic thyristor is formed, and there is a drawback that so-called latch-up, in which the parasitic thyristor becomes conductive due to external noise, is likely to occur.

FIG. 3 is a sectional view of the main parts of a conventional CMOS type semiconductor integrated circuit.

FIG. 4 is an equivalent circuit diagram for explaining the latch-up of the conventional example shown in FIG.

Resistance R1 is a parasitic resistance of the n-type silicon substrate 1, resistance R2 is a parasitic resistance of the p-well region 2, and Tr is a parasitic resistance of the p-type diffusion region 4.
A parasitic pnp) transistor with T as an emitter, an n-type silicon substrate 1 as a base, and a p-well region 2 as a collector, T, □
is a parasitic npn with the n+ type diffusion region 7 as the emitter, the p well region 2 as the base, and the n type silicon substrate 1 as the collector.
) is a transistor. As is known, Trl and Tr2 constitute a parasitic thyristor and cause latch-up.

[Problem that the invention seeks to solve]

There are three types of latch-up: power supply latch-up, input latch-up, and output latch-up, depending on the noise source that causes the latch-up.
There are different types. 9MO as a measure to strengthen latch-up
3) transistor and nM.

Increasing the distance between the S transistors on the semiconductor substrate is very effective. For this reason, this countermeasure is taken for the input buffer and output buffer, making them resistant to latch-up. However, due to the large number of transistors constituting the internal circuit and the need to reduce cost by reducing the area as much as possible, it is not possible to widen the distance between the pMOS transistors and nMOS transistors mentioned above. It was unrealistic. For this reason, it has been difficult to strengthen the power supply latch-up in conventional CMOS type semiconductor integrated circuits.

An object of the present invention is to provide a CM with improved power supply latch-up resistance.
An object of the present invention is to provide an OS type semiconductor integrated circuit.

[Means for solving problems]

The CMOS type semiconductor integrated circuit of the present invention comprises an internal circuit excluding an input buffer and an output buffer.
The source of at least one of the S transistor and the PMOS transistor is connected to a power supply terminal via a polycrystalline silicon resistance layer.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing the main parts of an embodiment of the present invention.

This embodiment uses nMOS transistors and 9MO3) that constitute the internal circuits excluding the input buffer and output buffer.
Among the transistors, the source of a PMOS transistor is connected to a power supply terminal via a polycrystalline silicon resistance layer 15.

A p++ diffusion region 3 formed in an n-type silicon substrate 1.
9MO3) which has a gate oxide film 13-1 and a gate electrode 12-1, with 4 as a drain region and a source region, respectively.
A transistor is formed. An nM transistor having a gate oxide film 13-2 and a gate electrode 12-2 with n++ diffusion regions 6 and 7 formed in a p-well region 2 formed in an n-type silicon substrate 1 as a drain region 6 and a source region, respectively.
○S transistor is formed. An n++ diffusion region 8 is formed in the n-type silicon substrate 1 and a p++ diffusion region 5 is formed in the p-well region 2 in order to apply a power supply potential to the n-type silicon substrate 1 and the p-well region 2, respectively. n++
An electrode 10 connected to the power supply terminal VDD is formed in the diffusion region 8 . nMO5) Source electrode of transistor and p+
An electrode 9 connected to the ground terminal V55 is formed in the + diffusion region 5. Next, the p++ diffusion region 4, which is the source region of the pMoS transistor, and the electrode, which is the power supply terminal VDD, are formed in the They are connected by a crystal resistance layer 15.

Next, the effect of improving latch-up according to this embodiment will be explained.

FIG. 2 is an equivalent circuit diagram of the parasitic bipolar transistor which is the CMO3 type NO type gate 07 circuit of FIG. Transistor T1□ is the source of pMOS transistor p
++ Diffusion region 4, n-type silicon substrate 1, p-well region 2
pnp) transistor formed by transistor Tr2
are nMOS transistor source 7, p well region 2, n
This is an npn) transistor composed of a type silicon substrate 1.

The parasitic resistance R1 is the resistance value between the p-well region 2 and the n+ type scattering layer 5, and the resistance R3 is the resistance value of the polycrystalline silicon resistance layer 15.

In FIG. 2, the power supply voltage V. When 0 rises and T12 breaks over, current flows through R1. When the current flowing through R1 becomes large and the emitter-base of Trl is forward biased and Trl is turned on, the thyristor composed of Trl and Tr2 becomes conductive and latch-up occurs. However, when Trl tries to turn on, the emitter potential decreases due to resistor R3, preventing Trl from turning on, and as a result, latch-up is less likely to occur.

As a condition to prevent latch-up, R3>RI
...(1) One dimension of the layer resistance of the polycrystalline silicon resistance layer may be designed to a resistance value that satisfies the following.

Note that a polycrystalline silicon resistance layer may be inserted between the source of the nMOS transistor and the ground terminal VB2.

〔Effect of the invention〕

As explained above, by connecting the sources of the MOS transistors constituting the internal circuit and the power supply terminals through a polycrystalline silicon resistance layer, there is an effect that the CMO3 semiconductor integrated circuit can be easily made resistant to power supply latch-up.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of a semiconductor chip showing the main parts of an embodiment of the present invention, Fig. 2 is an equivalent circuit diagram of the parasitic thyristor of the embodiment shown in Fig. 1, and Fig. 3 shows the main parts of a conventional example. FIG. 4 is an equivalent circuit diagram illustrating the conventional parasitic thyristor shown in FIG. 3. 1... N-type silicon substrate, 2... P well region, 3
．． 4.5...p+ type diffusion region, 6,7.8...n+
Mold diffusion region, 9.10.11...electrode, 12-1゜1
2-2... Electrode, 13-1.13-2... Gate oxide film, 14... Insulating film, 15... Polycrystalline silicon resistance layer. Figure 1 Figure 2 Figure 30 Figure 4

Claims (1)

[Claims] Of the nMOS transistors and pMOS transistors that constitute the internal circuit excluding the input buffer and output buffer,
A CMOS type semiconductor integrated circuit characterized in that a source of at least one MOS transistor is connected to a power supply terminal via a polycrystalline silicon resistance layer.