JPS62293757A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the distance between a drain and a diffused layer for the lower electrode of a capacitor practically and reduce leakage current even in a microminiturized structure by providing a recess at the intermediate part of a trench and filling it with oxide. CONSTITUTION:After SiO2 30 and Si3N4 31 are grown on a silicon substrate 29, a part of the SiO2 30 and a part of the Si3N4 are selectively removed to form a vertical opening 32 and an SiO2 film 34 and an Si3N4 film 35 are grown on the side wall and the bottom of the opening 32. Then the parts of the Si3N4 film and the SiO2 film on the substrate 29 surface and on the bottom of the opening 32 are etched away and an oxide layer 36 is formed on the bottom. Then a deep opening 37 and an aperture 38 at a different position are obtained by etching and, after boron ions are implanted into the bottoms of the openings to form p<+>type layers 39, n<+>type layers 40 are formed on the side walls of the openings by doping. Then, after the side walls of the openings are oxidized to form thin oxide films 41 which constitute a capacitor, the openings are filled with polycrystalline silicon 42 and n<+>layers 43 and 44 are formed by diffusion and a gate oxide film 45 and a gate metal 46 are formed.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention Field of Industrial Application The present invention relates to an ultra-high density semiconductor storage device, DRAM (Dynamic Random Access Memory).

The present invention relates to semiconductor memory devices such as SRAM (Static Random Access Q Memory).

2. Description of the Related Art The prior art related to the present invention will be explained with reference to the drawings. Figure 4 shows a one-transistor type MOS dynamic RAM.
(abbreviated as DRAM) is shown. This DRA
The M cell has a structure in which the capacitance surrounds the transistor, and is a cell designed to have the maximum capacitance per unit area.

The cell of the conventional structure will be explained according to the drawings. Fourth
1 in the figure is 1) (100') silicon substrate, the substrate surface is etched from the top, and trench portions 100, 2 are etched.
00f3: Formed. 2.3 at the bottom of the trench has p
There is a type diffusion part, which is provided to suppress n-type inversion at the silicon-oxide film interface, which causes leakage between cells. Reference numeral 4 designates an n-type diffusion layer which becomes the lower electrode of the capacitor section, and this diffusion layer 4 is electrically connected to the source section 16 of the transistor. 6 is an n-type diffusion layer similar to 4, which serves as a lower capacitor and is connected to the diffusion layer 4 so as to surround the MOS transistor. That is, 4 and 5 represent cross sections of opposite sides surrounding a square (MOS) run sister.

6 and 7.8 are thin oxide films forming capacitors, and 1
The thickness is around 0.25 oz. 9.1° is, for example, a diffused polycrystalline silicon or gold layer, and the diffusion electrode 4.5
and a thin oxide film 6. They are fighting against samurai across the border. 11.1
2 is a metal electrode connected to 9.10, which is connected to an external (not shown) fixed potential.

13idMO8) For example, at the gate part of the run sister, W
(tungsten), titanium (titanium), or its silicide/polycide.

14 is a gate oxide film. Reference numeral 16 denotes an n-type diffusion layer forming a source, which is connected to one electrode 4 forming the capacitor. 16 is a drain portion where n-type diffusion is performed. 17 is an insulating film used to insulate the metal electrode 12 and the metal wiring 18 electrically connected to the drain part 16, and 5i02 formed by CVD method etc.
(silicon dioxide) is used.

Reference numeral 19 denotes an insulating film, which includes a metal wiring 2o that becomes a bit line in the memory and a metal electrode 11 installed on the surface of the substrate.
It is insulated from metal parts such as 13. As is clear from the above configuration, the memory cell in Figure 1 has a structure in which the capacitance formed on the side of the trench surrounds the transistor, and one electrode is connected to the diffusion layer formed on the side of the trench. This is the structure connected to the source. In this structure, the capacitive part surrounds the transistor, so the capacitance per unit area is large.
It has an excellent structure for future high-density memory.

Problems that the invention seeks to solve However, this structure also has drawbacks. This concerns the p-type foil plate portions 21 and 22 between the drain portion 16 diffused with n-type impurities and the diffusion layer 5 which is also diffused with n-type impurities and serves as one electrode of the capacitor. This 21
and 22 parts usually cannot be made wide or long enough. Basically, memory is required to have a large capacity in a small area, and in order to achieve this, it is necessary to make the trench deep and increase the distance between the sides of the trench. If the depth of the trench is too deep, defects may easily occur during etching, and it may be difficult to form a diffusion layer or oxide film layer uniformly within the trench. cannot be made extremely deep. Therefore, it is required to shorten the distance between the drain 16 and the diffusion layer 5, and it is desirable that the distance therebetween is also about 0.3 to 0.6 μm.

However, if this distance is shortened, an n-type inversion layer may be formed on the oxide film surface 21, 22 between the drain 16 and the diffusion layer 5, or a depletion layer between the n-type diffusion layers may cause punch-through. This is because this part is on the side of the trench, so it is not cleaned thoroughly, and heavy metals such as C (carbon) are not fully removed and tend to remain, which tends to cause crystal defects at the silicon-oxide film interface. n reversal is likely to occur.

The present invention aims to solve the conventional problems and take advantage of the characteristics of high-density memory cells to solve their electrical defects.

Means for Solving the Problems The present invention provides a memory cell integrated into a semiconductor, in which, for example, a capacitive part that is an element of the memory cell is formed surrounding a transistor to form a parenthetical capacitive part. This method is characterized in that a recess is provided in the middle of the trench, the width of which is wider than the width of the upper and lower grooves of the trench, and the recess is filled with an insulating film.

According to the present invention, since there is a recess in the middle part of the trench groove and the oxide film is filled in the recess, the distance between the drain and the diffusion layer for the lower electrode of the capacitor becomes substantially longer, resulting in miniaturization. It also becomes possible to make leakage current extremely small.

Embodiment FIG. 1 shows a manufacturing process of a memory cell according to the present invention. 29 in FIG. 1(a) indicates a p-type (100) silicon substrate. 30.31 is 5102 (
A silicon oxide film) and a 5i3N4 (silicon nitride film) film are shown, which were grown on the silicon substrate 29 by the CVN (chemical vapor deposition) method, and then a portion was selectively removed.

32, the silicon substrate is exposed to CF4 in a plasma gas atmosphere.
A gas such as carbon fluoride (Cc44C carbon tetrachloride) is introduced and the silicon substrate 2 is
9 is partially vertically opened.

In FIG. 1(b), the silicon substrate is oxidized to form an oxide film 34, a silicon nitride film 35 is grown on it, and a silicon oxide film and a silicon nitride film are also grown on the side and bottom surfaces of the opening 32. In addition, a thick nitride film grows on the surface of the substrate. After that, a dry etching method with high verticality, such as RoI, X, (React etching no.
By the ion etohing) method, silicon 'i
When etching is performed by 0.3 to 0.8 μm, the insulator on the side surfaces of the opening 32 is not removed, but the Si3N4 film and the 5in2 film on the substrate surface and the bottom of the opening 32 are removed. As mentioned before, the Si, N4 film 36 on the substrate surface is grown thicker than the bottom of the opening, so the Si, N4 film 36 on the bottom of the opening is grown thicker than the bottom of the opening.
The film remains even after the four films are removed. (in Fig. 1), 34 and 35 are the remaining 5i02 films, Si
3H4 membranes are shown respectively.

In FIG. 1C, the silicon substrate is oxidized, in which case only the bottom of the opening where the silicon substrate not covered with the nitride film is exposed is oxidized to form an oxide film layer 36.

In FIG. 1(d), the oxide film layer 3e is
1. E. Dry etching method is used to open the hole, and then by changing the gas, the silicon layer at the bottom of the opening is etched. etching to obtain a deep opening 37t.

When this opening is opened, other locations are also opened to obtain a new opening 38. The opening 38 has a square shape when viewed from above, and the openings 37 are connected.

Thereafter, by implanting boron into the bottom of the silicon using a highly vertical ion implantation method, a p+ layer 39 is obtained at the bottom of the opening. After that, doping with arsenic or the like (for example, using a SiO□ film doped with impurities) is performed, and an n+ layer 4
Make 0.

In FIG. 1(6), the side surface of the opening is oxidized to grow a thin oxide film 41 that becomes a capacitor. Thereafter, the opening is filled with polycrystalline silicon 42 [FIG. 1(f)].

In FIG. 1Cg), the source of the MoS transistor.

Diffusion of n layer 43, 44 which will become the drain and gate oxide film 46. A gate metal 46 is formed, and 43 to 46 constitute a MOS (MOS) run sister.

In FIG. 1Cg), the source 43 of the MOS transistor is physically and electrically connected to the diffusion layer 40 diffused on the side surface of the opening. As the figure clearly shows,
A thick oxide film layer 36 is formed below the drain section 440 of the MOS transistor, and the oxide film 36 electrically insulates the n4 layer 40 diffused on the side surface of the opening. The thickness of the oxide film 36 is 0.2
Since it is set to about μm, the actual distance is 0.2 μm.
Even if the distance is only 0.5, the lateral spread of 36 is 0.5
Since the size is more than μm, each diffusion layer of 40 and 44 is approximately 1
They are separated by μm, and bunch-through caused by the spread of each depletion layer can be prevented.

FIG. 3 shows a top view of the opening,
41 is a thin oxidized wave film, 42 is a polycrystalline silicon layer, and the capacitor part has a square structure, surrounding the transistor at the center.

Therefore, the capacitance per potential area is very large.

FIG. 4 is a circuit diagram of a memory cell corresponding to the above structure, where 60 is a memory capacitor section, and in FIG. 2(g), polycrystalline silicon 42 is used as one electrode and the other electrode is
+ Consists of a diffusion layer 4o and an oxide film 41 forming a capacitance, and 61 is 43.44.45.4 in FIG. 2(g).
She is a rough sister of 6 years old @ M OS.

Effects of the Invention The present invention has been described in the section regarding the conventional problems, and therefore, the present invention has a diffusion layer serving as one electrode of a memory capacitor portion, and a MOS transistor (MOS transistor) serving as a switching element for charge transfer. Since the drain regions of C and D are very close to each other, the depletion layers of C come into contact with each other, and in order to eliminate the defect that tends to cause the so-called punch-through effect, an oxide film is formed on that part. The aim is to completely isolate the active region of the device. In addition, if this insulating film itself induces strain and tends to generate fc, t, pinholes, etc., it will not be effective, so thermal oxidation, which has excellent compatibility with the silicon substrate, is used. The generated silicon oxide film is used. For this reason, as described in the embodiment, the distance between the drain and the diffusion layer of the capacitor lower electrode, which is originally only about 0.2 μm apart, has become almost 1.
The film spreads to 1.0 μm and has the great effect of not causing punch-through or the like.

As mentioned in the examples, the manufacturing method was industrially relatively easy and highly effective by devising a highly inventive manufacturing method and structure by using well-known materials and equipment. That will happen.

[Brief explanation of drawings]

FIG. 1 is a process cross-sectional view showing the manufacturing process and new memory cell structure of a new memory cell having a capacitance surrounding a transistor according to an embodiment of the present invention and having no leakage between the drain and the capacitor part. , FIG. 2 is a sectional view of a conventional memory cell, FIG. 3 is a plan view of a memory capacitor section, and FIG. 4 is an equivalent circuit diagram of the memory cell. 29...Group/Silicon substrate, 36°°°°°°Thick silicone acid (11,4
1°°...thin silicon oxide film, 4o°゛°゛...
A diffusion layer that serves as one electrode of a capacitor connected to the source of a transistor, 43.44...MOS) Source and drain of a run sister. Name of agent: Patent attorney Toshio Nakao (1 person)
] Figure 1 Section 4

Claims (1)

[Claims] It has a trench structure forming a part of a semiconductor memory element, and the width of the middle trench groove is wider than the width of the upper and lower grooves of the trench groove, and the wide opening A semiconductor integrated circuit device characterized in that a recess in a recessed portion is filled with an insulating film.