JPH08204146A - Semiconductor device - Google Patents

Abstract

PURPOSE: To provide the novel structure of a trench type DRAM having excellent electrical characteristics of storage capacitor (condenser part) in less defective development in the trench part. CONSTITUTION: An SOI substrate holding an oxide film 22 between an n<+> substrate 21 and a p substrate 23 is used as a base substance to form a selective transistor in the p substrate 23, next a plate electrode 242, a condenser oxide film 243 and a storage electrode 244 are formed in a trench from the p substrate 23 to the n<+> substrate 21 to be a storage capacitor so that the storage electrode 244 may be electrically connected to the source region 231 of the selective transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a novel structure of a MOS dynamic random access memory (hereinafter referred to as "DRAM") used as a main storage device of a large-scale computer,
In particular, it relates to a DRAM having a trench capacitor cell structure.

[0002]

2. Description of the Related Art In MOS / DRAM, one memory cell is composed of one selection transistor (MOS transistor) and one storage capacitor (capacitor), and the device structure is relatively simple and high integration is possible. Therefore, it is the main product of semiconductor memory devices.

The development of MOS / DRAM has continued to be four times as highly integrated in three years, and it is considered that a similar tendency will continue in the future, supported by the ever-increasing needs. DRAM is becoming finer with each generation, so-called "process
It has played a role as a “driver.” There are various technological innovations behind the background of such high integration. Regarding the cell structure, in the generation from 1M DRAM to 4M DRAM, the storage capacitor portion (capacitor portion) has been three-dimensionalized from a planar type to a stack type or a trench type.

That is, 1/2 V _cc up to 1 MDRAM
Due to the adoption of the cell plate method, even a thin oxide film of about 10 nm can be used as a capacitor insulating film with sufficient reliability, and a planar structure can be maintained.
However, in 4MDRAM, the capacitor area cannot be ensured with a planar structure due to the reduction in cell size, and there are two major types: a trench type in which a capacitor is buried in a hole and a two-layer structure capacitor is stacked on top of a transistor. That is why we have no choice but to adopt the three-dimensional capacitor structure. However, in the stack type, (i) the diffusion layer area of the storage electrode is not as large as that of the trench type, and therefore the collection efficiency of the electrons generated by α rays is small and is resistant to soft error.

(Ii) It does not require a special process such as digging a hole or doping on the side surface of the hole, and the deposition and etching techniques of the polysilicon film which have been conventionally used can be used.
A relatively easy process.

Although there are advantages such as (i) no matter how the storage electrode is protruded above the transistor, only a part of the cell area can be used as a capacitor because of the bit line contact portion. Inability to secure storage capacity C _s .

(Ii) Since the stack capacitor is stacked on the transistor as compared with the trench type, the step difference of the bit line and Al wiring after that becomes large, and it becomes difficult to form fine wiring and deep contacts.

It has drawbacks such as

On the other hand, the trench type is advantageous in that it has a small step, but has a problem that it is weak against soft errors. In order to solve this, as shown in FIG. 15, a cell plate type system has been proposed in which a capacitor is formed only on the side surface of the trench and a substrate electrode is formed on the bottom of the trench. With this method, since the storage electrodes are separated by the substrate, there is no problem of punch-through between trenches, and high integration is possible.

[0010]

However, in order to form this cell plate structure, the substrate is selectively etched to form a trench (groove), and then the bottom of the trench is ion-implanted or the like, for example, phosphorus is used. (P) is injected at a high concentration and then heat-treated to be thermally diffused to form. Since this portion is used as an electrode, it is necessary to reduce the resistance and, of course, high concentration ion implantation is required. As a result, not only the process becomes complicated, but also the damage of the ion implantation is added to the bottom of the trench, primary crystal defects are generated, or the crystal defects are easily generated, and the subsequent heat treatment process such as oxidation is performed. , Crystal defects such as dislocations and other 2
Secondary crystal defects occur, which is a factor of lowering the yield.

In view of the above problems, it is an object of the present invention to provide a novel trench type DRAM structure which can be manufactured with a high yield by a simple process.

Another object of the present invention is a trench type DR having a cell plate in which crystal defects do not occur at the bottom of a trench or the like.
It is to provide a novel structure of AM.

Still another object of the present invention is to provide a novel DRAM structure capable of increasing the storage capacity without making the trench deep.

[0014]

In order to solve the above-mentioned problems, according to the present invention, as shown in FIGS. 1 to 5, a first conductive type first semiconductor substrate 21 having a high impurity density and a second conductive type are provided. A DRAM in which one cell having a dielectric isolation substrate sandwiching a dielectric film 22 between the second semiconductor substrate 23 and the second semiconductor substrate 23 is formed of one transistor and one storage capacitor section. Transistors are formed on the surface of the second semiconductor substrate 23, and a storage capacitor portion connected to the source region of each selection transistor is formed from the surface of the second semiconductor substrate 23 to the dielectric film 2.
The first polysilicon film 242 and the capacitor oxide film 24 inside the groove that penetrates the first semiconductor substrate 21
3 and the second polysilicon film 241 are provided in a small number. The first polysilicon film is a plate electrode and becomes a common electrode,
The second polysilicon film serves as a storage electrode and is connected to the source region of the selection transistor. Both the first and second polysilicon films are so-called doped polysilicon (DOPOS) doped with impurities.

1 and 2, the trench inner wall oxide film 2 is formed between the first polysilicon 242 and the trench inner wall.
41 is formed and illustrated, the trench inner wall oxide film 241 can be omitted as shown in FIGS.

Preferably, the specific resistance of the first semiconductor substrate 21 is 0.02 Ωcm or less, and more preferably 0.006 Ωc to which phosphorus, arsenic or boron is added.
It is a silicon substrate of m or less.

More preferably, as shown in FIG. 6, the width of the groove is larger in the first semiconductor substrate 21 than in the dielectric layer 22 and the second semiconductor substrate 23. Is. The structure of FIG. 6 is shown in FIGS.
It can be easily manufactured by the method shown in FIG.

[0018]

According to the features of the present invention, the first semiconductor substrate is
Since it plays the role of a so-called cell plate, it is not necessary to form the buried cell plate electrode 13 as shown in FIG. 15 by ion implantation, and the process-induced defect due to damage of ion implantation is also eliminated. Therefore, the breakdown voltage of the oxide film of the storage capacitor (capacitor) formed in the trench is improved, and the leak current in the capacitor portion is reduced.

Further, by forming the pot shape as shown in FIG. 6, the surface area is increased and the capacitance of the capacitor can be increased.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As a first embodiment of the present invention, FIG. 1 shows a DRAM having a cell plate type trench structure. In FIG. 1, the substrate is a so-called SDB (Silicon Direct Bondin).
g) SOI (Sil
An icon-on-insulator (dielectric isolation substrate) substrate was used, and the support substrate 21 was a CZ.n-type substrate (ρ = 0.006 Ωcm) doped with 10 ¹⁹ atoms / cm ³ of phosphorus (P). The substrate 23 on the active layer side is made of boron-doped CZp.
The mold substrate 23 (ρ = 4 Ωcm). Substrate 2 on the active layer side
A thermal oxide film 22 having a thickness of 500 nm is formed on No. 3 and is adhered (so-called bonded) to the support substrate 21 which is mirror-polished 1
It heat-processed at 100 degreeC, the thickness of an active layer was processed into 0.4 micrometer, and it was set as the SDB-SOI substrate. SIMOX (Separation
The SOI substrate may be formed by the IMplanted OXygen) method. In this case, 2 × 10 ¹⁸ cm from the surface of the n ⁺ substrate
^It is only necessary to implant 0 ⁺ ions at 400 keV with a dose amount of ^-2 , perform heat treatment at 1325 ° C. for about 5 hours, and then form a p layer on the Si layer on the oxide film.

Next, using this SOI substrate, an element isolation process, a storage capacitor (trench capacitor) formation process, a selection transistor formation process, a metal wiring formation process and the like are performed to form a cell plate type DRAM. .

A typical trench depth in FIG. 1 is 7
μm, the diameter of the trench is 1 μm, but this is a DRAM
It may be arbitrarily selected according to the required trench capacitor capacity according to the specifications of. 100n thick inside the trench
First polysilicon film 242 in trench to be a sheath type plate electrode of m, capacitor oxide film 24 having a thickness of 20 nm
3. The storage capacitor of the DRAM is formed by the second polysilicon 244 in the trench which serves as a storage electrode having a thickness of 400 nm. The second polysilicon 244 in the trench is a switch M
It is electrically connected to the n ⁺ source region 231 of the OS transistor (selection transistor). In the select transistor, the n ⁺ region 231 formed on the surface of the p-type substrate 23 is the source region 231, and the n ⁺ region 232 is the drain region 23.
2, p-type substrate 2 between n ⁺ region 231 and n ⁺ region 232.
3 is formed from the gate oxide film 29 formed on the surface of the gate electrode 3 and the polysilicon gate electrode 25 on the gate oxide film 29. The polysilicon gate electrode 25 also serves as the word line 25. N ⁺ region 232 and bit line 233 are electrically connected. The first and second polysilicon films and the polysilicon gate electrode are so-called doped polysilicon (DOPOS) doped with impurities.

FIG. 2 shows a second embodiment of the present invention, which is a high-speed switching DRAM in which the source region 231 and the drain region 232 have a thickness of 0.25 μm, which is thinner than 0.4 μm of the p-type substrate 23. When the bit line 233 is made of a metal such as Al, a solid phase reaction at the metal-semiconductor interface, such as a spike of Al into the drain region 232, may be a problem, but basically such a process problem occurs. If not, the drain region 232 may be shallower.

In FIGS. 1 and 2, a sheath-shaped trench inner wall oxide film 241 is formed between the trench inner wall and the trench inner first polysilicon 242. However, this trench inner wall oxide film is formed due to the manufacturing process. It is formed and is not always necessary. FIG. 3 shows a third embodiment of the present invention in which the trench inner wall oxide film 241 is omitted, and the rest is the same as the first embodiment.

In order to operate at a higher speed, the storage electrode 244 is formed as a multi-layered film than that of the DOPOS alone, and has a polycide structure containing a silicide of a refractory metal such as WSi ₂ , MoSi ₂ , TiSi _{2 in the} central portion. It is preferable.

FIG. 4 shows a DRA according to the fourth embodiment of the present invention.
In the cross-sectional structure of M, the isolation region between the unit cells of the memory is almost completely filled with the field oxide film 26. In FIG. 4, the p-type substrate 23 between the right and left trenches is completely replaced by the field oxide 26. By doing so, the leak current between the cells is reduced, and the wiring capacity of the word line and the like is also reduced.

FIG. 5 shows a DRA according to the fifth embodiment of the present invention.
In the cross-sectional view of M, the thickness of the oxide film 22 in the SOI structure is increased to 6 μm, and the sidewall of the trench is almost completely formed of the oxide film. The leak current between cells is reduced and the parasitic capacitance of the select transistor is also reduced, which enables high-speed operation. Not only the DRAM but also the semiconductor device using the SOI structure has a common problem of leak current due to the SOI structure. However, in the fifth embodiment, the SDB
The adhesion surface in the method is formed sufficiently far from the switching transistor (selection transistor), and the leak current is extremely small. Similar to the fourth embodiment, the field oxide film 26 may be completely formed in the isolation region also in the fifth embodiment.

FIG. 6 shows a DRA according to a sixth embodiment of the present invention.
In the cross-sectional view of M, the structure is for increasing the storage capacity, and is a cell structure suitable for, for example, 256 MDRAM. D
One of the problems in increasing the degree of integration of the RAM is how to increase the storage capacitance C _s , but according to the sixth embodiment of the present invention, the selection transistor which has not been utilized conventionally is used. The area on the back side becomes available. It is also possible to form a so-called stack type on the back side of the selection transistor. That is, as shown in FIG. 6, the SOI structure is used to form a pot shape in which the groove width of the lower portion of the trench is wider than that of the upper portion. Although the storage capacity C _s is proportional to the surface area, the area increases according to the square law. Therefore, the structure of FIG. 6 causes the storage capacity C _s to increase dramatically. Although not shown, a fin (F
In) structure further increases the capacity. In the conventional trench structure, it was necessary to deepen the trench in order to increase the capacity. However, considering the aspect ratio of the trench shape, the trench depth is limited.
According to this embodiment, it is not necessary to deepen the trench, and the manufacturing is easy.

The structure of the sixth embodiment of the present invention is shown in FIGS.
It can be manufactured by the manufacturing method as shown in.

(1) First, as described above, the SOI structure shown in FIG. 7 is formed by the SDB method, and then the LO structure is formed.
The field oxide film 2 is formed in the vicinity of the isolation region by using the COS method or the like.
6 is formed.

(2) Next, using photolithography,
A photoresist is formed on a portion other than the portion where the trench is to be formed, and CF ₄ , CF ₄ / H ₂ or C ₃ F ₈ is formed as shown in FIG.
Etch the field oxide film by ECR or RIE etching, and use the oxide film as a mask to form the trench 24 by RIE or ECR ion etching with CF ₄ , SF ₆ , CBrF ₃ , SiCl ₄ , or CCl _4. Form. It is also effective to cool the substrate to -110 ° C to -130 ° C during the trench etching.

(3) Next, as shown in FIG. 9, undercut of the n-type support substrate 21 is caused by chemical dry etching or wet etching using the SOI structure oxide film 22 and the field oxide film 26 as a mask. , For example, 1 μm over-etching.

(4) Next, as shown in FIG. 10, a reduced pressure CV
A doped polysilicon (DOPOS) film having a thickness D of 100 nm is formed as a sheath-shaped plate electrode 242, a capacitor oxide film 243 having a thickness of 20 nm is formed by thermal oxidation, and a storage electrode 244 is formed so as to bury a trench (pot). Then, the DOPOS film is formed by low pressure CVD. The capacitor oxide film 243 is also formed by low pressure CVD, and the DOPOS film 242,
Continuous C of capacitor oxide film 243 and DOPOS film 244
It may be VD. As another method, the DOPOS film 24
After CVD of 2, the photoresist may be embedded in the trench (pot), the DOPOS film 242 may be etched back, and then the thermal oxide film 243 may be formed. This DOPOS film 24
The etch back of 2 is D near the entrance of the vase so that it can be contacted with the source region as shown in FIGS.
It is preferable to etch back the OPOS film 242 as well.

(5) Next, as shown in FIG. 11, in order to make contact between the source region of the select transistor and the storage electrode 244, the DOPOS films 242 and 244 and the oxide film 24 are formed.
3, 26 are etched back using photolithography and RIE.

(6) Next, 50 on the etched back surface.
nm of SiO ₂ is CVD, and SiO near the entrance of the pot
_A contact hole is opened in ₂ films and DOPOS2
44 is additionally CVD connected to the DOPOS 244 in the pot,
After that, a pattern as shown in FIG. 12 is formed by using photolithography and RIE.

(7) The subsequent process is a process of forming a select transistor by a normal MOS process. Although not described in detail, for example, a polysilicon gate electrode 25 is formed and a source region 23 is formed by a self-alignment process.
1, a drain region 232 is formed, and an insulating film 16 is formed thereon.
Is deposited, a contact hole for taking out a bit line is opened in the insulating film 16, and the bit line 233 is wired to complete the DRAM shown in FIG.

In the above description, the n ⁺ type support substrate 21 is used.
N-channel MOSFET as the selection transistor
As described above, p ^{+ +} with all conductivity types reversed.
A p-channel MOSFET may be used as the selection transistor by using the mold supporting substrate. Further, the n ⁺ type supporting substrate 2
1 is used to form an n-well inside the p-type substrate 23 to form C
It may be a DRAM having a MOS structure.

[0038]

The manufacturing yield of the DRAM manufactured according to the present invention is shown in FIG. 13 together with the result of the prior art. It can be seen that the present invention has a higher overall yield than the conventional example. This is because in the present invention, the process of forming the cell plate electrode can be omitted, the yield decrease due to process factors can be reduced, and ion implantation is not required at the trench bottom as in the prior art, so the defect density at the trench bottom is extremely low. This is because. FIG. 14 is a cross-sectional view of a trench portion formed in each of the DRAM according to the present invention and the DRAM according to the conventional example, which is selectively etched, and the surface thereof is etched by a scanning electron microscope (SEM) around the trench, particularly around the bottom of the trench. This is the result of observing the pits. In the conventional example, it is necessary to perform high-concentration ion implantation to form the cell plate electrode. As a result, ion implantation damage (damaged portion of crystal) is introduced around the bottom of the trench, and crystal defects such as dislocation are likely to occur. For this reason, stress is applied due to oxidation or the like in the subsequent process, and defects are generated. On the other hand, according to the present invention, since the formation of the cell / plate electrode of the high-concentration layer is not performed by ion implantation, there is no ion implantation damage and the occurrence of crystal defects is small.

Therefore, according to the present invention, the cell plate electrode of the trench capacitor type DRAM of the cell plate electrode system, which is resistant to punch-through, soft error, etc. and can be highly integrated, can be easily formed without causing defects. And can be formed with a high yield.

Further, according to the present invention, the storage capacitance C _s can be increased without increasing the depth of the trench, and the DRAM
The degree of integration can be easily increased. Moreover, since there is no defect in the trench, the productivity is improved.

[Brief description of drawings]

FIG. 1 is a sectional structure of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a sectional structure of a DRAM according to a second embodiment of the present invention.

FIG. 3 is a sectional structure of a DRAM according to a third embodiment of the present invention.

FIG. 4 is a sectional structure of a DRAM according to a fourth embodiment of the present invention.

FIG. 5 is a sectional structure of a DRAM according to a fifth embodiment of the present invention.

FIG. 6 is a sectional structure of a DRAM according to a sixth embodiment of the present invention.

FIG. 7 is a sectional view (No. 1) for explaining the method of manufacturing the DRAM according to the sixth embodiment of the present invention.

FIG. 8 is a sectional view (No. 2) for explaining the method of manufacturing the DRAM according to the sixth embodiment of the present invention.

FIG. 9 is a cross-sectional view (3) for explaining the method of manufacturing the DRAM according to the sixth embodiment of the present invention.

FIG. 10 is a cross-sectional view (4) for explaining the method of manufacturing the DRAM according to the sixth embodiment of the present invention.

FIG. 11 is a cross-sectional view (5) for explaining the method of manufacturing the DRAM according to the sixth embodiment of the present invention.

FIG. 12 is a cross-sectional view (6) for explaining the method of manufacturing the DRAM according to the sixth embodiment of the present invention.

FIG. 13 is a comparison diagram of yields of the present invention and a conventional example.

FIG. 14 is a comparison diagram of defect densities of the present invention and a conventional example.

FIG. 15 is a sectional view of a conventional DRAM.

[Explanation of symbols]

11 p-type substrate 13 embedded cell plate electrode 15, 26 element isolation (field oxide film) 16 insulating film 21 first semiconductor substrate (n ⁺ substrate) 22 dielectric film (SOI oxide film) 23 second semiconductor substrate (p Substrate) 25 Word line 29 Gate oxide film 231 Source region 232 Drain region 233 Bit line 241 Trench inner wall oxide film 242 First polysilicon film (plate electrode) 243 Capacitor oxide film 244 Second polysilicon film (storage electrode)

Claims (3)

[Claims] 1. A DRAM using a dielectric isolation substrate in which a dielectric film is sandwiched between a first semiconductor substrate of a first conductivity type and a high impurity density and a second semiconductor substrate of a second conductivity type. The DRAM is configured by arranging a large number of unit storage elements each including one transistor and one storage capacitor section, and the selection transistor is formed on the surface of the second semiconductor substrate. From the surface of the second semiconductor substrate,
To have at least a portion formed by the first polysilicon film, the capacitor oxide film, and the second polysilicon film inside the groove portion that penetrates the dielectric film and reaches the first semiconductor substrate. A semiconductor device characterized by: 2. The specific resistance of the first semiconductor substrate is 0.0.
The semiconductor device according to claim 1, wherein the semiconductor device has a resistance of 2 Ωcm or less. 3. The width of the groove in the first semiconductor substrate is larger than the width in the dielectric layer and the second semiconductor substrate. Semiconductor device.