JPH0488665A - Semiconductor device provided with charge storage capacitor and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a semiconductor device to be surely provided with a capacitor prescribed in capacity and a space between a charge storage capacitor and another charge storage capacitor or an element or the like to be lessened and to obtain a semiconductor device of high density by a method wherein the lower electrode of a capacitor is formed of a first and a second silicon film. CONSTITUTION:A silicon film (first silicon film) 4 is formed on a silicon oxide film 2 provided to a P-type silicon semiconductor substrate 1 to fill an opening provided to the silicon oxide film 2. Arsenic or phosphorus is introduced into the film 4 as high in concentration as 10<15>-10<18> atoms/cm<2>, and a selection polysilicon film (second silicon film) 5 doped with impurities is deposited on the surface and the side face of the film 4. Arsenic or phosphorus is introduced into the film 5 as high in concentration as 10<18>-10<20> atoms/cm<2>. A capacitor insulating film 6 is formed on the film 2 including the film 5, and a counter electrode 7 doped with impurities is formed on the insulating film 6. As the lower electrode of a capacitor is formed of a two-layered film composed of the films 4 and 5, a capacitor of prescribed capacitance can be ensured, a space between a charge storage capacitor and another charge storage capacitor or an element or the like can be sharply lessened, and the capacitors can be integrated high in density.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device equipped with a stacked charge storage capacitor and a method for manufacturing the same, and particularly to a semiconductor device equipped with a charge storage capacitor suitable for high integration of semiconductor devices. The present invention relates to a semiconductor device and its manufacturing method.

[Background Art] In recent years, rapid progress has been made in increasing the density and integration of silicon semiconductor devices. And currently, 0.8μm
4 megapixels) DRAM (Dyna
mic Random Access Memory)
and 1 Mbit S RAM (Static Ran
V L such as dom AccessMe＋＊ory)
3.Very Large ScaleInteg
rated C1rcuit) has been commercialized.

In addition, 16 Mbit) DRAM with 0.5 μm design rule
and ULSI (Ultr
a Large 5cale Integrated
C1rcuit) is being researched and developed, and these UL
The practical application of SI is being considered.

In such high-density and large-capacity semiconductor devices, it is necessary to miniaturize the elements on a plane and to make effective use of the vertical direction, that is, to make the elements three-dimensional. In this case, it is easier to make passive elements such as resistors and capacitors three-dimensional than active elements, and semiconductor devices formed by making resistors and capacitors three-dimensional are currently being commercialized. has been done.

Incidentally, increasing the density of DRAM requires three-dimensional charge storage capacity, and currently, trench structure type or stack structure type capacitors are being put into practical use in 1 Mb/2 DRAM, 4 Mbit DRAM, etc. . but,
In the case of 16 megabit DRAM with a design rule of 0.5 to 0.6 μm and 64 megabit DRAM with even stricter design rules, increasing the dielectric constant of the capacitor insulating film, improving the capacitor electrode structure, or increasing the number of layers. It is said that this will become necessary. Fin structure ([EDM Tech, Dig, p. 592, 19
published in 1988) and cylinder structure (VLSI Symp.
, p. 69, published in 1989) is proposed.

However, when putting into practical use a semiconductor device having a capacitance with a fin structure or a cylinder structure, the capacitor insulating film and the capacitor counter electrode are placed on the surface of the capacitor lower electrode because the structure of the capacitor lower electrode is complicated. There are problems in that it is extremely difficult to uniformly form the capacitor lower electrode pattern, and the aspect ratio of the capacitor lower electrode pattern becomes large, making it difficult to planarize the interlayer insulating film required for wiring. Therefore, these structures have not been put into practical use.

FIG. 7 shows one of the conventional semiconductor devices equipped with a charge storage capacitor.
FIG. 2 is a cross-sectional view showing an example (IEEE Trans.

Electron Devices, Vol, ED-
27, p. 1586, published in 1980).

A silicon oxide film 4 is formed on the surface of the silicon semiconductor substrate 41.
2 is formed, and openings are selectively provided in this silicon oxide film 42. A diffusion region 43 into which impurities are introduced is selectively provided on the surface of the semiconductor substrate 41 in this opening. A silicon film 44 is formed in a predetermined pattern on the silicon oxide film 42, filling the opening. Impurities are introduced into this silicon film 44 at a high concentration. This silicon film 4
A capacitor insulating film 4B is formed on the silicon oxide film 42 including the top of 4B.
is formed. A counter electrode 47 is formed on this capacitive insulating film 46.

In this semiconductor device, the silicon film 44 is a capacitor lower electrode, and the capacitor lower electrode, the capacitor insulating film 4B, and the counter electrode 47 constitute a charge storage capacitor.

Next, a method for manufacturing this semiconductor device will be explained.

First, a thick silicon oxide film 42 for element isolation is formed on the surface of a silicon semiconductor substrate 41, and this silicon oxide film 4
2 is selectively provided with an opening. Thereafter, this opening is filled and a silicon film 44 made of polysilicon containing, for example, phosphorus at a concentration of 1020 ato S/CD13 is formed on the silicon oxide film 42 in a predetermined pattern. Then, phosphorus is diffused from this silicon film 44 to the surface of the substrate 41 to selectively form a diffusion region 43.

Next, a capacitor insulating film 4e is formed to cover the Schiff J-con film 44. Thereafter, polysilicon or the like doped with impurities is deposited on the capacitor insulating film 46 to form a capacitor counter electrode 47. As a result, the above-described semiconductor device is completed.

[Problems to be Solved by the Invention] However, in the conventional semiconductor device described above, the following problems have become apparent as density increases and miniaturization increases. That is, as the size of the opening provided in the silicon oxide film 42 is reduced, the aspect ratio of the opening increases, so polysilicon containing effective impurities such as phosphorus for forming the silicon film 44 is used in the opening. It is difficult to embed and form the Further, when the capacitor insulating film 46 is made thinner, an inversion phenomenon of the capacitor lower electrode occurs at the contact surface with the capacitor insulating film 46, resulting in a decrease in the capacitance value of the charge storage capacitor. In order to avoid this, it is necessary to increase the concentration of effective impurities contained in the silicon film 44, which is the capacitor lower electrode, but it is not possible to bury polysilicon with a high impurity concentration into the opening with a large aspect ratio. It is extremely difficult.

Furthermore, in order to secure a predetermined capacitance value while increasing the density, it is necessary to increase the surface area of the capacitor lower electrode per unit area on the substrate surface, but conventionally, the surface area of the capacitor lower electrode per unit area on the substrate surface has to be increased.
Alternatively, it is difficult to reduce the distance between the elements and other elements, which impedes higher density.

The present invention has been made in view of such problems, and includes:
A charge storage capacitor that can secure a predetermined capacitance value, reduce the distance between the charge storage capacitor and other charge storage capacitors or elements, and enable semiconductor devices to be made more densely packed than before. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same.

[Means for Solving the Problems] A semiconductor device equipped with a charge storage capacitor according to the present invention includes a lower electrode provided on a semiconductor substrate with an insulating film interposed therebetween, and a dielectric material covering the side and upper surfaces of the lower electrode. In a semiconductor device including a charge storage capacitor constituted by a film and a counter electrode formed on the dielectric film, the lower electrode comprises:
It is characterized by being composed of a first silicon film and a second silicon film that covers the side and top surfaces of the first silicon film and is electrically connected to the first silicon film.

A method of manufacturing a semiconductor device with a charge storage capacitor according to the present invention includes a step of forming an insulating film on the surface of a semiconductor substrate, a step of selectively forming an opening in the insulating film, and a step of filling the opening. A first pattern is formed on the insulating film in a predetermined pattern.
The method is characterized by comprising the steps of forming a silicon film, and forming a second silicon film by selectively growing polysilicon on the side and top surfaces of the first silicon film.

[Operations] In the present invention, the capacitor lower electrode is constituted by the first and second silicon films. Therefore, for example, the first silicon film is formed by a method such as selective epitaxial growth, selective polysilicon growth, or amorphous silicon growth that provides excellent coverage in the opening, and the second silicon film is formed by selective polysilicon growth. As a result, the diffusion region formed on the substrate surface and the lower capacitor electrode can be reliably connected, and the distance between the capacitor and another capacitor or other element can be reduced. Further, for example, by increasing the impurity concentration of the second silicon film, the reversal phenomenon at the contact surface between the dielectric film (capacitor insulating film) and the capacitor lower electrode can be avoided. Therefore, it becomes possible to increase the density of semiconductor devices.

In this case, by providing a high melting point metal such as tungsten or a barrier metal film such as titanium nitride or tungsten nitride between the second silicon film and the electric film, the dielectric film and the second silicon film can be separated. direct contact is prevented;
Even if the impurity concentration of the second silicon film is not made high, it is possible to avoid a decrease in the capacitance value due to the inversion phenomenon.

In addition, in the method of the present invention, the capacitor lower electrode is formed by filling the opening with a first silicon film, and selectively growing polysilicon on the top and side surfaces of the first silicon film to form a second silicon film. The formation process is divided into two steps. Thereby, a semiconductor device having a charge storage capacitor having the above-described structure can be easily manufactured.

When the first silicon film is formed, for example, by selective epitaxial growth using a vapor phase growth (hereinafter referred to as CVD) method, the opening can be reliably filled, and the first
It is possible to form extremely fine silicon films. For this reason, the first silicon film is preferably formed by selective epitaxial growth using the CVD method.

Embodiments Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a sectional view showing a semiconductor device equipped with a charge storage capacitor according to a first embodiment of the present invention.

A silicon oxide film 2 is formed on the surface of the P-type silicon semiconductor substrate 1.
is relatively thick. An opening is selectively provided in this silicon oxide film 2, and an N" type diffusion region 3 is formed on the surface of the substrate 1 in this opening. Furthermore, while filling the opening, silicon oxide A silicon film (first silicon film) 4 is formed in a predetermined pattern on the film 2.Arsenic or phosphorus is added to this silicon film 4 in a predetermined pattern.
The tail was introduced at a concentration of Q15 to 10'8 atoms/cm3.

A selective polysilicon film (second silicon film) 5 doped with impurities is deposited on the side and top surfaces of this silicon film 4. Arsenic or phosphorus is introduced into this selective polysilicon film 5 at a concentration of xol& to 1020 atol++s/Cm3. A capacitor insulating film 6 made of a high dielectric constant material film such as a silicon nitride film or a tantalum oxide film is formed on the silicon oxide film 2 including the selected polysilicon 5.
is formed, and on this capacitive insulating film 6 is a counter electrode 7 made of polysilicon or metal material doped with impurities.
is formed.

In this embodiment, the capacitor lower electrode is composed of a silicon film 4 and a selective polysilicon film 5, and the impurity concentration of the selective polysilicon film 5 is 1018 to 101020.
Since it is as high as ato/cm', an inversion phenomenon at the contact surface between the capacitor lower electrode and the capacitor insulating film 6 can be avoided even if the film thickness of the capacitor insulating film 6 is made thin.

FIG. 2 is a cross-sectional view showing the method for manufacturing the above-described semiconductor device, and FIG. 3 is a plan view thereof.

First, after forming a relatively thick silicon oxide film 2 for element isolation on a P-type silicon substrate 1, this silicon oxide film 2 is
An opening 2a is selectively provided in the opening 2a.

Next, arsenic or the like is ion-implanted into the substrate surface through this opening 2a to form an N1 type diffusion region (not shown). Thereafter, arsenic or phosphorus is grown at 1015 to 1018 atoIls by selective epitaxial growth, selective polysilicon growth, normal polysilicon growth, or amorphous silicon growth using the substrate 1 exposed in the opening 2a as a growth seed.
A silicon-containing film 4 is formed at a concentration of /am'. Note that when the silicon film 4 is formed by amorphous silicon growth, this silicon film 4 is subjected to heat treatment to convert silicon into polysilicon. Further, when forming the silicon film 4 by polysilicon growth and amorphous silicon growth, a known microfabrication technique is used for patterning.

Next, by CVD method, arsenic or phosphorus is added only on the surface of this silicon film 4 at 1018 to 11)20 atoms/
Too much polysilicon containing at a concentration of cs+3.

A selective polysilicon film 5 is formed by selectively growing the polysilicon film 5 to a thickness of 5,000 to 5000 nm.

Next, as shown in FIG. 1, a capacitor insulating film 6 is formed by depositing a high dielectric constant material such as a silicon nitride film or a tantalum oxide film on the entire surface. Thereafter, polysilicon or a metal material doped with impurities is deposited on the capacitor insulating film 6 to form a counter electrode 7.

As described above, in this embodiment, the silicon film 4 is formed by selective epitaxial growth or selective polysilicon growth using the semiconductor substrate 1 exposed in the opening 2a as a seed;
Alternatively, after forming a silicon film by polysilicon growth, amorphous silicon growth, etc., this silicon film is molded by microfabrication technology to form the silicon film 4. Therefore, even if the aspect ratio of the opening is large, the opening can be filled in a good condition. Furthermore, since the polysilicon film 5 is formed by selectively growing polysilicon on the side and top surfaces of the silicon film 4, when a plurality of charge storage capacitors are formed, as shown in FIG. The lower electrodes can be formed very close to each other. As a result, the surface area of the capacitive lower electrode per unit area of the substrate surface can be increased by about 50% compared to the conventional method.

FIGS. 4(a) to 4(h) are cross-sectional views showing, in order of steps, a method for manufacturing a semiconductor device according to a second embodiment in which the present invention is applied to a DRAM.

First, as shown in FIG. 4(a), a channel stopper region 12 is selectively formed on the surface of a P-type silicon semiconductor substrate 11, and a silicon oxide film 13 is formed on this channel stopper region 12.

Next, as shown in FIG. 4(b), a gate oxide film 14 is formed on the substrate 11, and a gate electrode 15 is selectively formed on the gate oxide film 14 using polysilicon containing phosphorus, silicide, or the like. to form. Using this gate electrode 15 as a mask, phosphorus ions are implanted into the surface of the substrate 11 to form a relatively shallow diffusion region 1θ. after that,
Spacers 17 made of silicon oxide or the like are formed on the sides and above the gate electrode 15.

Next, as shown in FIG. 4C, arsenic or phosphorus is ion-implanted into the surface of the substrate 11 using the gate electrode 15 and spacer 17 as a mask, and then heat treatment is performed to form a relatively deep diffusion region 18. do. This heat treatment oxidizes the surface of the substrate 11.

Next, as shown in FIG. 4(d), openings are selectively provided on the diffusion region 18. After that, increase the phosphorus from 1016 to 1
The opening is filled with polysilicon containing a concentration of 01017ato/cm', and the spacer 17 is
A polysilicon film 19 is formed thereon in a predetermined pattern.

In this case, since the impurity concentration of phosphorus contained in polysilicon is relatively low, even if the aspect ratio of the opening is large, the opening can be formed while suppressing deterioration of film coverage during polysilicon film formation. Can be embedded.

Next, as shown in FIG. 4(e), using the CVD method as in the first embodiment, the polysilicon film 19 is coated with phosphorus at 1018 to 1020 atlls/C.
A selective polysilicon film 20 is formed by selectively growing polysilicon containing a concentration of va3.

Next, as shown in FIG. 4(f), a capacitive insulating film 2 is formed over the entire surface.
form 1. This capacitive insulating film 21 is formed by forming a silicon nitride film and thermally oxidizing its surface, or by using a silicon nitride film, which has a film density of approximately 50% in terms of silicon oxide film.
Form to the thickness of a person.

Next, as shown in FIG. 4(g), a counter electrode 22 is formed on the capacitor insulating film 21, and the counter electrode 22 and the capacitor insulating film 21 are patterned.

Next, as shown in FIG. 4(h), an interlayer insulating film 23 is formed on the entire surface, and openings reaching the diffusion region 18 from the surface of the glabellar insulating film 23 are selectively provided. Then, while filling the opening, electrode wiring 24 is formed on the interlayer film 23 in a predetermined wiring pattern. In this way, DR
AM can be manufactured.

In this embodiment, the polysilicon film 19 and the selective polysilicon film 20 constitute a capacitor lower electrode.

In this case, since the impurity concentration of the polysilicon film 19 is relatively low, the polysilicon film 19 can be buried and formed in an opening having a large aspect ratio with good coverage. Further, since the selective polysilicon film 20 is deposited on this polysilicon film 19, the surface area of the capacitor lower electrode is relatively large. Furthermore, it is possible to adjust the impurity concentration in the selective polysilicon film 20 of this capacitor lower electrode. Therefore, even if the thickness of the capacitor insulating film 21 is reduced, by increasing the impurity concentration in this selective polysilicon film 20,
It is possible to suppress the inversion phenomenon at the contact surface between the capacitor lower electrode and the capacitor insulating film and the accompanying decrease in the capacitance value. As a result, DRAMs can be manufactured with extremely high density compared to conventional methods.

FIG. 5 is a sectional view showing a semiconductor device equipped with a charge storage capacitor according to a third embodiment of the present invention.

A silicon oxide film 32 is formed on the surface of the semiconductor substrate 31. An opening is selectively provided in this silicon oxide film 32, and an N-type scattering layer 33 is formed below this opening. In addition to filling this opening, a silicon film 34 is formed on the silicon oxide film 32 in a predetermined pattern.

A selective polysilicon film 35 is deposited on the side and top surfaces of this silicon film 34. Furthermore, a barrier metal film 38 made of a high melting point metal such as tungsten or titanium nitride is deposited on the side and top surfaces of this selective polysilicon film 35. A capacitor insulating film 3θ is formed on the silicon oxide film 32 including the barrier metal film 38. Further, a counter electrode 37 is formed on the capacitive insulating film 36.

In this embodiment, a barrier metal film 38 is interposed between the selective polysilicon film 35 and the capacitive insulating film 36.
This barrier metal film 38 allows the selective polysilicon film 35 to
This prevents contact between the capacitive insulating film 36 and the capacitor insulating film 36. Therefore, even if a tantalum oxide film with a high dielectric constant is used as the capacitor insulating film 36, the tantalum oxide film will react with the selective polysilicon film 35 and the insulation properties of the capacitor insulating film 36 will deteriorate. It can be avoided. In this way, by using a material with a high dielectric constant as the capacitor insulating film 36, the charge storage capacitor can be further miniaturized. Furthermore, since the selective polysilicon film 35 and the capacitive insulating film 36 do not come into direct contact with each other, the inversion phenomenon can be avoided even if the impurity concentration of the selective polysilicon film 35 is not low.

FIGS. 6(a) to 6(h) are cross-sectional views showing the method for manufacturing the above-mentioned semiconductor device in the order of steps.

First, as shown in FIG. 6(a), a relatively thick silicon oxide film 32 for isolation between elements is formed on the surface of a P-type silicon semiconductor substrate 31 by a known selective oxidation method.

Then, openings are selectively formed in this silicon oxide film 32.

Next, as shown in FIG. 6(b), arsenic ions are implanted into the substrate 31 through the opening, and then heat treatment is performed to form an N'' type diffusion region 33.

Next, using the same method as in the first embodiment, arsenic or phosphorus is added at 1015 to 10' to fill the opening and form a predetermined pattern on the silicon oxide film 32.
``Silicone film 3 containing at a concentration of atoms/cm3
form 4.

Next, as shown in FIG. 6C, a selective polysilicon film 35 containing arsenic or phosphorus is formed on the side and top surfaces of this silicon oxide film 32 by selective CVD. In this case, the concentration of arsenic or phosphorus in the selective polysilicon film 35 is made to be approximately the same as the concentration of arsenic or phosphorus in the silicon film 34.

Next, as shown in FIG. 6(d), by sputtering,
A titanium metal thin film 38a is deposited on the entire surface to a thickness of 500 to 1000 nm. After that, this titanium metal thin film 38a
Heat treatment is applied to. As a result, the portion of the titanium metal thin film 38a in contact with the selective polysilicon film 35 reacts with the polysilicon to form a titanium silicide film. After that, the substrate 31 was washed with NH4OH, H20Q and H.
Immerse in a chemical solution consisting of O. As a result, Fig. 6(e)
As shown in , the titanium on the silicon oxide film 32 is removed, and the titanium silicide film 38b remains only on the surface of the selective polysilicon film 35.

Next, heat treatment is performed in an ammonia atmosphere. As a result, as shown in FIG. 6(f), the titanium silicide film 38
b changes into a barrier metal film 38 made of a titanium nitride film.

Next, as shown in FIG. 6(g), a capacitor insulating film 36 made of a tantalum oxide film is formed to a thickness of 100 nm over the entire surface by plasma CVD or sputtering. The dielectric constant of this insulating film made of tantalum oxide film is extremely large, 4 to 5 times that of a silicon dioxide film conventionally used as a capacitor insulating film. Therefore, this capacitive insulating film 36 corresponds to an extremely thin silicon dioxide film having a film thickness of approximately 20 to 30 mm.

Next, as shown in FIG. 6(h), tungsten is deposited on the entire surface by bias sputtering or CVD to form a counter electrode 37 made of tungsten.

This completes the semiconductor device.

In this embodiment, in order to form a barrier metal film 38 such as titanium nitride on the surface of the selective polysilicon film 35,
It becomes possible to use a high dielectric constant material such as a tantalum oxide film as the capacitor insulating film 36. If such a barrier metal is not used, a high dielectric constant material such as a metal oxide will react with the silicon element that makes up the capacitor lower electrode, and the insulation properties of this high dielectric constant material will deteriorate significantly, causing it to fail as a capacitor insulating film. ceases to function. However, in this embodiment, a barrier metal film 3 is used between the capacitor lower electrode and the capacitor insulating film 3θ.
8 is present, it is possible to prevent the reaction between silicon element and metal oxide, etc.

Further, in this embodiment, since the inversion phenomenon of the surface of the selective polysilicon film 35 is prevented by the barrier metal film 38, the impurity concentration of the selective polysilicon film 35 may be the same as the impurity concentration of the silicon film 34.

Note that, like the second embodiment, this embodiment can be easily applied to a DRAM cell section.

Furthermore, in each of the embodiments described above, N is added to the capacitor lower electrode.
Although a type impurity is introduced, the same effect as in each of the above embodiments can be obtained even if the capacitor lower electrode contains a P type impurity such as boron.

[Effects of the Invention] As explained above, according to the present invention, since the lower electrode of the capacitor is composed of two layers of the first and second silicon films, it is possible to reduce the impurity concentration of the first silicon film, for example. By filling the opening with this first silicon film and increasing the impurity concentration of the second silicon film on the dielectric film side, good coverage can be obtained even in the opening with a large aspect ratio. Even if the thickness of the dielectric film is reduced in order to increase the density of semiconductor devices, the inversion phenomenon can be avoided and a predetermined capacitance value can be ensured.

Furthermore, in the method of the present invention, after forming the first silicon film by selective epitaxial growth or the like, polysilicon is selectively grown on the side surfaces and the top surface of the first silicon film to form the second silicon film. The distance between a charge storage capacitor and another charge storage capacitor or other element can be made extremely narrow. As a result, it is possible to significantly increase the density of a semiconductor device including a charge storage capacitor compared to the conventional one while ensuring a predetermined capacitance value.

Therefore, the present invention provides a 64 megapixel) DRAM and a [24 megapixel] DRAM.
It is extremely useful for manufacturing high-density semiconductor devices such as megabit DRAM.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a semiconductor device equipped with a charge storage capacitor according to a first embodiment of the present invention, FIG. 2 is a sectional view showing a manufacturing method thereof, and FIG. 3 is a plan view thereof. 4(a) to (h) are cross-sectional views showing in order of steps a method for manufacturing a semiconductor device according to a second embodiment in which the present invention is applied to a DRAM, and FIG. 5 is a cross-sectional view according to a third embodiment of the present invention. Cross-sectional views showing a semiconductor device equipped with a charge storage capacitor, FIGS. 6(a) to (
h) is a sectional view showing the manufacturing method in the order of steps;
The figure is a cross-sectional view showing an example of a conventional semiconductor device equipped with a charge storage capacitor. 1.11.31,41: Semiconductor substrate, 2.13°32.
42; Silicon oxide film, 2a; Opening, 3°16.18
, 33, 43; Diffusion region, 4, 34° 44; Silicon film, 5, 20, 35; Selective polysilicon film, 8, 21.3
6, 48; Capacitive insulating film, 7.22, 37, 47; Counter electrode, 12; Channel stopper region, 14; Gate oxide film, 15; Gate electrode, 17: Spacer, 19; Polysilicon film, 23; Interlayer insulation Film, 24; Electrode wiring, 38; Barrier metal film, 38a; Titanium metal thin film, 38b; Titanium silicide film

Claims (5)

[Claims] (1) A charge storage capacitor composed of a lower electrode provided on a semiconductor substrate via an insulating film, a dielectric film covering the side and upper surfaces of this lower electrode, and a counter electrode formed on this dielectric film. In the semiconductor device, the lower electrode includes a first silicon film, and a second silicon film that covers the side and top surfaces of the first silicon film and is electrically connected to the first silicon film. What is claimed is: 1. A semiconductor device comprising a charge storage capacitor. (2) The semiconductor device with a charge storage capacitor according to claim 1, wherein a barrier metal film is interposed between the second silicon film and the dielectric film. (3) There are 10^1^5 impurities in the first silicon film.
The impurities are introduced into the second silicon film at a concentration of 10^1^8 atms/cm^3.
2. The semiconductor device according to claim 1, wherein the charge storage capacitor is introduced at a concentration of 8 to 10^2^0 atoms/cm^3. (4) forming an insulating film on the surface of the semiconductor substrate; selectively forming an opening in the insulating film; burying the opening and forming a first insulating film in a predetermined pattern on the insulating film;
and forming a second silicon film by selectively growing polysilicon on the side and top surfaces of the first silicon film. A method for manufacturing a semiconductor device. (5) The method for manufacturing a semiconductor device with a charge storage capacitor according to claim 4, wherein the first silicon film is formed by selective epitaxial growth of silicon using a vapor phase growth method.