JPS62293629A - Accelerated life test of semiconductor device - Google Patents

Abstract

PURPOSE:To enable many semiconductor devices in a sheet of wafer to be tested simultaneously, by using elastic needles implanted vertically in the wafer surface. CONSTITUTION:A spacer 6 having a hole formed in conformity with an outside shape of a wafer 4 is mounted on a heater 17, and then the wafer 4 is put into the hole of the spacer 6, with a cover 2 being put thereon from above. Many needles 1, which are vertically extended downwards with up-and-down directional elasticity, are implanted in the cover 2. The needles 1 become in contact with the electrodes of respective semiconductor devices inside the wafer 4. The cover 2 is tightened to be fixed by means of fixing tools 3 until it becomes in close contact with the spacer 6. Current is then supplied to the heater 17. After temperature becomes stabilized, bias voltage is supplied from the terminals 5 on the cover 2 and impressed on the respective semiconductor devices inside the wafer 4, through the needles 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an accelerated life testing method for a semiconductor device, and more particularly to an accelerated life testing method for a semiconductor device in which the semiconductor device is tested in a wafer state.

[Conventional technology]

Conventionally, an accelerated life test of a semiconductor device in a wafer state has been carried out by a method as illustrated in FIGS. 2 and 3. That is, the example shown in FIG. 2 is a method in which the needle 8 is brought into oblique contact with the wafer 4 mounted on the heater 7, and a bias voltage is applied to the needle 8 while heating the heater 7. In the example shown in FIG. 1, a wafer 4 mounted on a heater 7 is sandwiched between lids 9 having electrodes 1O, and a bias voltage of 10 is applied to the electrodes.

In the conventional accelerated life test method for semiconductor devices as described above, in the case of the method shown in FIG. When attempting to test a large number of semiconductor devices using a single wafer, there is a drawback in that it is not possible to test a large number of semiconductor devices at the same time because adjacent needles come into contact with each other. In addition, in the case of the method shown in Figure 3, it is possible to test a large number of semiconductor devices at the same time, but since the electrodes for applying bias that come into contact with the wafer are not stretchable, it is not possible to test the wafer with a heater. The drawback is that when the wafer is sandwiched between the lids, a large amount of pressure is applied to a part of the wafer, potentially causing it to crack.

[Problem that the invention seeks to solve]

The problem to be solved by the present invention, in other words, the purpose of the present invention is to eliminate the drawbacks of the conventional accelerated life testing method for semiconductor devices as described above, and to simultaneously test a large number of semiconductor devices in poor wafer condition. An object of the present invention is to provide a method for accelerated life testing of semiconductor devices that is highly safe because it is possible to perform the following steps, and there is no risk of damaging the wafer.

[Means for solving problems]

In the accelerated life test method for semiconductor devices of the present invention, a spacer with a predetermined thickness and a hole that matches the external shape of the wafer is placed on a heater that has a flat top surface and can be set to an arbitrary temperature. The wafer of the test object is inserted into the hole and brought into contact with the heater. A cover having a plurality of needles that is extendable and has a length larger than the difference between the thickness of the spacer and the thickness of the wafer is placed on the cover, and the cover is fixed in close contact with the spacer, and then the heater is fixed. The temperature is maintained at a set temperature by supplying current to the needle, and a bias voltage is supplied to the needle.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line A-A, showing an example of a test apparatus using an embodiment of the present invention.

In FIG. 1, a spacer 6 having a hole shaped to match the outer shape of the wafer 4 is placed on top of the heater 17, the wafer 4 is placed into the hole of the spacer 6, and the lid 2 is placed from above. A large number of needles 1 extending vertically downward are implanted in the lid 2, and these needles 1 come into contact with the electrodes of each semiconductor device in the wafer 4, and all the needles 1 have elasticity in the vertical direction. The length is longer than the difference between the thickness of the spacer 6 and the thickness of the wafer 4.

Next, the lid 2 is tightened and fixed with the fixture 3 until it comes into close contact with the spacer 6, and current is supplied to the heater 17 to raise the temperature to the set temperature. After the temperature has stabilized, a bias voltage is applied from a terminal 5 provided on the lid 2 to apply a bias voltage to each semiconductor device on the wafer 4 via the needle 1, thereby performing an accelerated life test on each semiconductor device on the wafer 4.

〔Effect of the invention〕

As explained above, the accelerated life test method for semiconductor devices of the present invention uses elastic needles installed in a direction perpendicular to the surface of the wafer to test a large number of semiconductor devices within a single wafer. This method has the effect of allowing tests to be performed simultaneously, and because the elasticity of the needle does not apply large force to the local area of the wafer, the test can be performed safely without damaging the wafer. be.

[Brief explanation of drawings]

1(a) and 1(b) are a plan view and an A-A sectional view showing an example of a test apparatus using an embodiment of the accelerated life test method for semiconductor devices of the present invention, and FIGS. 2 and 3 1 is a cross-sectional view showing an example of a conventional test method. 1...needle, 2...lid, 3...fixing tool, 4...
Wafer, 5... terminal, 6... spacer, 7...
- Heater, 8... needle, 9... lid, 10... electrode.

Claims (1)

[Claims] A spacer with a predetermined thickness and a hole that matches the external shape of the wafer is placed on a heater that has a flat top surface and can be set to any temperature, and the wafer of the test object is placed in the hole of the spacer. The spacer is fitted into contact with the heater, is provided at a position corresponding to each semiconductor device in the wafer, is planted vertically downward, is expandable and contractable in the vertical direction, and has the dimensions of the spacer. Covering the wafer with a lid having a plurality of needles with a length greater than the difference between the thickness of the wafer and fixing the lid in close contact with the spacer, supplying current to the heater to maintain the temperature at a set temperature; An accelerated life test method for a semiconductor device, comprising supplying a bias voltage to the needle.