JPS62293342A - Decimal addition/subtraction system - Google Patents

Abstract

PURPOSE:To perform a decimal multiple operation with the same instruction regardless of an operator by using a register to store the designated operator and carrying out successively the operations divided by an arithmetic instruction common with the flag of said register. CONSTITUTION:The instruction code part of an arithmetic instruction M is decoded by a decoder 11 and erases the flag of a flag register 12 via an inverter 13 and an OR circuit 14 to set it at 0 when a processing instruction ABCD instructing the addition of decimals including no positive/negative code is outputted in the form of value '1'. While a flag 1 is set to the register 12 via the circuit 14 when a processing instruction SBCD instructing the subtraction of decimals including no positive/negative code is outputted in the form of '1'. In such a way, a decimal arithmetic circuit carries out successively additions or subtractions in response to the flag state of the register 12 after an arithmetic instruction DCE is received.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] In order to process additions and subtractions of decimal numbers exceeding the number of significant digits of an arithmetic register by dividing them into each number of significant digits of this register, a specified A register is provided to store a flag indicating an operator, and the divided operations are sequentially executed using this flag and an operation instruction common to addition and subtraction.

[Industrial application field]

This invention relates to a decimal addition/subtraction method that performs addition/subtraction of decimal numbers with a number of digits exceeding the number of effective digits of an arithmetic register, such as in double-precision arithmetic.

[Conventional technology]

When performing an operation on a decimal number with a number of digits exceeding the number of significant digits in the operation register (hereinafter referred to as "1-double precision operation" for convenience), such as double-precision operation, the decimal number is calculated for each number of significant digits in this register. is divided from the lower digits, and first performs an operation using a specified operator on the lower digits having the number of digits from the lowest order corresponding to the number of significant digits of the two registers of the two numbers to be operated,
The calculation is performed using the resulting carry or digit and the upper digits of the two numbers to be calculated, that is, the value of the upper digit that exceeds the number of effective digits of operation 1/register.
When performing such additions and subtractions, dedicated addition and subtraction instructions for carry or borrowing are required, and for this reason separate instruction codes were assigned for addition and subtraction with carry. .

[Problem that the invention seeks to solve]

In the present invention, when such a double-length operation is performed, the same instruction can be used to perform the double-length operation on a decimal number, regardless of the operator of the operation to be executed.

[Means for solving problems]

As shown in the schematic principle diagram in Figure 1, a register 1 is provided to store flags instructing addition and subtraction specified by operation instructions, and operations divided by the number of significant digits of operation registers 21 and 22 are sequentially executed. When processing, by executing the addition or subtraction specified by this flag,
This allows addition or subtraction to be performed using the same arithmetic instruction.

In the figure, M is an operation instruction including an instruction code part M1 and an operand specification part M2, which are shown in the form of an instruction register for convenience, and A and B are double-length decimal numbers to be operated, shown in the form of numerical registers for convenience. are shown as consisting of upper digits At, Bl and lower digits A2, B2, respectively, and as the arithmetic processing progresses, Al, Bl and A, 2, B2 are stored in the arithmetic registers 21 and 22. , according to the flag indicating the operator obtained by decoding the instruction code part M1 of the above operation instruction with the decoder 3,
In the decimal number arithmetic circuit 4, arithmetic processing including arithmetic operations between lower digits A2 and 82, upper digits AI and B, and carry-up or down-carrying is performed sequentially.

[For production]

By storing a flag indicating the operator specified by the arithmetic instruction in the flag register l, the arithmetic operations that are divided and executed sequentially according to the number of significant digits in the arithmetic registers 21 and 22 contain information specifying addition or subtraction. is not required, so the required processing is performed even if addition or subtraction is not specified in the instruction that instructs the operation on the upper digits, so the same operation instruction is used regardless of whether it is addition or subtraction. be able to.

〔Example〕

FIG. 2 shows an embodiment of the present invention, which corresponds to the part in the principle diagram shown in FIG. 1 that generates an arithmetic processing instruction from the flag register 1, decoder 3, and arithmetic instruction.

The instruction code part of the operation instruction M is decoded by a decoder 11 corresponding to the decoder 3 in FIG. 1, and a processing instruction ABCD (A
(BCD means addition, BCD means decimal number) is output as “1”, the flag in flag register 12 corresponding to flag register 1 in FIG. 1 is erased via inverter 13 and OR circuit 14, and “O '', and when the processing instruction 5BCD (S means subtraction, BCD means decimal number) that instructs subtraction of a decimal number that does not include positive or negative signs is output as "1", it is output to the flag register 12 via the OR circuit 14. flag ″1
” to cents.

As a result, when the arithmetic instruction DCE is given, addition or subtraction is executed depending on the state of the flag in the flag register 12.

In this example, the signals controlling these flags are OR
It is shown as being supplied to the flag register 12 via the circuit 14, and further when the operator specified by the operation instruction is converted to calculate the numerical value of the positive or negative sign material (for example, A-(- The sign output of the operator selection circuit 15 for setting the above-mentioned flag by the operator converted from B) to A+B) is also shown as being supplied to this OR circuit I4.

The decoder 11 further outputs an output S indicating that the instruction is to calculate a numerical value within the number of effective digits in the operation register (21.22 in FIG. 1) from the instruction code, and an output W indicating that it is a double-length operation instruction. is selectively output, AND circuit 1
By 6.17.18.19” - flag register 1
The AND circuit 16.17.18.1 of the flag from 2 and this output S or W is taken, and the arithmetic processing command that instructs the arithmetic processing of the decimal number arithmetic circuit 4 in FIG.
Output from 9.

AN that takes the AND of the output S of the decoder 11 and the output of the flag register 12, which indicates that the operation is within the number of effective digits.
The output (subtraction instruction) of the D circuit I6 (subtraction instruction) DCl, the output of the AND circuit 18 (addition instruction) which ANDs the output S of the decoder 11, and the output of the flag register 12 via the inverter 20. The decimal number calculation circuit (FIG. 1, 4) indicates that the operation is an operation, and as in the present invention, an operation according to the state of the flag in the flag register I2 is executed by an operation instruction that does not specify an operator. It is something that

Also, the output W of the decoder 11 indicating that it is a double-length operation
and the output of the flag register I2 (subtraction instruction) DCE, and the AND circuit 19 which takes the AND of the output W of the decoder 11 and the output of the flag register 12 via the impark 20. The DCE signal, which is the output (addition instruction) DCE, instructs the decimal number arithmetic circuit (FIG. 1, 4) to perform double length arithmetic according to the present invention.

〔Effect of the invention〕

For example, a conventional program for performing a double-length operation on the two numbers A and B mentioned above is as follows.

BRSUB −−−−−−−−−=−−−−−
-111A DD: --------
−−−−−+21A, B CD −−−−
------f3) A B CD E -----
------------(41BRNEXT ------
=−1−−−−〜〜 (5) SU B:
-------------111-[61SBCD
−〜−−−−−−−−−−−−−(71S B
CD E ----------------
-(8)NEXT: -1----
−−−−−−−−==−(9) On the other hand, the program according to the present invention is, for example, BRSUB −−−−−−−−−−−111
A, DD: ------------
−−+21A B CD −1−−−−−=
−−−−〜〜−−(3) B RN E W (F S
= 0) --001SUB:
−−−−1=−−−−−−−(6) S B CD
−−〜−−−−−〜−=−−−−(7+NEW
: −・−−−−−−−−−−1−−aυD
CE −−−−−−−−−1=−−−−−
Hit NEXT: -----------
---It will be as follows from 1 to (9).

Here, BR is a branch instruction, +il is a branch instruction to "SUB" if the specified operation is subtraction, (2) is an addition operation, (3) is a decimal addition instruction, and (4) is a double-length operation. decimal number addition instruction, (5) is “NEX” upon completion of the addition process.
Instruction to branch to "T", (6) is the branch destination name, (7) is the subtraction instruction, (8) is the decimal subtraction instruction using double-length operation, (9)
is the branch destination name, 0[ is the instruction to branch to "NEW", and at this time, the flag in the flag register is 0'' indicating addition.Also, αυ is the branch destination name, and α2) is the instruction that is common to addition and subtraction according to the present invention. This is an arithmetic instruction used for addition and subtraction, and as explained earlier, whether it is addition or subtraction is determined by the flag in the flag register.

As described above, according to the present invention, since the number of instructions is reduced by one, other instructions can be added as long as the number of instructions is equal to a certain number, and since the instructions for addition and subtraction can be used in common, it is possible to divide the instructions. The greater the number of times the calculations are performed, the greater the effect of reducing the program size and steps.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention. 1 is a flag register, 2 is an arithmetic register, 3 is a decoder for decoding the instruction code of an arithmetic instruction, and 4 is a decimal number arithmetic circuit. O

Claims (1)

[Claims] In order to perform the addition or subtraction of decimal numbers that exceed the number of valid digits in the calculation register by dividing them according to the number of valid digits in the calculation register (2), the decoder (3) decodes the calculation instruction and performs the addition or subtraction. A flag register (1) is provided to store a flag indicating a specified operator, and the decimal number calculation circuit (4) sequentially executes the divided operations using the instruction common to addition and subtraction and the flag. A decimal number addition/subtraction method featuring: