JP2529694B2 - Standby instruction execution device for microprocessor - Google Patents

Description

DETAILED DESCRIPTION [Outline] The present invention has a conventional WAIT instruction by providing one wait (WAIT) instruction having a special instruction format and configuring hardware for executing the instruction. Inconvenient as a result of executing a combination of several instructions in a non-microprocessor, for example, a check could not be made in a timely manner, or if a specific checkpoint was passed even a little, the following Solved the problem that the check could not be performed until a specific checkpoint in the check cycle, or that the same address group would be extracted unless a condition was met or the timer expired when address tracing was performed. There is.

[Industrial applications]

The present invention relates to a wait instruction execution device for a microprocessor, and more particularly to a wait instruction execution device for a microprocessor capable of efficiently processing a conventional wait routine with only one wait instruction.

[Conventional technology]

In the past, when performing WAIT processing in a microprocessor, some instructions were combined and executed because there was no special WAIT instruction.

For example, FIG. 5 shows a processing routine for monitoring the processing state of the microprocessor using a timer. That is, from the start of the processing routine performs initial value setting of the timer in step S _1, performs a state processing in step S _2, step
A judgment process result in S _3, if the decision result is good (YES) the process proceeds to the next step. However, if the determination result is not satisfactory (NO), the timer is decremented in step S ₄ , and the process proceeds to step S ₅ . The step
In S ₅ timer determines whether or not time out, the process operation is repeated so that the effects performs state process returns to step S ₂ if NO. However, as a result of step S _5, (the case of YES), if the timer times out, so that the process ends.

[Problems to be solved by the invention]

However, in the processing routine according to the above-mentioned conventional technique, since a plurality of instructions are combined and the instructions are executed, the number of used addresses also increases, so that an extra memory area is required. Further, even if the process state at the time of past processing in step S ₃ advances to the side of the success and thus escape the chance of the check, to wait until it passes a checkpoint for the following step S ₃ Therefore, there is a problem that the time corresponding to several steps is wasted.

Further, in the conventional processing device, when tracing the address of the instruction to be executed, only the same address group is repeatedly traced unless a check condition is satisfied to exit this routine or the timer times out. However, there is a problem that the trace memory becomes full, and when the trace memory is used cyclically, the trace results for other addresses are deleted.

[Means for solving problems]

FIG. 1 is a principle block diagram of an apparatus for realizing a standby instruction execution apparatus according to the present invention.

1 is a standby instruction provided in the present invention,
The waiting condition is determined by the fields D to F, the logic of the information corresponding to the external condition is taken in the field B, and the standby release is determined in the field C. Reference numeral 2 is a multiplexer group which receives external conditions and selects the standby condition, 3 is a logic gate circuit, and 4 is a multiplexer which selects the standby condition according to the contents of the C portion. Then, the standby instruction 1 is executed by the wire logic, and the same processing as the software processing in the conventional case shown in FIG. 5 is executed by one instruction.

[Action]

By utilizing only one wait instruction 1 having a special format according to the invention, the multiplexer group 2 and the logic gate circuit 3 correspond to the conditions given to the fields B to F when each part of the instruction is decoded. The processing result can be checked via and the timeout processing can be performed. Therefore, it is possible to execute a desired standby process without having a combination of many instructions as in the conventional case, so that the processing efficiency is improved.

〔Example〕

FIG. 2 is a WA for realizing the standby instruction execution device according to the present invention.
Indicates the IT command format.

The instruction format consists of fields A to G, and the total number of bits is 32 bits. That is, the field A is a 4-bit instruction code part, the field B is a 1-bit part for determining AND (OR) or OR (OR) condition, and the fields D, E, F described below are used.
It defines the condition of the angular state shown by the part. And B =
When it is 1, the AND condition is defined, and when B = 0, the OR condition is defined. Field C is a part that defines a 2-bit timer condition. Depending on what the 2-bit state is,
As shown in Fig. 3, internal timer timeout, external WAIT
The condition for releasing the status (EXTMO) is defined.

On the other hand, the field D consists of 3 bits and the WAIT condition WTC0, and the field E also consists of 3 bits and the WAIT
The condition WTC1 and the WAIT condition WTC2, each of which is also composed of 3 bits in the field F, constitute the WAIT condition WTC2. Therefore, the possible states of each of the 3 bits are (000), (001),
(010), (011), (100), (101), (110), (11
There are 8 types of 1), but the first (000) and the last (11)
The combination of 1) is treated as giving a logic 0 and a logic 1, respectively. These WAIT conditions (001) to (110) are associated with the EXCNDnm (n = 0,1,2, m = 0,1,2,3,4,5) signal input to the microprocessor from the outside. However, this will be described in detail later.

The G portion of the preceding WAIT instruction is a 16-bit branch destination address portion, and branches to this address when the WAIT condition is satisfied during standby.

FIG. 3 shows the configuration of a device that realizes the standby instruction execution device according to the present invention.

11 is a WAIT instruction register in which a wait instruction according to the present invention is entered, 1
2 is the first multiplexer, 13 is the second multiplexer, 1
Reference numeral 4 is a third multiplexer, 15 is an AND gate, 16 is an OR gate, 17 is a fourth multiplexer, 18 is a microprocessor timer, and 19 is a fifth multiplexer.

Here, the input signal EXCND from the outside is 18 combinations of EXCND00 to 05, EXCND10 to 15 and EXCND20 to 25 as shown in FIG. 3, and these are each logic "0" and "1".
It also serves as an input to the first, second, and third multiplexers. EXCNDn0 (n = 0,1,2) corresponds to the above (001), EXCNDn1 is (010), EXCNDn2 is (011), EXCNDn3 is (100), EXCNDn4 is (101), EXCNDn5 is It is configured to correspond to (110).

Also, as shown in the figure, the field B of the WAIT instruction conditions the input of the fourth multiplexer 17, and the field C
Are arranged to condition the inputs of the fifth multiplexer 19 and the fields D, E, F to condition the inputs of the first, second and third multiplexers 12, 13, 14.

 Next, the operation of the apparatus thus configured will be described.

External conditions EXCND00 to 05, EXCND10 to 15, EXCND20 to 25
Of the 18 inputs of the group, any one input of each one group is associated with a specific three bits of 001 to 110, and the first, second and third bits are selected to select them. A logic "0" or "1" input is fixedly applied to each of the multiplexers while being applied to select the multiplexers 1-3. At this time, when the WAIT instruction according to the present invention shown in FIG. 2 is entered into the instruction register 1, D, E, and F consisting of 3 bits from (000) to (111)
Partial bits are decoded and specified 3
Each output consisting of bits is output from the multiplexers 12, 13 and 14. The respective outputs are given to the inputs of the AND gate 15 and the OR gate 16, and the AND logic and the OR logic are respectively taken, and the resultant logic output is given to the fourth multiplexer 17.

On the other hand, the bit output of the field B that determines the WAIT condition of the fields D, E, and F of the WAIT instruction is given to the fourth multiplexer 17. Therefore, if B = 1, the output from the AND gate 15 is selected, and if B = 0, the output from the OR gate 16 is selected. Therefore, when an output is generated from the fourth multiplexer 17, in this case, it is determined that the desired AND or OR condition is satisfied, the "unsuccessful establishment" signal is output, and the branch destination address G branches to the address specified. To be done.

Further, the input of the fifth multiplexer 19 is an output signal from the timer 18 of the microprocessor and an external signal from the outside.
WAIT release signal EXTMO is given, and both signals are
It is selected and output according to the condition of the field C of the instruction shown in the figure. That is, (i) neither the output from the timer 18 nor the output from the WAIT release signal EXTMO is output when the value of the field C is "00", and (ii) the timeout from the timer 18 when the value of the field C is "01". Output a “successful or unsuccessful” signal in response to only (iii) the value of field C is “1”
When "0", the "unsuccessful establishment" signal is output only in response to the WAIT release signal EXTMO signal. (Iv) When the value of field C is "11" The "unsuccessful establishment" signal is output corresponding to either or both of the above. The timer 18 can also be set by a microprogram.

As described above, the microprocessor's standby instruction execution device according to the present invention can execute the same processing as the processing operation by a combination of several instructions shown in FIG. 5 with one instruction.

〔The invention's effect〕

According to the present invention, the processing result can be checked with an instruction having one address, and WAIT can be released (timeout) according to a specific condition. Therefore, when the check condition is satisfied, the process immediately proceeds to the next step without waiting time. Can be migrated.

Further, in the present invention, the same processing as the state monitoring routine, which is composed of several instructions as in the prior art, can be performed by executing only one instruction, so that the response to the processing result is quick and Addresses are not wasted. In addition, various processing results can be promptly dealt with depending on how the instruction content is set.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of a standby instruction execution device according to the present invention,
2 is a format of a standby instruction used in the apparatus of the present invention, FIG. 3 is a block diagram of an apparatus for realizing the standby instruction execution apparatus of the present invention, and FIG. 4 is defined by a field C in the instruction of FIG. FIG. 5 is a flow chart of a processing apparatus in which some instructions are combined according to the conventional apparatus. In the figure, 1 is the standby instruction format, 2 is the multiplexer group, 3
Is a logic gate circuit, and 4 is a multiplexer.

Claims (1)

(57) [Claims] 1. A first predetermined portion (D to
F), a second predetermined part (B) for designating an upper logical product or a logical sum corresponding to the external condition selected by the predetermined part, and a third predetermined part (C) for defining the waiting release condition,
An information processing apparatus configured to be able to process one standby instruction (1) having a fourth predetermined portion (G) that specifies a branch destination when a standby condition is satisfied, wherein the first predetermined portion A multiplexer group (2) that selects an external condition according to the content, and an output from the multiplexer group (2) is supplied as an input to perform logical processing, and the output is selected according to the content of the second predetermined portion, and the establishment is successful. A logic gate circuit (3) for issuing a signal, an output from the timer and a standby release signal are supplied as inputs, and one of the combination of the timer output and the standby release is selected according to the condition of the third predetermined portion. And a multiplexer (4) for issuing an unsuccessful success signal, and by executing the standby execution process with one instruction by decoding the standby instruction, execution of the standby instruction of the microprocessor Location.