JPS62291970A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the characteristics by relieving the thermal strain, etc., of a nitride film by a method wherein an impurity regions to be source.drain regions are formed before the title device is formed into MNOS structure. CONSTITUTION:Element isolating regions 11 are formed in specified regions of a P type semiconductor substrate 10; selective gates 4, 5 are patterned after specified shape through the intermediary of an oxide film 20; the gates 4, 5 are coated with another oxide film 21; and a photoresist 22 is formed between the gates 4, 5. First, impurity is led-in using the resist 22 and gates 4, 5 as masks to activate impurity regions 12, 13 by annealing process; and impurity regions to be source.drain regions are formed. Second, after pattern-forming another photoresist 23, the oxide films 21, 20 are removed in the region to form a memory gate, i.e., a region between gates 4, 5; the substrate 10 is exposed to form the other oxide film 3; and the resist 23 is removed to form a nitride film 2 into a part of MNOS structure. Finally, a polycrystalline silicon layer 24 as a polycrystalline semiconductor layer is formed on the nitride film 2.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention A. Industrial Application Field The present invention has a three-gate structure (so-called tri-gate structure) consisting of a pair of selection gates and a storage gate. The insulating film is so-called MNO3 (Metal N1tride).
The present invention relates to a method of manufacturing a semiconductor device having at least a nitride film, such as an oxide semiconductor structure.

B0 Summary of the Invention The present invention provides a method for manufacturing a semiconductor device in which a gate insulating film below a storage gate electrode formed between a pair of selection gate electrodes is composed of an oxide film and a nitride film, in which a mask layer is formed. By forming the impurity regions that will become the source/drain regions before forming the MNO3 structure, the thermal distortion of the nitride film can be alleviated and the characteristics can be improved.

C9 Conventional technology so-called EEPROM (Electrically
Erasable and Programmable
Among semiconductor devices such as eReadOnlyMemory), devices employing elements having an MNO3 structure are known.

This MNO3 structure has at least a nitride film as a gate insulating film. For example, an extremely thin oxide film is formed on the main surface of a semiconductor substrate such as a silicon substrate, a nitride film is formed on the oxide film, and the nitride film is It has a laminated structure in which gate material is formed on the film. And MNO3 like this
In an EEPROM consisting of elements of this structure, first, when writing information signals, a high voltage is supplied to the selected element, and carriers (electrons) are tunneled through the oxide film and then transferred to the interface with the nitride film. and capture it and cause vth fluctuations there. When reading an information signal from such an element, a predetermined reading becomes possible based on the difference in vth.

By the way, when forming an element having a so-called three-gate structure and an MNO3 structure, the source/drain regions are formed in a so-called self-line using a mask consisting of a storage gate and a pair of selection gates to facilitate the process. ing. In addition, as the gate material formed on the nitride film, a polycrystalline semiconductor layer such as a polycrystalline silicon layer, which can be made finer than materials such as Ai, is generally used. Phosphorus or the like is diffused into the impurity-free polycrystalline silicon layer deposited by et al. in order to impart monoelectricity.

D1 Problems to be Solved by the Invention However, in the device with the MNO3 structure as described above,
Thermal distortion occurs in the nitride film, resulting in deterioration of characteristics over time.

That is, the source/drain regions of a three-gate electrode device having a pair of selection gates and a storage gate are formed using a so-called self-line using three gate electrodes as described above; In order to do this, the gate electrode must already be punctured during ion implantation, etc., and the heat treatment during annealing of the source/drain region may cause the part of the gate insulating film that exists under the storage gate electrode to The quality of the nitride film deteriorates, and this appears as characteristic deterioration over time.

For example, Figure 2 compares nitrogen annealing and hydrogen 7 annealing in terms of memory retention function as heat treatments when forming source/drain regions. Deterioration of characteristics cannot be avoided only when annealing is used.

Furthermore, when impurities are introduced into the polycrystalline silicon layer serving as the gate material by diffusion of phosphorus, etc., as described above, the heat treatment required for the diffusion ranges from approximately 950°C to
Since the heat treatment is performed at a temperature of about 1000° C. for, for example, 20 minutes, there is a negative impact on the nitride film. Furthermore, diffusion of impurities such as phosphorus into the nitride film may also have adverse effects such as alteration of the nitride film.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device in which the thermal strain of a nitride film is alleviated and the characteristics are improved.

Means for Solving Problem E8 The present invention provides a method for manufacturing a semiconductor device in which a gate insulating film below a storage gate electrode formed between a pair of selection gate electrodes is composed of an oxide film and a nitride film. forming the pair of selection gate electrodes on the substrate; forming a mask layer between the pair of selection gate electrodes; and introducing impurities into the substrate using the pair of selection gate electrodes and the mask layer as a mask. a step of heat-treating the substrate to form an impurity region using the introduced impurity;
A method for manufacturing a semiconductor device comprising the steps of forming an oxide film between the pair of selection gate electrodes, forming a nitride film on the oxide film, and forming the gate electrode on the nitride film. This solves the above problems.

F2 action In the present invention, impurities are introduced into the substrate, and an impurity region is formed by heat treatment. During this heat treatment, the region where the memory gate is to be formed is covered with the mask layer. Since the nitride film has not yet been deposited, the nitride film forming the MNO8 structure is not affected by the heat treatment. Therefore, it is possible to prevent characteristics such as memory retention function from deteriorating over time.

Further, the mask layer serves as a mask together with a pair of selection gate electrodes when impurities are introduced to form source/drain regions. Therefore, the introduction of impurities is performed in the self-alignment line, and it is possible to simplify the process and improve the performance of the device.

G. Example Preferred embodiments of the present invention will be described with reference to the drawings.

The method for manufacturing a semiconductor device of this embodiment is an example of a method for manufacturing an EEFROM having a three-gate structure, in which the storage gate has the MNO5 structure as described above, and the storage gate is formed after the source/drain regions are formed. Therefore, thermal distortion of the nitride film is suppressed, and deterioration of the memory retention function over time is prevented.

First, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.

(a) As shown in FIG. 1a, element isolation regions 11 are formed in predetermined regions of P-type semiconductor substrates Fj, io, such as silicon substrates, by selective oxidation or the like. Note that the same applies to a well region of a semiconductor substrate.

Next, a pair of selection gates 4.5 are formed with the oxide film 20 interposed therebetween. This selection gate 4.5 is a first layer of polycrystalline silicon layer, is patterned into a predetermined shape as a selection gate, and is covered with an oxide film 21.

(b) Next, as shown in FIG. 1, a photoresist 22 is formed as a mask layer in the region between the selection gates 4.5 where storage gates are to be formed.

This photoresist 22 is formed so as to cover the region where the storage gate is to be formed and other channel portions in the case of CMO5, and is patterned so that the regions which will be the source/drain regions are opened. At this time, the end of the photoresist 22 is on the selection gate 4.5, which is convenient for mask alignment.

(C) Next, as shown in FIG. 1C, impurities are introduced by a method such as ion implantation using the photoresist 22 and the selection gate 4.5 as a mask. By this ion implantation, impurities are introduced into impurity regions 12 and 13 which become source and drain regions in a so-called self-line. Note that the method of introducing impurities is not limited to the above-mentioned ion implantation, and other methods may be used.

(d) Next, as shown in m1ld, the impurity regions 12 and 13 are activated by annealing to form impurity regions that will become source and drain regions. At this time, the nitride film to be disposed later under the storage gate has not yet been formed, and therefore the nitride film is not adversely affected by the heat treatment for forming the source/drain regions.

(e) As shown in FIG. 1e, in order to form a storage gate having an MNO3 structure, a photoresist 23 is deposited in which the area between the selection gates 4 and 5 where the storage gate is to be formed is opened. . And photoresist 2 like this
After forming the pattern No. 3, the oxide film 21.20 is removed in the region between the pair of selection gates 4.5 where a storage gate is to be formed, and the semiconductor substrate 10 is exposed. Where the semiconductor substrate 10 is thus exposed, an extremely thin oxide film 3 is formed in which carrier tunneling occurs during writing and erasing.

(f) Next, as shown in Fig. 1 f, phorcyst 2
3 is removed, and a nitride film 2 is formed.

This nitride film 2 is formed on the extremely thin oxide film 3 in the region covering the storage gate and becomes a part of the MNO3 structure. Since this nitride film 2 is formed after forming the impurity regions 12.13 that will become the source/drain regions as described above, it is not affected by heat treatment such as annealing for activating the impurity regions 12.13. Therefore, no thermal distortion occurs.

(g) After the formation of the nitride film 2, a polycrystalline silicon layer 24 is formed as a polycrystalline semiconductor layer on the nitride film 2, as shown in FIG. 1g. For such a polycrystalline silicon layer 24, as shown in FIG. 1g, a so-called pure polysilicon layer containing no impurities is deposited, and impurities are introduced into the polycrystalline silicon layer by ion implantation. Another method involves forming a polycrystalline silicon layer and incorporating impurities using the CVD method.

In the method of incorporating impurities while forming a polycrystalline silicon layer, that is, the method of forming so-called DOPO3, a polycrystalline silicon layer containing impurities is formed by CVD, and the temperature for this formation is approximately 630°C. This is sufficiently lower than the conventional diffusion temperature of phosphorus, etc., which is 950°C to 1000°C. Therefore, even if the polycrystalline silicon layer formed on the nitride film 192 is subjected to heat treatment, the adverse effect on the nitride film is effectively prevented.

Furthermore, as shown in FIG. 1g, in the method of depositing a so-called pure polysilicon layer as the second polycrystalline silicon layer and then implanting ions, for example, B+ (
After ion implantation using dopants such as boron), P+ (phosphorus), As+ (arsenic), etc., the temperature is 800℃~900℃
The polycrystalline silicon layer is activated by annealing at a relatively low temperature. Since the temperature of this heat treatment is also sufficiently lower than that of the conventional heat treatment, it is possible to prevent an adverse effect on the nitride film existing under the heat treatment. Note that this ion implantation may be performed after the polycrystalline silicon layer is patterned into a predetermined storage gate. In addition, in the case of P channel,
The impurities to be introduced may be selectively used, such as using poron and arsenic or phosphorus in the case of an N channel.

(h) As described above, a polycrystalline semiconductor layer is formed on the nitride film 2, and a predetermined glabella insulating film 15, wiring layer 16, etc. are formed to form a three-gate structure as shown in Figure 1. An EEFROM having an MNO3 structure is completed.

Here, to briefly explain the operation of the semiconductor device manufactured based on the manufacturing method of this embodiment, first, when writing an information signal, a high voltage is supplied to a selected element, and a carrier ( Writing is performed by tunneling electrons through the oxide film 3 and capturing them at the interface with the nitride film 2, thereby causing a change in Vth (dark voltage). Furthermore, during erasing, holes are injected by a reverse electric field and the information signal is erased. When reading the information signal of such an element, its vthO
Reading becomes possible based on the difference.

In the semiconductor device according to this embodiment, the heat treatment for forming the impurity regions 12 and 13, which will become the source/drain regions, is performed before the formation of the nitride film 2. Therefore, the nitride film 2 is It is not affected by heat, and therefore no thermal strain can occur in the nitride film 2.

In addition, since annealing at approximately 900° C. or lower is used to form the polycrystalline semiconductor layer, the nitride film 2 is not adversely affected by heat, and carriers are gradually injected and retained as the number of readings increases. It is possible to prevent problems such as changes in stored memory contents, and to improve memory retention characteristics.

Furthermore, using the photoresist 22 serving as a mask layer and the pair of selection gates 4.5 described above, impurities are introduced to form impurity regions that will become source/drain regions in the self-line. Therefore, there are advantages such as the possibility of fine processing.

In the above embodiment, an example of an EEFROM having a 3-gate structure was described, but the present invention
Of course, the present invention can also be applied to other devices having an OS structure.

Further, it goes without saying that the pair of selection gates are not limited to both performing the same operation, and one selection gate may perform a different operation.

H0 Effects of the Invention In the semiconductor device manufacturing method of the present invention, a nitride film is not yet deposited during the heat treatment for forming the impurity region.

Therefore, the nitride film forming the MNO3 structure is not affected at all by the heat treatment. Therefore, it is possible to prevent characteristics such as memory retention function from deteriorating over time.

Further, impurities can be introduced to form an impurity region in the self-alignment line using the mask layer, which is convenient in terms of process and can improve the performance of the device.

Furthermore, thermal distortion and the like to the nitride film can be effectively prevented during heat treatment of the polycrystalline semiconductor layer.

[Brief explanation of the drawing]

Figures 1a to 1 are cross-sectional views for explaining the method of manufacturing a semiconductor device of the present invention, and Figure 2 shows Δvth (variation in dark value voltage) when hydrogen annealing and nitrogen annealing are performed. FIG. 2 is a characteristic diagram showing changes over time. 1...Storage gate 2...Nitride film 3...Oxide film 4.5...Selection gate 10...Semiconductor substrate 12.13...Impurity region Patent Applicant: Sony Corporation Agent Patent Attorney Kowa Mima Ei Tamura - Fig. 1 e Fig. 1 f Fig. 1 9 1st drawing hue/1V help (2 quantity (V) Core Pillar Sword Fig. 2

Claims (1)

[Scope of Claims] In a method for manufacturing a semiconductor device in which a gate insulating film below a storage gate electrode formed between a pair of selection gate electrodes is composed of an oxide film and a nitride film, the pair of selection gates are formed on a substrate. forming an electrode; forming a mask layer between the pair of selection gate electrodes; introducing an impurity into the base using the pair of selection gate electrodes and the mask layer as a mask; forming an impurity region using impurities introduced through heat treatment; forming an oxide film between the pair of selection gate electrodes; forming a nitride film on the oxide film; A method for manufacturing a semiconductor device, comprising the step of forming the gate electrode.