JPH1187537A - Manufacture of nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a nonvolatile semiconductor memory device which satisfies required device operation standards, such as high-speed operation, reduced drive voltage, etc., and furthermore, enables further improvement of the reliability by forming a gate insulating film with a smaller leakage current. SOLUTION: This manufacturing method of a nonvolatile semiconductor memory device consisting of a memory cell which has a p-type silicon substrate 1 and a floating gate formed on the substrate 1 with a gate insulating film therebetween includes a process in which impurity ions 32 are implanted into the p-type silicon substrate 1 and a process in which the gate insulating film is formed on the p-type silicon substrate and furthremore, includes a process in which the p-type silicon substrate 1 is heated to a temperature of not lower than 950 deg.C.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a non-volatile semiconductor memory device, which comprises a step of implanting impurities into a semiconductor substrate by an ion implantation technique and thereafter forming a tunnel insulating film on the semiconductor substrate. is there.

[0002]

2. Description of the Related Art Conventionally, an ion implantation technique has
It is an indispensable technique for LSI manufacturing, such as adjustment of the threshold voltage of an OS transistor, formation of a source and a drain, and formation of isolation. This is because, according to the ion implantation technique, impurity ions are accelerated by a high electric field and implanted into an arbitrary place, whereby an impurity profile as designed for a device can be accurately realized.

In the non-volatile semiconductor memory device, the ion implantation technique of ionizing atoms such as phosphorus (P) and arsenic (As) into a semiconductor substrate serving as a cell part and accelerating the atoms by a high electric field is used for the ion implantation technique. Since it is possible to easily control the impurity atom concentration and the impurity distribution in the depth direction from the substrate surface, it is an extremely important technique for controlling the threshold value of a transistor which is important for device operation.

On the other hand, this ion implantation technique injects high-energy ions into a semiconductor substrate, which causes crystal defects and contamination by metal atoms. In the current manufacturing process of a nonvolatile semiconductor memory device, ions such as As are implanted into a region where a tunnel oxide film is to be formed, the threshold value of a transistor (cell transistor) in a cell portion is adjusted, and the device is operated. I have. Therefore, at the time of forming the most important tunnel oxide film in the manufacturing process of the nonvolatile semiconductor memory device, ion implantation is performed on the region where the tunnel oxide film is formed,
At present, crystal defects and contamination occur in this region.

[0005]

However, the crystal defects and contamination brought to the semiconductor substrate in this manner tend to be taken into the tunnel oxide film as they are, especially when the process temperature is reduced in the future.

[0006] Crystal defects and contamination introduced into the tunnel oxide film impair the network of the silicon oxide film (SiO 2). Therefore, when a writing or erasing operation stress is applied to such a gate insulating film, a leak current of the gate insulating film is generated. ,
In particular, the leakage current in a low electric field increases. This is a fatal problem for the nonvolatile semiconductor memory device.

On the other hand, if ions of phosphorus or arsenic are not implanted into the region (cell region) where the tunnel oxide film is formed, the threshold voltage of the cell transistor increases. This is an extremely large negative factor in terms of speeding up device operation.

Therefore, it is extremely important to form a gate oxide film having a small leakage current while satisfying a desired device operation standard by performing ion implantation into a region where a tunnel oxide film is formed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has been made in view of the above circumstances. A gate which can satisfy a desired device operation standard such as high speed operation of a device and low drive voltage and has a small leakage current is provided. It is an object of the present invention to provide a method for manufacturing a nonvolatile semiconductor memory device in which reliability can be further improved by forming an insulating film.

[0010]

According to a first aspect of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory device, comprising the steps of: starting from a memory cell having a floating gate formed on a semiconductor substrate via a tunnel insulating film; A method of implanting an impurity into the tunnel insulating film forming region of the semiconductor substrate, and a step of forming the tunnel insulating film on the semiconductor substrate into which the impurity has been implanted. And a step of heating the semiconductor substrate to 950 ° C. or higher between the step of implanting the impurities and the step of forming the tunnel insulating film.

According to a second aspect of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory device comprising a memory cell having a floating gate formed on a semiconductor substrate via a tunnel insulating film. Implanting an impurity into the tunnel insulating film forming region of the semiconductor substrate, and forming the tunnel insulating film in the semiconductor substrate into which the impurity has been implanted, wherein the implanting the impurity and the tunnel Between the step of forming an insulating film,
A step of thermally oxidizing the semiconductor substrate at a temperature of 950 ° C. or more.

According to a third aspect of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory device comprising a memory cell having a floating gate formed on a semiconductor substrate via a tunnel insulating film. Implanting an impurity into the tunnel insulating film forming region of the semiconductor substrate, forming a gate insulating film different from the tunnel insulating film on the semiconductor substrate into which the impurity has been implanted, and implanting the impurity. Forming a tunnel insulating film of the memory cell on a semiconductor substrate, wherein after the step of forming the gate insulating film and before the step of forming the tunnel insulating film of the memory cell, the semiconductor substrate is removed by 950. It is characterized by having a step of heating to a temperature of not less than ° C.

According to a fourth aspect of the present invention, in the method of manufacturing a nonvolatile semiconductor memory device according to any one of the first to third aspects, the step of implanting the impurity comprises the step of: Is set so that the crystal defect density on the surface of the semiconductor substrate immediately after the implantation of Si is 1.4 × 10 ²⁰ / cm ³ or more.

According to a fifth aspect of the present invention, in the method of manufacturing a nonvolatile semiconductor memory device according to any one of the first to fourth aspects, the step of implanting the impurity comprises the step of: Is set to 1.2 × 10 ¹² / cm ² or more when the impurity is boron or phosphorus, and the dose is set to 2 × 10 ¹³ / cm ² or more when the impurity is boron or phosphorus. I do.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described below with reference to the drawings. In the following embodiment, a NAND type EEPROM of a nonvolatile semiconductor memory device will be described as an example.

FIG. 1 shows a NAND type EEPROM formed by a manufacturing method according to first to fourth embodiments described later.
FIG. 3 is a diagram showing a cross-sectional structure of FIG. As shown in FIG. 1, a plurality of memory cell transistors (hereinafter, memory cell transistors) 2 and two memory cells sandwiching the transistors 2 are arranged in a region surrounded by an element isolation region (not shown) on a p-type silicon substrate 1. A NAND cell including a selection transistor (hereinafter, a selection transistor) 3 is formed as follows.

On the p-type silicon substrate 1, a floating gate 6 made of a first polycrystalline silicon film is formed via a first gate insulating film 4 to be a tunnel insulating film. On this floating gate 6, a control gate 10 made of a second polycrystalline silicon film is formed via a second gate insulating film 8. Further, an N ⁺ layer 12 is formed on the drain and source portions of the memory cell transistor 2 and the select transistor 3.

An insulating film 14 is formed on the entire surface of the p-type silicon substrate 1.
A contact hole leading to the source at the end of the ND cell is provided. On the insulating film 14, a wiring 16 made of aluminum (Al) or the like connected to the drain portion or the source portion via the contact hole is provided. In this embodiment, a p-type silicon substrate is used. However, the present invention is not limited to this, and a p-type well may be formed on an n-type silicon substrate.

Next, such a NAND type EEPROM will be described.
A general manufacturing method of the memory cell transistor 2 will be described. 2 (a), (b) to FIG. 4 (a),
FIG. 4B is a diagram showing a step of manufacturing the memory cell transistor 2 of the NAND type EEPROM.

As shown in FIG. 2A, a p-type silicon substrate 1 (or a p-type well formed on an n-type silicon substrate)
A dummy insulating film 20 having a predetermined film thickness of about 10 to several tens nm is formed by thermal oxidation in a channel portion forming region of the memory cell transistor on the surface. Then, a desired conductivity type impurity ion 22 (for example, arsenic ion) is injected into the p-type silicon substrate 1 via the dummy insulating film 20 by a predetermined acceleration voltage, for example, 120 keV, and a predetermined dose amount by an ion implantation method. For example, implantation is performed at 1.2 × 10 ¹² atoms / cm ² or less.

Thereafter, as shown in FIG. 2B, the dummy insulating film 20 is peeled off. Then, as shown in FIG. 3A, a first gate insulating film 4 of about 10 nm is formed by a thermal oxidation method. At this time, the impurity ions 22 implanted in the above-described steps are activated on the surface of the p-type silicon substrate 1 by a heat step for forming the first gate insulating film 4 to form an activated impurity layer 24. I do.

Further, as shown in FIG. 3B, a first polysilicon film 6 is formed on the first gate insulating film 4, and a silicon oxide film is formed on the first polysilicon film 6. A second gate insulating film 8 having a thickness of about 25 nm is formed. Although not shown here, the first polycrystalline silicon film 6 is provided with a slit-shaped opening corresponding to the element isolation region after deposition.

Further, on the second gate insulating film 8,
A second polycrystalline silicon film 10 is formed. A photoresist is applied on the second polycrystalline silicon film 10, and is exposed and drawn to form a resist pattern 26.

Subsequently, as shown in FIG. 4A, using the resist pattern 26 as an etching mask,
The control gate 10 and the floating gate 6 are formed by sequentially etching the second polysilicon film 10, the second gate insulating film 8, and the first polysilicon 6 by reactive ion etching (RIE).

Thereafter, as shown in FIG. 4B, after removing the resist pattern 26, a drain and source region (N ⁺ layer) 12 is formed by ion implantation. Thereafter, the insulating film 14, the wiring 16, and the like are formed according to a normal process. As described above, the NAND type E of the first embodiment
The EPROM memory cell transistor is completed.

Here, the relationship between the number of charge retention failure bits (Fail bit number) in the nonvolatile semiconductor memory device obtained by such a manufacturing method and the implantation dose (Dose amount) at the time of ion implantation into the channel portion formation region. FIG. 5 shows the relationship. According to FIG. 5, when the impurity ion is arsenic,
It can be seen that when the implantation dose is suppressed to 1.2 × 10 ¹² atoms / cm ² or less, the number of defective memory cells rapidly decreases.

Thus, the impurity ions (arsenic ions) 2
2 is a predetermined amount of 1.2 × 10 ¹² atoms / cm.
^By setting it to ² or less, it can be said that the leakage current can be suppressed and the data retention characteristics can be improved. The predetermined amount of the dose is p after removal of the dummy insulating film 20.
Crystal density on the surface of the silicon substrate 1 is 1.4
× 10 ²⁰ / cm ³ or an impurity atom density of 1.3 × 1
The amount is 0 ¹⁶ atoms / cm ³ . That is, when the dummy insulating film 20 is a silicon oxide film having a thickness of 25 nm, the acceleration energy of the impurity ions 22 is 120 keV, and the impurity ions 22 are arsenic, the implantation dose is 1.2 × 10 ¹² atoms / cm ^2. By setting as follows, the leakage current can be suppressed and the data retention characteristics can be improved.

Under the same conditions except that the impurity ions are boron or phosphorus, the implantation dose is 2 × 10 ¹³ atom
By setting the ratio to s / cm ² or less, it is possible to suppress the leak current and improve the data retention characteristics.

In this case, the dummy insulating film 20 is a silicon oxide film having a thickness of 25 nm, and the implantation dose is set to 1.2 ×
FIG. 6 shows the relationship between the acceleration energy of the impurity ions 22 and the density of crystal defects generated on the surface of the p-type silicon substrate 1 when the impurity ions 22 are arsenic at 10 ¹² atoms / cm ² . FIG. 6 shows that increasing the acceleration energy monotonously reduces the density of crystal defects generated on the surface of the p-type silicon substrate 1.

Thus, it can be said that by setting the acceleration energy of the impurity ions 22 to a predetermined value or more, it is possible to suppress the leak current and improve the data retention characteristics. The predetermined value of the acceleration energy is such that the crystal defect density is 1.4 × 10 ²⁰ / cm ³ or the impurity atom density is 1.3 × 10 ¹⁶ atoms on the surface of the p-type silicon substrate 1 after the peeling of the dummy insulating film 20. / Cm ³ . That is, the dummy insulating film 20 has a thickness of 25 nm.
Silicon oxide film, implantation dose is 1.2 × 10 ¹² atom
When s / cm ² and the impurity ions 22 are arsenic, by setting the acceleration energy of the impurity ions 22 to 120 keV or more, the leakage current can be suppressed and the data retention characteristics can be improved.

Here, the acceleration energy of the impurity ions 22 is 120 keV and the implantation dose is 1.2 × 1.
FIG. 7 shows the relationship between the thickness of the dummy insulating film 20 made of a silicon oxide film and the density of crystal defects generated on the surface of the p-type silicon substrate 1 when 0 ¹² atoms / cm ² and the impurity ions 22 are arsenic ions. Show. FIG. 7 shows that when the thickness of the dummy insulating film 20 is reduced, the density of crystal defects generated on the surface of the p-type silicon substrate 1 decreases monotonously.

Thus, it can be said that by setting the thickness of the dummy insulating film 20 to a predetermined value or less, it is possible to suppress the leak current and improve the data retention characteristics. The predetermined value of the film thickness is such that the crystal defect density on the surface of the p-type silicon substrate 1 after the removal of the dummy insulating film 20 is 1.
4 × 10 ²⁰ / cm ³ , or an impurity atom density of 1.3 ×
The value is 10 ¹⁶ atoms / cm ³ . That is, the impurity ions 22 are arsenic, the acceleration energy of the impurity ions 22 is 120 keV, and the implantation dose is 1.2 × 1.
When 0 ¹² atoms / cm ² , the dummy insulating film 20
By setting the film thickness to 25 nm or less, the leakage current can be suppressed and the data retention characteristics can be improved.

By the way, for example, due to restrictions on the manufacturing process required for adjusting the threshold value of the memory cell transistor, the conditions for ion implantation into the channel portion forming region deviate from the desired range described above. In some cases, the crystal defect density immediately after ion implantation cannot be reduced to 1.4 × 10 ²⁰ / cm ³ or less. Therefore, in the present invention, in such a case, by the manufacturing method described in the following first to fourth embodiments,
Manufacturing of a semiconductor memory device is performed.

First, the NAND-type EE of the first embodiment
A method for manufacturing the memory cell transistor 2 in the PROM will be described. 8 (a), (b) to FIG.
7A and 7B are diagrams showing a manufacturing process of the memory cell transistor 2 of the NAND type EEPROM.

As shown in FIG. 8A, a p-type silicon substrate 1 (or a p-type well formed on an n-type silicon substrate)
A dummy insulating film 30 having a predetermined film thickness of about 10 to several tens nm is formed by thermal oxidation in a channel formation region of the memory cell transistor on the surface. Then, impurity ions 32 (for example, arsenic ions) accelerated to high energy are implanted into the p-type silicon substrate 1 through the dummy insulating film 30 by an ion implantation method.

Here, the implantation of the impurity ions 32 is as follows.
The purpose of the present invention is to set the threshold voltage of the memory cell transistor 2 to a desired value, and the implantation dose in the ion implantation method is 1 × when the impurity ions 32 are arsenic.
This is performed in the range of 10 ¹⁰ atoms / cm ^{2 to} 5 × 10 ¹³ atoms / cm ² . When the impurity ions 32 are boron or phosphorus, 1 × 10 ¹⁰ atoms / cm ² to 1 × 10 ¹⁴ atoms
It is performed in the range of s / cm ² .

Subsequently, as shown in FIG. 8B, after the dummy insulating film 30 is peeled off, annealing is performed at a predetermined temperature, for example, 950 ° C. in a non-oxidizing atmosphere such as nitrogen gas. This annealing temperature is desirably 950 ° C. or higher. At this time, the impurity ions 32 implanted in the above-described step are activated on the surface of the p-type silicon substrate 1 by this annealing to form an activated impurity layer 34.

Thereafter, as shown in FIG. 9A, a first gate insulating film 4 having a thickness of about 10 nm is formed by a thermal oxidation method. Further, as shown in FIG. 9B, a first polycrystalline silicon film 6 is formed on the first gate insulating film 4, and is formed on the first polycrystalline silicon film 6 in terms of a silicon oxide film. A second gate insulating film 8 of about 25 nm is formed. Although not shown here, the first polycrystalline silicon film 6 is provided with a slit-shaped opening corresponding to the element isolation region after deposition.

Subsequently, a second polycrystalline silicon film 10 is formed on the second gate insulating film 8, and a photoresist is applied on the second polycrystalline silicon film 10, and this is exposed and drawn. Thus, a resist pattern 26 is formed.

Subsequently, as shown in FIG. 10A, the second polycrystalline silicon film 10 and the second gate insulating film are formed by reactive ion etching (RIE) using the resist pattern 26 as an etching mask. 8 and the first
Is sequentially etched to form the control gate 1
0 and the floating gate 6 are formed.

Thereafter, as shown in FIG. 10B, after removing the resist pattern 26, the drain and source regions (N ⁺ layers) 12 are formed by ion implantation. Thereafter, the insulating film 14, the wiring 16, and the like are formed according to a normal process. As described above, the memory cell transistor of the NAND type EEPROM of the first embodiment is completed.

As described above, in the first embodiment, annealing is performed at a temperature of 950 ° C. or more after the impurity ions 32 are implanted, so that the impurity ions 32 are implanted into the p-type silicon substrate 1. The crystal defects recovered recover, and the crystal defect density decreases. As a result, the occurrence of a leak current can be suppressed, and the data retention characteristics can be improved.

Next, the NAND type EE according to the second embodiment will be described.
A method for manufacturing the memory cell transistor 2 in the PROM will be described. 11 (a), (b), FIG.
(A), (b), (c), FIGS. 13 (a), (b) show the memory cell transistor 2 of the NAND type EEPROM.
It is a figure which shows the manufacturing process of.

As shown in FIG. 11A, a predetermined film is formed by a thermal oxidation method on a channel forming region of a memory cell transistor on the surface of a p-type silicon substrate 1 (or a p-type well formed on an n-type silicon substrate). A dummy insulating film 40 having a thickness of about 10 to several tens nm is formed. Then, impurity ions 42 (for example, arsenic ions) accelerated to a high energy by an ion implantation method are p-poured through the dummy insulating film 40.
Is implanted into the silicon substrate 1.

Further, as shown in FIG. 11B, after the dummy insulating film 40 is peeled off, a predetermined temperature, for example, 9 ° C.
An insulating film 44 having a thickness of about several tens nm is formed by a thermal oxidation method at 50 ° C. The temperature at the time of forming the insulating film 44 is desirably 950 ° C. or higher. The insulating film 4
Reference numeral 4 may be a film that functions as a gate insulating film in a peripheral circuit, or may be a film for simply removing dirt on the substrate surface. At this time, the impurity ions 42 implanted in the above-described step are activated on the surface of the p-type silicon substrate 1 by the high-temperature oxidizing atmosphere in the thermal oxidation to form an activated impurity layer 46.

Thereafter, as shown in FIG. 12A, the insulating film 44 is peeled off only at the portion of the memory cell transistor 2.
As shown in FIG. 12B, a film thickness of 10 n was formed by a thermal oxidation method.
The first gate insulating film 4 of about m is formed. Further, as shown in FIG. 12C, a first polycrystalline silicon film 6 is formed on the first gate insulating film 4, and is formed on the first polycrystalline silicon film 6 in terms of a silicon oxide film. A second gate insulating film 8 of about 25 nm is formed. Although not shown here, the first polycrystalline silicon film 6 is provided with a slit-shaped opening corresponding to the element isolation region after deposition.

Subsequently, a second polycrystalline silicon film 10 is formed on the second gate insulating film 8, and a photoresist is further applied on the second polycrystalline silicon film 10, and this is exposed and drawn. Thus, a resist pattern 26 is formed.

Subsequently, as shown in FIG. 13A, the second polycrystalline silicon film 10 and the second gate insulating film are formed by reactive ion etching (RIE) using the resist pattern 26 as an etching mask. 8 and the first
Is sequentially etched to form the control gate 1
0 and the floating gate 6 are formed.

Thereafter, as shown in FIG. 13B, after removing the resist pattern 26, the drain and source regions (N ⁺ layers) 12 are formed by ion implantation. Thereafter, the insulating film 14, the wiring 16, and the like are formed according to a normal process. As described above, the memory cell transistor of the NAND type EEPROM according to the second embodiment is completed.

As described above, in the second embodiment, after the impurity ions 42 are implanted, thermal oxidation at 950 ° C. or higher (holding in a high-temperature oxidizing atmosphere) is performed to form a gate insulating film for peripheral circuits. 2), the crystal defects generated in the p-type silicon substrate 1 due to the implantation of the impurity ions 42 are recovered, and the crystal defect density is reduced. As a result, the occurrence of a leak current can be suppressed, and the data retention characteristics can be improved.

Next, the NAND type EE of the third embodiment will be described.
A method for manufacturing the memory cell transistor 2 in the PROM will be described. 11 (a), (b), FIG.
(A), (b), (c), FIGS. 13 (a), (b) show the memory cell transistor 2 of the NAND type EEPROM.
It is a figure which shows the manufacturing process of.

As shown in FIG. 11A, a predetermined film is formed on the surface of the p-type silicon substrate 1 (or the p-type well formed on the n-type silicon substrate) in the channel forming region of the memory cell transistor by a thermal oxidation method. A dummy insulating film 40 having a thickness of about 10 to several tens nm is formed. Then, impurity ions 42 (for example, arsenic ions) accelerated to a high energy by an ion implantation method are p-poured through the dummy insulating film 40.
Is implanted into the silicon substrate 1.

Further, as shown in FIG. 11B, after the dummy insulating film 40 is peeled off, the p-type silicon substrate 1 is heated to 750 ° C.-8
By heating in an oxidizing atmosphere at 50 ° C., an insulating film 44 having a thickness of about several tens nm is formed. Thereafter, annealing is performed at a predetermined temperature, for example, 950 ° C. in a non-oxidizing atmosphere such as nitrogen gas. This annealing temperature is desirably 950 ° C. or higher. At this time, the impurity ions 42 implanted in the above-described process are converted into the p-type silicon substrate 1 by this annealing.
Activated on the surface to form an activated impurity layer 46.

Thereafter, as shown in FIG. 12A, the insulating film 44 is peeled off only at the memory cell transistor 2 portion.
As shown in FIG. 12B, a film thickness of 10 n was formed by a thermal oxidation method.
The first gate insulating film 4 of about m is formed. Further, as shown in FIG. 12C, a first polycrystalline silicon film 6 is formed on the first gate insulating film 4, and is formed on the first polycrystalline silicon film 6 in terms of a silicon oxide film. A second gate insulating film 8 of about 25 nm is formed. Although not shown here, the first polycrystalline silicon film 6 is provided with a slit-shaped opening corresponding to the element isolation region after deposition.

Subsequently, a second polycrystalline silicon film 10 is formed on the second gate insulating film 8, and a photoresist is applied on the second polycrystalline silicon film 10, and this is exposed and drawn. Thus, a resist pattern 26 is formed.

Subsequently, as shown in FIG. 13A, the second polycrystalline silicon film 10 and the second gate insulating film are formed by reactive ion etching (RIE) using the resist pattern 26 as an etching mask. 8 and the first
Is sequentially etched to form the control gate 1
0 and the floating gate 6 are formed.

Thereafter, as shown in FIG. 13B, after removing the resist pattern 26, the drain and source regions (N ⁺ layers) 12 are formed by ion implantation. Thereafter, the insulating film 14, the wiring 16, and the like are formed according to a normal process. As described above, the memory cell transistor of the NAND type EEPROM according to the third embodiment is completed.

As described above, according to the third embodiment, after the impurity ions 42 are implanted, the temperature of 750.degree.
Thermal oxidation was performed in an oxidizing atmosphere at 50 ° C., and annealing was performed at a temperature of 950 ° C. or more in a non-oxidizing atmosphere such as nitrogen gas, so that impurity ions 42 were implanted into the p-type silicon substrate 1. The crystal defects recover and the crystal defect density decreases. As a result, the occurrence of a leak current can be suppressed, and the data retention characteristics can be improved.

Next, the NAND type EE of the fourth embodiment will be described.
A method for manufacturing the memory cell transistor 2 and the selection transistor 3 in the PROM will be described. FIG.
(A), (b), FIG. 15 (a), (b), (c), FIG.
6 (a) and 6 (b) are diagrams showing a manufacturing process of the memory cell transistor 2 and the selection transistor 3 of the NAND type EEPROM. In the figure, the left side shows the memory cell transistor 2 and the right side shows the selection transistor 3.

As shown in FIG. 14A, a predetermined film is formed by a thermal oxidation method on the channel forming region of the memory cell transistor on the surface of the p-type silicon substrate 1 (or the p-type well formed on the n-type silicon substrate). A dummy insulating film 50 having a thickness of about 10 to several tens nm is formed. Then, the impurity ions 52 (for example, arsenic ions) accelerated to a high energy are ion-implanted through the dummy insulating film 50 into p-type.
Is implanted into the silicon substrate 1.

Further, as shown in FIG. 14B, after the dummy insulating film 50 is peeled off, a step 7 is formed to form a gate insulating film (select gate insulating film) of the select transistor.
By a thermal oxidation method at 50 ° C to 850 ° C or other methods,
An insulating film 54 having a thickness of about several tens nm is formed. Thereafter, annealing is performed at a predetermined temperature, for example, 950 ° C. in a non-oxidizing atmosphere such as nitrogen gas. The annealing temperature is 9
It is desirable that the temperature is 50 ° C. or higher. At this time, the impurity ions 52 implanted in the above-described step are activated on the surface of the p-type silicon substrate 1 by this annealing to form an activated impurity layer 56.

Thereafter, as shown in FIG. 15A, the insulating film 54 is peeled off only at the memory cell transistor 2 portion.
As shown in FIG. 15B, a film thickness of 10 n
The first gate insulating film 4 of about m is formed. Further, as shown in FIG. 15C, in the memory cell transistor 2 on the left side, a first polycrystalline silicon film 6 is formed on the first gate insulating film 4, and the first polycrystalline silicon film 6 is formed. A second gate insulating film 8 having a thickness of about 25 nm in terms of a silicon oxide film is formed on the silicon film 6. Although not shown here, the first polycrystalline silicon film 6 is provided with a slit-shaped opening corresponding to the element isolation region after deposition.

Subsequently, a second polycrystalline silicon film 10 is formed on the second gate insulating film 8, and a photoresist is applied on the second polycrystalline silicon film 10, and this is exposed and drawn. Thus, a resist pattern 26 is formed.

On the other hand, in the portion of the selection transistor 3 on the right side, as shown in FIG. 15C, a first polysilicon film 6 is formed on the insulating film 54, and the first polysilicon film 6 is formed. A second gate insulating film 8 having a thickness of about 25 nm in terms of a silicon oxide film is formed on 6. Subsequently, a second polycrystalline silicon film 10 is formed on the second gate insulating film 8, a photoresist is further applied on the second polycrystalline silicon film 10, and this is exposed and drawn to form a resist. The pattern 26 is formed.

Subsequently, as shown in FIG. 16A, the second polycrystalline silicon film 10 and the second gate insulating film are formed by reactive ion etching (RIE) using the resist pattern 26 as an etching mask. 8 and the first
Is sequentially etched to form the control gate 1
0 and the floating gate 6 are formed.

Thereafter, as shown in FIG. 16B, after removing the resist pattern 26, the drain and source regions (N ⁺ layers) 12 are formed by ion implantation. FIG.
18 is a sectional view taken along a direction perpendicular to the sectional direction shown in FIGS. 14 to 16, that is, a sectional view taken along AA in FIG. 18. 14 to 16 correspond to FIG.
6 is a cross-sectional view along BB in FIG.

As shown in FIG. 17, after the manufacturing process shown in FIG. 16B, an insulating film 14 is formed on the entire surface of the p-type silicon substrate 1, and the right select transistor 3 shown in FIG. In this portion, a contact hole for connecting the floating gate (first polycrystalline silicon film) 6 and the control gate (second polycrystalline silicon film) 10 is formed in the insulating film 14. Then, aluminum (Al) is formed on the insulating film 14.
A wiring 16 composed of the same is provided, the floating gate 6 and the control gate 10 are connected to the same potential by the wiring 16, and the selection transistor 3 is formed between the element isolation regions 58. Thereafter, the production is performed according to the usual process. Thus, the NAND type EEPROM according to the fourth embodiment is completed.

As described above, in the fourth embodiment, after the impurity ions 52 are implanted, the temperature is set to 750 ° C. to 8 ° C.
Thermal oxidation was performed in an oxidizing atmosphere at 50 ° C., and annealing was performed at a temperature of 950 ° C. or more in a non-oxidizing atmosphere such as nitrogen gas, so that impurity ions 52 were implanted into the p-type silicon substrate 1. The crystal defects recover and the crystal defect density decreases. As a result, the occurrence of a leak current can be suppressed, and the data retention characteristics can be improved.

According to the above-described embodiment, a nonvolatile semiconductor memory device capable of reducing a leakage current of a gate insulating film of a memory cell in a low electric field without sacrificing a driving current or a writing speed of the memory cell. Can be realized.

[0070]

As described above, according to the present invention, it is possible to satisfy a desired device operation standard such as high-speed device operation and low drive voltage, and to provide a gate insulating film with a small leakage current. It is possible to provide a method for manufacturing a nonvolatile semiconductor memory device which can be formed to further improve reliability.

[Brief description of the drawings]

FIG. 1 is a diagram showing a sectional structure of a NAND type EEPROM formed by a manufacturing method according to first to fourth embodiments of the present invention.

FIG. 2 is a diagram showing a manufacturing process of a memory cell transistor of a NAND type EEPROM.

FIG. 3 is a diagram showing a manufacturing process of a memory cell transistor of a NAND type EEPROM.

FIG. 4 is a diagram showing a manufacturing process of a memory cell transistor of a NAND type EEPROM.

FIG. 5 shows the number of defective charge retention bits (Fai) in the nonvolatile semiconductor memory device obtained by the manufacturing method shown in FIGS.
FIG. 6 is a diagram showing a relationship between an L bit number) and an implantation dose (Dose amount).

FIG. 6 is a diagram showing the relationship between the acceleration energy of impurity ions and the density of crystal defects generated on the surface of a p-type silicon substrate in the nonvolatile semiconductor memory device.

FIG. 7 is a diagram showing the relationship between the thickness of a dummy insulating film made of a silicon oxide film and the density of crystal defects generated on the surface of a p-type silicon substrate in the nonvolatile semiconductor memory device.

FIG. 8 is a diagram illustrating a manufacturing process of the memory cell transistor of the NAND type EEPROM according to the first embodiment;

FIG. 9 is a diagram illustrating a manufacturing process of the memory cell transistor of the NAND type EEPROM according to the first embodiment;

FIG. 10 is a NAND type EEPROM according to the first embodiment;
FIG. 14 is a diagram showing a manufacturing process of the memory cell transistor of FIG.

FIG. 11 shows a NAND-type EEP according to the second and third embodiments.
FIG. 7 is a diagram illustrating a manufacturing process of the memory cell transistor of the ROM.

FIG. 12 shows a NAND-type EEP according to the second and third embodiments.
FIG. 7 is a diagram illustrating a manufacturing process of the memory cell transistor of the ROM.

FIG. 13 shows a NAND-type EEP according to the second and third embodiments.
FIG. 7 is a diagram illustrating a manufacturing process of the memory cell transistor of the ROM.

FIG. 14 is a NAND EEPROM according to a fourth embodiment;
FIG. 7 is a diagram showing a manufacturing process of the memory cell transistor and the selection transistor of FIG.

FIG. 15 shows a NAND type EEPROM according to a fourth embodiment;
FIG. 7 is a diagram showing a manufacturing process of the memory cell transistor and the selection transistor of FIG.

FIG. 16 shows a NAND type EEPROM according to a fourth embodiment;
FIG. 7 is a diagram showing a manufacturing process of the memory cell transistor and the selection transistor of FIG.

FIG. 17 shows a NAND type EEPROM according to a fourth embodiment.
FIG. 14 is a view showing a manufacturing process of the selection transistor of FIG.
FIG. 17 is a cross-sectional view from a direction orthogonal to the cross-sectional direction shown in FIG.

FIG. 18 is a view showing a cross section of FIG. 17;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... p-type silicon substrate 2 ... Transistor for memory cells (hereinafter memory cell transistors) 3 ... Transistor for selecting memory cells (hereinafter select transistors) 4 ... First gate insulating film 6 ... Floating gate (first polycrystalline 8 ... second gate insulating film 10 ... control gate (second polycrystalline silicon film) 12 ... N ⁺ layer 14 ... insulating film 16 ... wiring 20 ... dummy insulating film 22 ... impurity ion 24 ... activating impurity Layer 26 resist pattern 30 dummy insulating film 32 impurity ions 34 activated impurity layer 40 dummy insulating film 42 impurity ions 44 insulating film 46 activated impurity layer 50 dummy insulating film 52 impurity ions 54 Insulating film 56 Activated impurity layer 58 Element isolation region

Claims (5)

[Claims] 1. A method for manufacturing a nonvolatile semiconductor memory device comprising a memory cell in which a floating gate is formed on a semiconductor substrate via a tunnel insulating film, comprising: a step of implanting an impurity into the tunnel insulating film forming region of the semiconductor substrate; Forming the tunnel insulating film on the semiconductor substrate into which the impurity has been implanted, wherein the semiconductor substrate is heated to 950 ° C. or higher between the step of implanting the impurity and the step of forming the tunnel insulating film. A method of manufacturing a nonvolatile semiconductor memory device, comprising the steps of: 2. A method of manufacturing a nonvolatile semiconductor memory device comprising a memory cell in which a floating gate is formed on a semiconductor substrate via a tunnel insulating film, comprising: implanting an impurity into the tunnel insulating film forming region of the semiconductor substrate; Forming the tunnel insulating film on the semiconductor substrate into which the impurity has been implanted, wherein the semiconductor substrate is heated to 950 ° C. or higher between the step of implanting the impurity and the step of forming the tunnel insulating film. A method for manufacturing a nonvolatile semiconductor memory device, comprising a step of thermally oxidizing at a temperature. 3. A method of manufacturing a nonvolatile semiconductor memory device comprising a memory cell in which a floating gate is formed on a semiconductor substrate via a tunnel insulating film, wherein a step of implanting an impurity into the tunnel insulating film forming region of the semiconductor substrate is provided. Forming a gate insulating film different from the tunnel insulating film on the semiconductor substrate into which the impurity has been implanted; and forming a tunnel insulating film of the memory cell on the semiconductor substrate into which the impurity has been implanted. A step of heating the semiconductor substrate to 950 ° C. or higher after the step of forming the gate insulating film and before the step of forming a tunnel insulating film of the memory cell. Manufacturing method. 4. The method according to claim 1, wherein the step of implanting the impurities is performed under a condition that a crystal defect density on the surface of the semiconductor substrate immediately after the implantation of the impurities is 1.4 × 10 ²⁰ / cm ³ or more. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1. 5. The step of implanting an impurity, wherein when the impurity is arsenic, the dose is 1.2 × 10 ¹² / cm.
² above, when the impurity is boron or phosphorus, non according to any one of claims 1 to 4, characterized in that the dose is set to 2 × 10 ¹³ / cm ² or more Of manufacturing a nonvolatile semiconductor memory device.