JPS62290216A - Auto-zero device - Google Patents

Abstract

PURPOSE:To prevent an S/N from deteriorating even if an analog signal changes by detecting the number of synchronizing signals that have polarity bits with the same polarity through the use of a counter circuit set by a polarity bit change detection circuit and controlling an auto-zero circuit in a high speed mode if said number exceeds a set number. CONSTITUTION:If the polarity bit inputted to the change detection circuit 5 is fixed at a positive, the counter circuit 4 advances counting with the aid of the synchronizing signal, and after it counts 64, it outputs a control signal 7 to the auto-zero circuit 6. It becomes the high speed mode due to the control signal 7. In the high speed mode, the auto-zero circuit 6 sets an integration amount per time greater than that in a low speed mode of 5-500 times, for example. Consequently, in the output voltage of the auto-zero circuit its changing amount is 5-500 times. As a result, time required for compensating an off-set voltage caused by unbalanced positive and negative integration amounts is shortened, whereby the deterioration of the S/N, which is caused by a remaining off-set voltage can be restored quickly.

Description

Detailed Description of the Invention λ Detailed Description of the Invention [Field of Oncology Application] The present invention relates to an auto-zero device for compensating the offset voltage of an ADf detector, and in particular for converting an analog signal into a digital signal. The present invention also relates to an auto-zero device that uses the count number of the polarity bit of the digital signal to provide two types of auto-zero operation: a high-speed mode and a low-speed mode.

[Conventional technology]

In an AL converter that converts an analog signal to a digital signal, when configuring a successive approximation type AD converter using a local DA converter, a comparator, and a successive approximation register, D
DC offset voltage of A converter and offset of comparator
Pressure is generated.゛In addition, a band pass filter (B
PF) and low pass filters (LPF) are used to prevent aliasing noise. Since the offset voltage generated by this filter is also equivalent to the offset voltage of the AD converter, it is necessary to prevent the signal-to-noise ratio from deteriorating due to an increase in the offset voltage.

As a technique conventionally used for this method, it has been considered to compensate for the offset voltage of the rainbow system in the auto-zero device shown in Fig. 2. In FIG. 2, an analog signal is inputted from an analog signal 21 to an ADK transmitter 23 via a filter 22 for preventing aliasing noise. The AD converter performs successive approximation to convert an analog signal into a digital signal.

When performing this ADK check, by connecting the inertia bit signal gold auto-zero time w67 of the AD converter and integrating the polarity bit, the offset voltage added to the analog input 21 and the local DA converter and comparator The offset voltage can be compensated by this auto-zero device.

[Problem that the invention seeks to solve]

The conventional auto-zero device described above integrates the polarity bit to compensate for offset voltages of local DA converters, comparators, and band-limiting filters.

In order to compensate, a problem arises if the ratio of the relative integral amount of the positive polarity bit integral and the negative polarity bit integral is different.

The integrated current value when the somatic pit is positive is ρ, and the integrated current value when the traumatic pit is negative is ρ. At this time, the operating point A that is stabilized by the operation of the auto-zero circuit can be expressed as the full width of the human analog signal V□. VX is the amplitude of the human-powered analog signal, and α is the ratio of the positive integrated current value to the negative integrated current value. α=l I, I/l IN + ...
...It can be expressed as (2).

Equation (1) shows that the stable operating point A changes depending on the amplitude of the input analog signal. In other words, the stable operating point changes depending on the amplitude V□ of the input analog signal), and for low-level input signals it operates as an auto-zero circuit that compensates for the offset voltage of the system. When the amplitude V of the input analog signal increases, an offset voltage is generated according to the ratio α between the positive integral current value I and the negative integral current value IIN+.

The offset voltage generated by the auto-zero circuit caused by the ratio α of the positive and negative integrated current values is the residual compensation of the auto-zero device when the analog signal changes from a large signal to a small signal, and the offset voltage is generated by the input signal. This results in a correspondingly large offset voltage. This caused a problem in that the signal to quantization noise ratio deteriorated due to the large offset voltage.

In this case, when α = 1.10 and v, and = iv, A is expressed by formula (1)
If calculated from 74.7 mV, some countermeasures are required.

[Means for solving problems]

The auto-zero device of the present invention integrates the polarity bit of an input signal to compensate for the offset voltage of the AD converter, and includes a counter circuit for counting the synchronization signal of the AD converter and a counter circuit for counting the change in the polarity bit. It has a change detection circuit for detection and an auto-zero circuit for integrating the polarity bit, and when the polarity bit changes due to the output signal of the change detection circuit, the counter circuit is reset just in case.
When the polarity bits have the same polarity, the counter output signal changes when the number of counters changes, and this change increases the integral amount of the auto-zero circuit by a certain amount, and the output of the change detection circuit changes. It is characterized in that when the counter circuit is reset by a signal, the integral amount of the auto-zero circuit decreases by a certain amount and returns to the initial value.

[Implementation row]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block circuit explanatory diagram of a first embodiment of the present invention. The synchronization signal 1g of the AD converter is applied to the terminal 1 and the counter circuit 4. A counter counts synchronization signals. On the other hand, the polarity bit of the analog signal is applied to the change detection circuit 5 from the terminal 2.

The change detection circuit 5 changes the polarity bit of the AD converter from positive to negative.
A reset signal 8t- is outputted to the counter circuit 4 every time there is a change from negative to positive.

For this reason, if the polarity bit manually input to the change detection circuit 5 is fixed to positive, the color/return circuit 4 advances the current by a synchronizing signal, and when a count of 64 is completed, a control # signal is sent to the auto-zero circuit 6. Outputs 7.

The auto-zero circuit 6 is set to J) A speed mode by the control signal 7. In the high-speed mode, the auto-zero circuit 6 increases the amount of integration per time, for example, by about 5 to 500 times as compared to the low-speed mode. Therefore, the amount of change in the output voltage of the auto-zero circuit at one time is 5 to 500 times. For example, if the integrated voltage in low-speed mode is 2011v/time, an offset voltage (for example, 747m
V) t-compensation time is 8kHz for synchronization signal frequency.
(125μ5ec), it takes time.

For example, if the integrated voltage in high-speed mode is 20 times Q, 4 mV
If Z times are used, it becomes possible to compensate for the offset voltage caused by the unbalance of the positive and negative integrals, and the deterioration of the signal-to-noise ratio due to the residual offset voltage can be quickly recovered.

In order to prevent deterioration of the signal-to-noise ratio, it is preferable that the integrated voltage of the auto-zero circuit for one pulse is 1710 or less, which is the minimum step voltage of the AD converter. For this reason, when the offset voltage compensation is completed and the polarity bits start to show positive and negative values, it is preferable that the change detection circuit 5 sets the counter circuit 4 with the reset signal 8 to enter the low speed mode.

The count number of the counter circuit 4 is generally determined from the frequency characteristics of the AD & converter. If the lower limit frequency of the AD converter is 1oo) (z, then positive or negative polarity continues 40 times for each synchronizing signal frequency of 8kHz. Therefore, if the count number of the counter circuit 4 is 64, then )1z analog signal does not operate in high-speed mode, so deterioration of the signal-to-noise ratio due to the auto-zero circuit can be prevented.

FIG. 3 is a block circuit explanatory diagram of a second embodiment of the present invention. In FIG. 3, the same numbers are used for the same functions as in FIG. 1. The counter circuit 4 is composed of an inverter 33, a two-man NAND 31, and 64 counters.

When the reset signal 8 goes to H" level, the counter 32 is reset and the counter output QFi goes to "L" level. The counter 32 counts every time a synchronization signal enters the two-manufactured NAND 31. 64 synchronization signals are manually When this happens, the output Q of the counter 32 goes to the "H" level, and the input Q of the two-man NAND 31 goes to the "L" level via the inverter 33. In this state, the reset signal 8 goes to the ?'H" level and the counter 32 is reset. hold until

Change and production circuit is flip-flop 34 and FxOR35
This circuit is configured to set the reset signal t-″′H” level when the polarity bit changes.

The auto-zero circuit 6 includes current sources I and I, which perform current integration (switch not shown) for each synchronization signal.

In the high-speed mode, when 5vv1, sw is in a conductive state by the control signal 7, current integration (switch not shown) is performed for each synchronizing signal. It has a capacity 45 for holding yff.

The integrated cn voltage is used by the buffer amplifier 44 and attenuator 46 to obtain the optimum auto-zero integrated voltage and output the auto-zero output 3.
More output.

As an example, assume that the integrated voltage is 20 .mu./times and the attenuation ratio of the attenuator 46 is 1150. Assuming that the capacitance value of the capacitor 45 is a value that can be calculated, the integrated charge Q per time is Q = CV = 100 (p, F) x 20 (μV) = Ipti
It can be expressed as Here, ti represents the integration time.

When I p = 10 mA, t1 = 200 ms is obtained.

Normally I = IN = 10mA and high speed mode is 20mA.
If it is doubled, I,;:I,': 190mA, which can be easily achieved.

〔Effect of the invention〕

As explained above, the present invention uses a counter circuit that can be reset by a polarity bit change detection circuit to detect the number of synchronization signals whose polarity bits are of the same polarity, and when this exceeds a set number of times, an auto-zero circuit The auto-zero circuit outputs a control signal to control the high-speed mode, and the auto-zero circuit can quickly compensate for the offset voltage caused by the unbalance of the positive and negative integrated voltages of the auto-zero circuit in the high-speed mode. This has the effect of preventing deterioration of the signal-to-noise ratio even at 9 o'clock.

[Brief explanation of the drawing]

FIG. 1 is a block circuit explanatory diagram of the first embodiment of the present invention,
FIG. 2 is an explanatory diagram of a conventional auto-zero circuit, and FIG. 3 is an explanatory diagram of a block circuit according to a second embodiment of the present invention. 1... Synchronization signal, 2.26... Polarity bit, 3゜27... Auto zero output, 4...
...Counter circuit, 6...Auto zero circuit,
7... Change detection circuit, 8... Reset signal, 21... Analog input, 22...
・Filter, 23...ADf exchange! , 24・Mountain・
・Register, 25...Auto zero circuit, 28.
...Digital output, 31...2 human power N
AND, 32...mark/counter, 33...inverter, 34...flip 7 Rozzo, 35-
・---ExO 几、36、37、38゜39・・・
...'1 Source, 40.41...Switch, 42
...Positive power supply, 43...Negative power supply, 44.
River... Buffer amplifier, 45... Capacity, 46.
...attenuator. To the agent, patent attorney Susumu Uchihara? Mii / Utsuka 2 Male

Claims (1)

[Claims] In an autozero device that integrates the polarity bit of an input signal to compensate for the offset voltage of an AD converter,
a counter circuit for counting the synchronization signal of the converter; a change detection circuit for detecting a change in the polarity bit;
and an auto-zero circuit that integrates polarity bits, and resets the counter circuit when the polarity bit changes according to the output signal of the change detection circuit, and when the polarity bits have the same polarity, the counter circuit resets a certain number of counters. When the change detection circuit exceeds the limit, the counter output signal changes, and this change causes the integral amount of the auto-zero circuit to increase by a certain amount, and when the counter circuit is reset by the output signal of the change detection circuit, the integral amount of the auto-zero circuit decreases by a certain amount. An auto-zero device that is characterized by returning to the initial value.