JPH0640622B2 - Auto zero circuit - Google Patents

Description

The present invention relates to an auto-zero circuit, and more particularly to an auto-zero circuit for compensating an offset voltage of an AD converter.

[Conventional technology]

In an AD converter for converting an analog signal into a digital signal, when a local DA converter and a comparator and a successive approximation type AD converter using a successive approximation register are configured, a DA converter is used.
DC offset voltage of the converter and offset voltage of the comparator are generated. In addition, a band pass filter (BP) for limiting the band to about half the sampling frequency of the AD converter.
F) and a low pass filter (LPF) are used to prevent aliasing noise.

Since the offset voltage generated by this filter is also added to the offset voltage of the AD converter, it is necessary to prevent the deterioration of the signal-to-noise ratio accompanying the increase of the offset voltage.

As a technique conventionally used as this method, it has been considered to compensate the offset voltage of the system by the auto-zero circuit shown in FIG. FIG. 2 shows that an analog signal is input from the analog signal input terminal (Ain) 1 through the band limiting filter 2 for preventing aliasing noise to the AD converter 3
Entered in. The AD converter performs successive comparison to convert an analog signal into a digital signal.

When performing this AD conversion, the polarity bit signal of the AD converter is connected to the auto-zero circuit 7, and the polarity bit is integrated to add an offset voltage to the analog signal input terminal 1 and a local DA converter or comparator. This offset voltage can be compensated by this auto-zero circuit.

[Problems to be solved by the invention]

The above-mentioned conventional auto-zero circuit integrates the polarity bit to compensate the offset voltage of the local DA converter, the comparator, and the band limiting filter.

However, by integrating the polarity bit,
In order to operate the zero circuit and compensate the offset voltage,
A problem arises when the ratio of the relative integration amount between the positive bit integration and the negative bit integration is different.

The current value to be integrated when the polarity bit is positive is I _P, and the current value to be integrated when the polarity bit is negative is I _N. At this time,
Voltage A at the operating point stabilized by the operation of the auto-zero circuit
Is calculated as follows, where V _I is the amplitude of the input analog signal.

When a sine wave (sufficiently larger than the offset voltage of the system) is input to the analog signal input terminal 1 of FIG. 2, the waveform is y = V _I sinx (1) (x = ωt as shown in FIG. The unit is radian), and positive and negative half-waves appear alternately in a cycle of 2π on the X axis. Originally, if such a waveform is converted from analog to digital, the polarity bit of this digital value becomes positive in the case of a positive half-wave, so the positive integrated current value I _{P in} the auto-zero circuit of FIG. When it has a negative half-wave digital value, the polarity bit becomes negative, and the negative integrated current value I _N flows out from the capacitor 56 for π. Therefore, if I _P = I _N , the positive and negative integration amount is I _P × π− _IN × π
= 0, the electric charge of the capacitor 56 becomes zero at the end of each cycle, and the correction by the auto-zero output is not performed.

However, the actual due to variations in IC in the manufacturing process and I _P and I _N is slightly different. If this difference is represented by the ratio α of the positive integrated current value I _P and the negative integrated current value I _N , then α = | I _P | / | I _N | (2) The influence of α will be described.

If I _P > I _N , then I _P × π−I _N × π> 0 when the sine wave of equation (1) is input, so correction is performed by auto-zero output, and I _P flows in. shorter [pi, such correction in a direction to lengthen the period [pi where I _N flows out. As a result of this correction, I _P × (shortened period) -I _N
It is the operating point A (that is, y = A) in FIG. 5 that represents the state where x (longer period) = 0, and this x is x ₁ .

Therefore, from the equation (1), A = V _I sinx ₁ (3) Integration interval of I _P is, _(π-2x 1), the integration interval of _{I N,} since the (π + 2x _1), the balance conditions of the integrated charge _{is, | I P | × (π} -2x 1) = | I _N | × (π + 2x ₁ ) ... (4) When formula (4) is rearranged into the form on the right side of formula (2), And from equation (2) and equation (5) Becomes Rearranging this equation (6) into the form of x ₁ = Substituting equation (7) into equation (3) Becomes Expression (8) shows that the operating point changes depending on the amplitude of the input analog signal. In other words, the stable operating point changes depending on the amplitude V _I of the input analog signal, and operates as an auto-zero circuit that compensates the offset voltage of the system for low-level input signals.
When the amplitude V _I of the input analog signal increases, an offset voltage corresponding to the ratio α of the positive integrated current value | I _P | and the negative integrated current value | I _N |

The problem of the offset voltage generated from the auto-zero circuit caused by the ratio α of the positive and negative integrated current values will be described with reference to FIG.

In the section A of FIG. 7, when the analog input signal is a small signal, the change in the operating point depending on the amplitude shown in the equation (8) can be ignored, and the original offset voltage of the filter 2, the AD converter 3, etc. is automatically zeroed. It is the operating point compensated in.

In section B, the analog input signal changes from a small signal to a large signal, and the change in the operating point proportional to the amplitude shown in equation (8) is added to the above operating point as the amplitude increases, and the operating point changes. I will do it.

In the section C, when the analog input signal changes from the large signal to the small signal and the signal amplitudes of the section A and the section C are the same,
Originally, the operating point should be the same as in the section A, but the compensation residue of the auto-zero circuit generated in the section B becomes a large offset voltage with respect to the analog input signal. Therefore, the signal-to-quantization noise ratio deteriorates due to a large offset voltage, which is a problem.

For example, when the voltage A at the operating point that stabilizes when α = 1.10 and V _I = 1V is calculated from the equation (1), it becomes 74.7 mV, and some measure is required.

[Means for solving problems]

In the auto-zero circuit of the present invention, the input amplitude of the analog signal input to the AD converter is preset in the auto-zero circuit for integrating the polarity bit of the input signal for compensating the offset voltage of the AD converter. It is characterized in that the previous result is held if the limiter value is exceeded, and the integration is performed according to the polarity bit of the input signal when the input amplitude of the analog signal input to the AD converter is less than the limiter value.

〔Example〕

 Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is an explanatory diagram of a block circuit according to the first embodiment of the present invention. In FIG. 1, the same numbers are used for the same parts as in FIG.

In FIG. 1, an analog signal input terminal (Ain) 1 is input to an AD converter 3 through a band limiting filter 2 for preventing aliasing noise. As the AD converter, it is general to use a successive approximation type AD converter composed of a local DA converter (not shown), a comparator (not shown) and a successive approximation register (not shown). The register 4 is a register for storing the result of successive comparison and outputting it as a digital signal from the digital output terminal (D _out ) 5 by an output clock signal (not shown).

The auto-zero circuit 7 receives the polarity bit from the AD converter 3 and performs the integration operation once in the AD conversion cycle. In this embodiment, a digital signal is sent from the register 4 to the limiter circuit 6, and the output digital signal from the register is used to perform the auto operation. -The operation of the zero circuit 7 is controlled.

That is, when the output digital signal of the register 4 exceeds the set limit value, the auto-zero circuit is controlled to hold the previous result without performing the integration operation. When the output digital signal of the register 4 is less than or equal to the set limit value, offset voltage compensation of the filter 2 and the AD converter 3 is performed by performing integration of the auto-zero circuit by the polarity bit of the AD converter 3. .

Next, a brief description will be given with reference to FIG. FIG. 8 shows the case of the same analog input signal as in FIG.

In section A, the analog input signal is a small signal and is the same as in FIG.

In section B, when the analog input signal changes from a small signal to a large signal, and it is assumed that the limiter value is set to V1 at this time, the auto-zero circuit is controlled when the large signal V2 and V3 are input, and the integration is performed. The operation point is held without performing any operation.

In the section C, the compensation residue of the auto-zero circuit is suppressed and the signal-to-quantization noise ratio is improved when the analog input signal changes from a large signal to a small signal.

By controlling the operation of the auto-zero circuit by the limiter circuit in this way, the
The offset voltage is compensated by the action of the zero circuit. By holding the auto-zero circuit operation at a high input level, it is possible to reduce the offset voltage and prevent the generation of the residual offset voltage due to the compensation amount of the positive and negative polarity bits.

An example of this application is a codec with a built-in filter. In the codec with a built-in filter, the AD conversion becomes a non-linear operation, and for example, the operation of the limiter circuit is started by -4.
It is also possible to set it to about 5 dBm0.

FIG. 3 is an explanatory diagram of a block circuit according to the second embodiment of the present invention. FIG. 3 shows an example of a system corresponding to the output terminal 31 of the AD converter and the PCM code used in the audio signal. Registers 41 to 48 are registers for parallel-serial conversion for outputting from the digital output terminal 32.

FIG. 3 is suitable for application to, for example, the μ-law. Since the code rule of the μ-law is folded binary, the same result is obtained depending on whether the polarity bit is positive or negative, except for the polarity bit. Here, the judgments from the second bit to the fourth bit are taken out and input to the limiter circuit 35 (three-input NAND). Here, in the μ rule, when the 2nd to 4th bits are “1,1,1”, −45 dBm0
The following input levels are set, and if the limiter circuit is applied only at this level, the limiter circuit 35 may be a 3-input NAND 34. A limiter operation can be obtained by controlling the auto-zero circuit by the signal from the auto-zero control signal terminal 33.

FIG. 4 is an explanatory view of the third embodiment of the present invention. The difference between FIG. 4 and FIG. 3 lies in the structure of the limiter circuit 50. FIG. 4 shows an auto-zero control signal 51 as a control signal of the limiter circuit 50 and a 4-input NA of the limiter circuit 50.
In FIG. 4 in which the operation signal 49 of the auto-zero circuit is controlled by ND, the auto-zero operation is performed when the 2nd to 4th bits are all "1" and at that time the auto-zero control signal terminal 51 Only when the signal becomes "1", the auto-zero operation by the polarity bit is performed.

By controlling the auto-zero circuit as described above, it is possible to suppress the generation of the offset voltage due to the auto-zero circuit.

〔The invention's effect〕

As described above, the present invention relates to an auto-zero circuit that integrates a polarity bit of an input voltage for compensating an offset voltage of an AD converter, and an auto-zero circuit that uses a limiter circuit according to the amplitude of an input analog signal. By holding the signal or performing the integration depending on the polarity bit, it provides an auto-zero circuit with a limiter according to the input analog voltage, and the deterioration of the quantization noise from the large amplitude input to the small amplitude input. There is an effect that can prevent.

[Brief description of drawings]

FIG. 1 is a block diagram of the first embodiment of the present invention, FIG. 2 is a block diagram of a conventional auto-zero circuit, FIG. 3 is a block diagram of the second embodiment of the present invention, and FIG. FIG. 5 is a block diagram of a third embodiment of the present invention, and FIG.
FIG. 6 is a schematic diagram of an auto-zero circuit, FIG. 7 is an explanatory diagram of a relationship between a large signal, a small signal and an operating point in the prior art, and FIG. 8 is a relationship between a large signal, a small signal and an operating point in the present invention. The respective explanatory views are shown. 1 ... Analog input terminal, 2 ... Filter, 3 ... AD
Converter, 4 ... Register, 5,32 ... Digital output terminal, 6 ... Limiter circuit, 7 ... Auto zero circuit,
31 ... AD output terminal, 33, 51 ... Auto-zero control signal terminal, 35, 50 ... Limiter circuit, 41-48
...... Register, 49 ...... Auto-zero operation signal terminal. 52, 53 ... Current source 54 ... Positive power source 55 ... Negative power source 56 ... Capacity

Claims (1)

[Claims] 1. An AD in which the resolution is set high when the input amplitude of an analog signal is small, and set low when the input amplitude is large.
In an auto-zero circuit that performs integration according to the polarity of the polarity bit of the input signal for compensating the offset voltage of the converter, the input amplitude of the analog signal input to the AD converter is greater than or equal to a preset limiter value. When the input amplitude of the analog signal input to the AD converter is equal to or less than the limiter value, integration is performed according to the polarity bit of the input signal when the analog signal input to the AD converter is equal to or less than the limiter value. .