JP3226657B2 - ΔΣ modulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a .DELTA..SIGMA. Modulator (digital sigma modulator) used for an AD (analog-digital) converter.

[0002]

2. Description of the Related Art One of the oversampling methods, Δ
FIG. 1 shows a basic configuration of a conventional ΔΣ AD converter that performs AD conversion by Σ modulation. The ΔΣ modulator 10 generally includes an integrator for integrating an analog input signal, a quantizer for quantizing an output of the integrator, and a quantized signal output from the quantizer with its polarity inverted and added to the analog input signal. It has an adder. The quantized signal output from the ΔΣ modulator 10 is converted as an AD conversion output by the digital filter 20 into a digital signal corresponding to the analog input signal.

In a ΔΣ AD converter operating under a constant power supply voltage, a state variable value which is an integrator output inside the ΔΣ modulator 10 oscillates (amplitude increase phenomenon) in response to an excessive signal input having a large absolute value. And the linearity of the transformation is lost,
The SN ratio (signal-to-noise ratio) may decrease, or oscillation may continue even after the input returns to the normal operation range. Furthermore, in an AD converter for AD-converting an AC (alternating current) signal, it is preferable to remove the offset of the input signal from the viewpoint that it is necessary to support an AC signal input as large as possible.

FIG. 2 shows an example of a conventional circuit configuration for removing an offset. The removal of the offset of the input signal is performed by passing the input signal through a high-pass filter 30 before entering the ΔΣ modulator 10. In this case, the output (y) of the ΔΣ modulator 10 becomes the input (x)
(X ') from which the offset is removed
And the offset (O) generated by the ΔΣ modulator 10 itself.
S), that is,

[0005]

Y = x ′ + OS (1) However, here, a high-frequency component in noise that has been noise-shaped by the ΔΣ modulator 10 is not considered.

[0006]

The conventional ΔΣ AD converter has a problem that the offset generated by the ΔΣ modulator itself is added to the output of the ΔΣ modulator as described above.

In view of the above, an object of the present invention is to provide a ΔΣ modulator that can remove not only an offset of an input signal but also an offset generated by the ΔΣ modulator itself.

[0008]

In order to achieve the above object, the present invention provides a first integrating means for integrating an analog input signal, a quantizing means for quantizing an output of the first integrating means, First adding means for inverting the polarity of the output of the quantizing means and adding the result to the analog input signal, second integrating means for integrating the output of the quantizing means, and output of the second integrating means And a second adding means for inverting the polarity of the signal and adding the inverted signal to the analog input signal.

[0009]

The operation of the present invention will be described below in detail with reference to the drawings. FIG. 3 shows a basic configuration of the present invention. In FIG. 3, 1
Reference numeral 00 denotes a circuit portion having a configuration similar to that of the above-described conventional Δ 前述 modulator 10, a first integrator 11 for integrating an analog input signal, a quantizer 12 for quantizing an output of the first integrator 11, and a quantizer 12. A first converter for converting an output of the detector 12 into an analog signal with reference to a first reference signal (VREF1)
(Digital / analog) converter 13 and the first D
It has a first adder 14 that adds the output of the A converter 13 to the analog input signal (the polarity is negative). Reference numeral 41 denotes an output of the quantizer 12 as a second reference signal (VREF2).
A second DA converter that converts the analog signal into an analog signal with reference to
42 is a second integrator that integrates the output of the second DA converter 41, and 43 is a second adder that adds the output of the second integrator 42 to the analog input signal (negative polarity). is there. As described above, the ΔΣ modulator of the present invention is configured by adding the DA converter 41, the second integrator 42, and the second adder 43 to the circuit portion 100 similar to the above-described conventional example.

FIG. 4 shows the input / output relationship of signals in the above basic configuration. y is the output from the ΔΣ modulator.
The OS includes various frequencies other than the offset in the input noise of the ΔΣ modulator. However, high frequency components are not considered. It is also assumed that the integrated value of the high-frequency component in the integrator becomes zero. The following equation (2) is established from FIG.

[0011]

(Equation 2)

In the above equation (2), S (= jω) ≒ 0,
In other words, for low frequency components,

[0013]

(Equation 3)

## EQU1 ##

Therefore, when the signal is close to the DC component, y ≒ 0
Becomes Since x is an input signal (alternating current) and an offset, and OS is mainly a DC component, the offset of x and OS become ≒ 0 in the above equation (2), and only the signal component of x is output. As described above, the low frequency component is also removed from the input signal (x), the low frequency component is similarly removed from the offset (OS) of the ΔΣ modulator, and the output y of the ΔΣ modulator becomes only the x signal component.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 5 shows a circuit configuration of a ΔΣ modulator according to an embodiment of the present invention. The .DELTA..SIGMA. Modulator of this example is realized as an LSI (Large Scale Integrated Circuit) using a CMOS process, and each switch is made of a transfer gate using a MOS transistor. S in the figure
1 and S2 represent switching signals applied to each switch.
The ΔΣ modulator of this example is composed of a second-order ΔΣ modulator circuit portions 111 to 115 formed by a switched capacitor circuit (hereinafter abbreviated as an SC circuit) and a second reference signal (VREF) whose polarity is controlled by its output.
2) Integrator with SC circuit 117 for integrating (118)
And its integrator output to the input signal (negative polarity)
The SC circuit 119 performs the following.

The SC circuit 111 and 113 are equivalent to each resistor constituting the first integrator 11 of FIG. 3 in the operational amplifier 112 and the capacitor C _5, C _8. 11
Reference numeral 5 denotes a comparator constituting the quantizer 12 of FIG. 3, which gates an input clock signal with an integrator output at a point a to generate a binary quantized signal of "1" and "0". The SC circuit 116 corresponds to the first DA converter 13 and the first adder 14 in FIG. SC circuit 117, constituting the operational amplifier 118 and capacitor C ₁₀ in the second DA converter 41 in FIG. 3 the second integrator 42. The SC circuit 119 corresponds to the second adder 43 in FIG.

FIG. 6 is a timing chart showing signal timings and waveforms of the circuit of FIG.

In the experimental example of this embodiment, the output frequency of the ΔΣ modulator and the operating frequency of the switch of the SC circuit are each 512 kHz, the output rate at the time of outputting the digital filter is 8 kHz, and the low frequency of the input and the ΔΣ modulator is 16 Hz. It was configured to attenuate. As a result, when the digital filter output was a 14-bit output, it was confirmed that the offset could be reduced to a point where the offset could not be detected.

(Second Embodiment) FIG. 7 shows another configuration example in which the output of the second integrator is added to the signal at the input of the ΔΣ modulator (the polarity is negative). In this example, the left end of the capacitor C ₁ of the SC circuit 111 for introducing the analog input signal to the ΔΣ modulator is adapted to connect to alternate between the input signal and the second integrator output, thereby, ( An electric charge of (input signal−output of second integrator) × C ₁ is input to the first integrator of the ΔΣ modulator.

This embodiment has an advantage that the total number of the capacitors C ₄ constituting the SC circuit 119 and the switches connected thereto can be reduced by four as compared with the first embodiment of FIG.

(Other Embodiments) In the above-described embodiment of the present invention, it is possible to increase or decrease the order of the ΔΣ modulator and the integrator. It is also possible to build a system with a continuous time axis by assembling with passive components such as a vessel and a capacitor. Further, in the above-described embodiment of the present invention, voltage is used as an input and each state variable in the Δ 、 modulator, but current and charge can be used as a signal expression medium. Also,
VREF1 and VREF2 of the reference signal (voltage) may have different values or a common value.

[0024]

As described above, according to the present invention,
Since the output obtained by integrating the output of the ΔΣ modulator by the integrator is inverted and added to the input signal at the input section of the ΔΣ modulator, not only the offset of the input signal but also the offset of the ΔΣ modulator can be removed at the same time. The effect is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a conventional ΔΣ AD converter.

FIG. 2 is a block diagram showing a configuration of another conventional ΔΣ AD converter.

FIG. 3 is a block diagram showing a basic configuration of the present invention.

FIG. 4 is a diagram illustrating a relationship between signals in FIG. 3;

FIG. 5 is a circuit diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 6 is a timing chart showing timings and waveforms of the signals in FIG.

FIG. 7 is a circuit diagram showing a circuit configuration of another embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 10 ΔΣ modulator 11 First integrator 12 Quantizer 13 First DA converter 14 First adder 20 Digital filter 41 Second DA converter 42 Second integrator 43 Second adder 100 Conventional ΔΣ modulator circuit portion similar to 111, 113, 116, 117, 119 Switched capacitor circuit 112, 114, 118 Operational amplifier 115 Comparator

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 3/02 H03M 1/10

Claims (1)

(57) [Claims] A first integration means for integrating an analog input signal; a quantization means for quantizing an output of the first integration means; a polarity inversion of an output of the quantization means; First adding means for adding to the signal; second integrating means for integrating the output of the quantizing means; and second means for inverting the polarity of the output of the second integrating means and adding the output to the analog input signal. .DELTA..SIGMA. Modulator comprising: