JPS62287736A - Synchronizing serial transfer system - Google Patents

Abstract

PURPOSE:To improve the transfer efficiency by retarding a serial data from a data transmission side by 1/2 clock period, transferring the result to a data reception side so as to quicken the data latch timing at the data reception side. CONSTITUTION:A data 11 to be sent in a data transmitter 1 is loaded in a shift register 7 as a parallel data and transferred to a re-timing device 3 via a data line 4 as a serial data. The serial data is transferred to a data receiver 2 via a data line 5 while it is retarded by 1/2 clock. Then it is possible to fetch the serial data at the leading faster than the trailing of the clock signal by 1/2 clock period at the data receiving side. Thus, the transfer efficiency is improved.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a synchronous serial transfer method in which retiming is performed by reducing delay time.

[Conventional technology]

A well-known and widely used synchronous serial transfer method is a serial transfer method between a terminal device and a modem using an R5-232G interface. Here, the synchronous serial transfer sequence using the data line and clock line is shown in Figure 3 (a) and (b).
This can be explained by:

From the data transmission bag W1 to the data receiving device 2, serial data and
A clock signal is transferred. The data transmitting device 1 changes serial data at the rising edge of a clock signal, while the data receiving device 2 latches the serial data at the falling edge of the clock signal.

In addition, in the signal line name in the R8-232G interface, the serial data on data line 4 is the transmission data (
abbreviation BA) or received data (abbreviation BB), and a clock! ! The tarok signal on X6 corresponds to the transmission signal element timing (abbreviation D71) or the reception signal element timing (abbreviation [), respectively.

Publicly known documents regarding this P-232C interface include, for example, Basics and Practice of Microcomputer Data Transmission J (Section 3.2: R9-232C (pages 67-78), written by Hajime Miyazaki, CQ Publishing Sugi, 1984) ) can be mentioned.

Now, such a synchronous serial transfer sequence has the following problems. This is because if the transfer is long or the transfer speed is large and the phase shift between the clock signal and data signal can be ignored due to variations in α delay or element delay, retiming may be necessary during the transfer. 4
That's what it means.

The system configuration and transfer sequence when retiming is performed are shown in FIGS. 4(a) and 4(b). As shown in FIG. is delayed by one clock period T and output on the data (data) 5. In this case, it is a biography.

[The interlayer point that the invention attempts to solve]

As described above, in conventional timing devices, serial data is delayed by one crotter cycle, but depending on the data transfer mode, the transfer efficiency inevitably decreases as the data is transferred. In particular, the problem becomes more pronounced as the number of bits transferred per transmission is smaller.

An object of the present invention is to provide a synchronous serial transfer method in which the transfer efficiency is not significantly reduced even when the number of transfer bits is small.

Although it is inevitable that there will be delays in retiming the structure [means to solve the problem],
By advancing the data latch timing line on the data receiving side by 1/2 clock cycle on the assumption that retiming is performed, the delay due to retiming can be shortened to 1/2 clock cycle.

In other words, the above purpose is to delay the serial data from the data transmitting side by 1/2 clock cycle by retiming and then transfer it to the data receiving side, and on the data receiving side, the serial data is delayed by 1/2 clock cycle. This is accomplished by latching.

[Effect]

For example, when serial data is transferred from the data sending side as data that changes in synchronization with the rising edge of a clock signal,
The serial data is delayed by 1/2 clock cycle by the retiming device and then transferred to the data receiving side. In this case, the data determination point for each serial data delayed by 1/2 clock period is the rising edge of the clock signal, so on the data receiving side, the rising point is 1/2 clock period earlier than the falling edge of the clock signal. This makes it possible to import serial data at any time.

〔Example〕

The present invention will be explained below with reference to FIGS. 1 and 2.

First, the general configuration of a timing device and a sending/receiving device according to an example of the present invention will be explained with reference to FIG. The retiming device 3 according to the present invention includes a trailing edge trigger D-type flip-flop 9 as a 1-bit shift register, and the data receiving device 2 further includes a serial-in/parallel-out shift register 8. It has become. In the data transmitting device 1, data 11 to be transmitted is loaded into a shift register 7 as parallel data.

The serial data is transferred to the retiming device 3 via the data line 4, while the serial data is transferred from the retiming device 3 to the data receiving device 2 via the data line 5 in a state delayed by 1/2 clock cycle. This is what is meant to be done.

FIG. 2 shows an example of the input/output signal waveforms at the main part when the data 11 is 8 bits. To explain the operation in this way, data 11 to shift register 7
The presetting can be performed at the rising edge of the transfer clock signal 13 while the load signal 12 is being input.

When the load signal 12 is no longer input, the shift register 7
is placed in shift mode, and data 11 is transferred from the shift register 7 using the transfer clock signal 13 as a shift clock.
is output as serial data, and the glock signal CLK to the retiming device 3 and data receiving device 2 is obtained by ORing the transfer clock signal 13 and the load signal 12 using an OR gate 10.

As a result, the serial data from the shift register 7 is determined at the falling edge of the clock signal CLK, and changes at the rising edge of the clock signal CLK.

Now, the serial data from the shift register 7 is sent to the flip-flop 9 by the retiming device 3 using the clock signal CL.
The setting timing depends on the falling edge of the clock signal CLK. As a result, the serial data is finally obtained from the flip-flop 9 with a delay of 1/2 clock period. Since each piece of serial data after this delay is determined at the rising edge of the clock signal CLK, if the clock signal CLK is used as a shift clock and is shifted into the shift register 8, the data 11 will be transferred from the shift register 8 when the transfer is completed. is obtained as 8-bit parallel data 14. When inverting the phase of the clock signal CLK, the data transmitting device 1 changes the serial data at its falling edge, the retiming device 3 sets the serial data at its rising edge, and the data receiving device 2 changes the serial data at its falling edge. All you have to do is import the subsequent serial data.

Note that in the above examples, the clock signal is transferred on the clock line only during serial transfer, but it may be transferred all the time. In this case, the data receiving side should be separately notified of the transfer start and end timing. Bye.

Considering the effect of the present invention, the time required for serial transfer of 4-bit data and 8-bit data according to the prior art is 6 and 10 clock cycles, respectively. However, since the serial transfer time according to the present invention is 5.5 and 9.5 clock cycles, respectively, 8.3%
, a reduction of 5% can be achieved. In addition, in the conventional technology, two flip-flops were required to generate a delay of one clock cycle in the timing device, but according to the present invention, it is only necessary to generate a delay of 1/2 clock cycle. Therefore, only one is enough.

〔Effect of the invention〕

As explained above, according to the present invention, even when the number of transfer bits is small, the transfer efficiency is not significantly lowered, and data can be transferred economically.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a system configuration of an example of a transfer system including a retiming device according to the present invention. FIG. 2 is a diagram showing an example of input/output signal waveforms in the main part,
FIGS. 3(a) and (b) are diagrams for explaining a general synchronous serial transfer method, and FIGS. 4(a) and (b) are diagrams showing the system configuration of a synchronous serial transfer system according to the prior art. , is a diagram showing an example of a transfer sequence. 1... Data transmitting device, 2... Data receiving device, 3
... Retiming device, 4, 5... Data line, 6.
...Clock line, 9... Trailing edge D type flip-flop.

Claims (1)

[Claims] 1. A synchronous serial transfer method in which serial data is transferred from the data sending side to the data receiving side together with a clock signal via a retiming device, in which the data is transferred from the data sending side in synchronization with either the rising or falling edge of the clock signal. The serial data that has been updated and transferred is temporarily stored by a retiming device at the falling edge or rising edge of the clock signal, and then transferred to the data receiving side,
A synchronous serial transfer method characterized in that on the receiving side, serial data from the retiming device is taken in at the rising edge or falling edge of the clock signal.